JP2007157844A - Semiconductor device, and method of manufacturing same - Google Patents

Semiconductor device, and method of manufacturing same Download PDF

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JP2007157844A
JP2007157844A JP2005348216A JP2005348216A JP2007157844A JP 2007157844 A JP2007157844 A JP 2007157844A JP 2005348216 A JP2005348216 A JP 2005348216A JP 2005348216 A JP2005348216 A JP 2005348216A JP 2007157844 A JP2007157844 A JP 2007157844A
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semiconductor device
formed
electrode terminal
hole
terminal pattern
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Maki Okabe
真樹 岡部
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Sharp Corp
シャープ株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device along with its manufacturing method, capable of reducing the size of a semiconductor device while discarding the heat generated when the semiconductor device is operated. <P>SOLUTION: A semiconductor device 100 is provided on a ground plane, in which wiring and electrode terminal patterns 104 and 106 are formed on a semiconductor wafer 102. A conductive hole 108 is so formed at the semiconductor wafer as to penetrate the electrode terminal pattern provided at such portion of the electrode terminal pattern as an electrode terminal pattern is formed connecting to the ground plane. A hole 110 whose aperture is such dimension as can include bottoms of the conductive hole is formed on the semiconductor wafer, so that it reaches a bottom 108a of the conductive hole from a surface 102b on the side opposite to a surface 102a where the wiring and electrode terminal pattern of the semiconductor wafer are formed. The hole is provided with one conductor 112 which electrically connects the bottom parts and the ground plane. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置、および斯かる半導体装置の製造方法に関し、特に、半導体装置の配線・電極形成工程後に斯かる半導体装置を組み立てる組立工程における電極端子の形成・接続方法に関する。 The present invention relates to a semiconductor device, and to a method of manufacturing such a semiconductor device, particularly to a forming and a method of connecting the electrode terminals in the assembly process of assembling a semiconductor device such after the wiring electrode formation process of the semiconductor device.

従来からの半導体製造工程では、完成した半導体ウエハから個々のチップを切り出した後に外部要因によるこれらチップ損傷からの保護、水分混入等による腐食防止を目的とした上で取り扱いを考慮した電気的な接続端子を形成するために、各種のパッケージ形状による半導体組立工程を実施している。 The semiconductor manufacturing process from conventional finished protection from these chip damage due to external factors after cutting out the individual chips from a semiconductor wafer, electrical connection in consideration of handling upon for the purpose of corrosion prevention due to water contamination, etc. to form the terminal, it has implemented a semiconductor assembly process according to various package shapes.

また、薄層、分割化された斯かるチップに対しての半導体組立工程においても、その方法はさまざまであり、とりわけ電極端子形成方法では、ワイヤボンディング、フリップチップボンディングと大きく二つの方法がある。 Further, the thin layer, in the semiconductor assembly process with respect to segmentation has been such chips, the method is varied, with especially the electrode terminal forming method, there is wire bonding, flip chip bonding and two broad ways.

ワイヤボンディングによる電極端子形成方法では、図8に示すように、チップの電極取出端子106とリードフレーム(図示せず)のリード間に直径数十μm程度の細いAuまたはAl線118を使用して接続する方法であり、フリップチップボンディングによる電極端子形成方法では、図9に示すように、チップの電極端子106にバンプ119と呼ばれる柱状電極を形成してから、矢印で示す半導体装置の実装方向に移動させて一括して実装用基板(図示せず)と斯かるバンプ119を直接的に接続する方法であり、半導体電極部とこれを実装する基板とを最短距離で実装接続を行うことができる方法である。 The electrode terminal forming method by wire bonding, as shown in FIG. 8, using a thin Au or Al lines 118 of several tens μm diameter of about between the leads of the chip electrode lead terminal 106 and the lead frame (not shown) a method of connecting, in the electrode terminal forming method according to the flip chip bonding, as shown in FIG. 9, after forming columnar electrodes called bumps 119 on the chip electrode terminals 106, the mounting direction of the semiconductor device shown by the arrow substrate for mounting collectively by moving to a method of directly connected (not shown) and such bump 119, it is possible to perform mounting connection at the shortest distance and the substrate to a mounting this semiconductor electrode portion it is a method.

しかしながら、従来のワイヤボンディングによる電極端子形成方法では、各ワイヤボンディング用電極端子とリードフレーム側での対応する端子間でそれぞれ個別にワイヤボンディングを行うために、高機能、多機能化によるLSIの高集積化に伴って、電極端子の多数化が進むため、一つのチップに対するワイヤボンディングの本数が増加してしまう。 However, in the conventional wire bonding by the electrode terminal forming process, in order to correspond to individually wire bonding between the terminals of each wire bonding electrode terminals and the lead frame side, high-performance, the LSI by multifunctional high with the integration, since a large number of the electrode terminals progresses, the number of wire bonding is increased with respect to one chip. このため、ワイヤボンディング用電極端子の寸法およびワイヤボンディング用電極端子の数、ワイヤボンディング用電極端子とワイヤボンディング用電極端子同士の間隔が考慮される結果、これら要因が半導体チップの外周寸法を決定してしまうことより、LSIの高集積化に伴い、これらを実装する半導体装置のサイズの小型化が困難になる。 Therefore, as a result of the number of dimensions of the wire bonding electrode Wire bonding electrode terminals, distance between electrode terminals and the wire bonding electrode terminal wire bonding are considered, these factors will determine the outer periphery dimensions of the semiconductor chip than it would, with high integration of LSI, the size reduction in size of the semiconductor device implementing these is difficult.

また、フリップチップボンディングによる電極端子形成方法では、接続対象物との熱膨張などによる接続部の応力的問題を解消するために、特殊材料を使用したバンプや接着材の開発が不可欠となることと、フリップチップボンディングによる実装後のバンプやパッドの状態の接続部分を確認することが困難となることが課題となっている。 Further, the electrode terminal forming method according to the flip chip bonding, in order to solve the stress problem in the connecting portion due to thermal expansion of the connection object, and that the development of the bump and the adhesive material using special materials is indispensable , there lies a challenge can see the connecting portion of the bump and the pad state after mounting by flip chip bonding becomes difficult.

上記の課題を解決する従来技術として、半導体装置の電極端子の形成をするに際し、配線層間のコンタクトを簡便な工程で歩留まり良く良好に形成する方法として、特許文献1には、半導体基板上に第1の配線構体を構成し、この第1の配線構体上に絶縁層を介して第2の配線構体を構成し、第1の配線構体と第2の配線構体とを接続する第3の配線構体が凹部を有する金属と、斯かる凹部に埋め込まれた絶縁物とから構成されることを特徴とする配線構体が開示されている。 As a conventional technique for solving the above problems, when the formation of the electrode terminals of the semiconductor device, as a method of contact between wiring layers a good yield well formed by a simple process, Patent Document 1, first on a semiconductor substrate constitute one of the wiring structure, this first wiring structure on constitutes a second interconnection structure via an insulating layer, a first wiring structure and the third wiring structure for connecting the second wiring structure There is disclosed a wiring structure, characterized in that they are composed of a metal having a recess, and embedded in such recess insulator. これによって、配線の多層化、配線容量の低減、配線間干渉の低減を図り、高性能かつ小形な通信用混成IC等の半導体アナログ集積回路及びデジタル集積回路等を提供することができる。 Thus, multi-layered wiring, a reduction in wiring capacitance, achieving a reduction of inter-wiring interference, it is possible to provide a high-performance and semiconductor analog integrated circuits such as a small-sized communication hybrid IC and digital integrated circuits.
特開平7−142577号公報 JP-7-142577 discloses

しかしながら、上述の配線構体を備える半導体装置は、層間絶縁膜の厚さが大きくなっても配線層間のコンタクトを簡便な工程で歩留まり良く良好に形成することによって、高性能かつ小型な半導体アナログ集積回路等を提供できるものの、半導体装置が高性能かつ小型化するに伴って、斯かる半導体装置の動作時の発熱が小型化した半導体装置にかかる負荷が大きくなる。 However, the semiconductor device including the above-described wiring structure, by high yield satisfactorily formed in even thickness increases simple contact between wiring layers process of the interlayer insulating film, compact, high-performance semiconductor analog integrated circuit although such can provide, with the semiconductor device is high-performance and miniaturization, the load applied to the semiconductor device during operation of the heating of such a semiconductor device is miniaturized increases. 斯かる熱が半導体装置に滞留することによって、半導体装置がヒートアップして、上記回路の機能が低下することが問題となる。 By such heat is retained in a semiconductor device, a semiconductor device is heating up, the function of the circuit is reduced becomes a problem.

本発明は、従来の半導体装置が有する上記問題点に鑑みてなされたものであり、本発明の目的は、半導体装置の小型化を実現すると同時に、半導体装置の動作時の発熱を廃棄することの可能な、新規かつ改良された半導体装置および斯かる半導体装置の製造方法を提供することである。 The present invention has been made in view of the above problems of the conventional semiconductor device, object of the present invention, at the same time to realize the miniaturization of the semiconductor device, the discarding heat generation during operation of the semiconductor device possible to provide a method for producing a new and improved semiconductor device and such a semiconductor device.

上記課題を解決するために、本発明のある観点によれば、接地面に設けられ、半導体ウエハ上に配線および電極端子パターンが形成されている半導体装置において、かかる電極端子パターンのうち、接地面と接続する電極端子パターンが形成されている部位には、かかる部位に設けられた電極端子パターンを貫通するようにして半導体ウエハに導通孔が形成され、半導体ウエハには、この半導体ウエハの配線および電極端子パターンが形成されている面と反対側の面から導通孔の底部に達するまで、径が導通孔の各底部を包含可能な大きさである孔部が形成され、かかる孔部には各底部および接地面を電気的に接続する一の導電体が設けられていることを特徴とする、半導体装置が提供される。 In order to solve the above problems, according to an aspect of the present invention, provided on the ground plane, a semiconductor device wiring and the electrode terminal pattern on a semiconductor wafer is formed, out of such electrode terminal pattern, a ground plane and the site where the electrode terminal pattern to be connected are formed, through hole in the semiconductor wafer is formed so as to penetrate the electrode terminal pattern provided on such sites, the semiconductor wafer, the semiconductor wafer interconnection and the surface on which the electrode terminal pattern is formed from the surface opposite to reach the bottom of the through hole, the hole is a size that can encompass the bottom of the diameter of the introducing hole is formed, for such holes each wherein the first conductor electrically connects is provided a bottom and a ground plane, a semiconductor device is provided.

このとき、一の導電体は、成膜加工により形成されている導電性のめっきであることとしてもよい。 In this case, one conductor, it is also possible that a conductive plating formed by a deposition process.

このような構成とすることにより、接地面に対応する電極端子と半導体装置の裏面側から接地面に有するリードフレームへ一の導電体を介して直接的に接続することが可能となるので、半導体装置組立工程でのワイヤボンディングにおけるワイヤーの本数およびワイヤボンディング用電極端子数が低減できる。 With such a configuration, it becomes possible to directly connect via one of the electrical conductors from the rear surface side of the electrode terminals of the semiconductor device corresponding to the ground plane to the lead frame having a ground plane, a semiconductor device number and the wire bonding electrode terminals of each wire in the wire bonding in the assembly process can be reduced. このため、電極端子の外周寸法が縮小可能となるので、半導体装置の小型化に伴う高密度化・高性能化が実現される。 Therefore, since the outer peripheral dimension of the electrode terminal is reducible, high density and high performance due to miniaturization of the semiconductor device can be realized.

また、半導体装置の接地面と対応させる電極端子は、接地面と接する半導体装置の裏面側に設けた金属系のほうが半導体ウエハを構成する半導体材料に比べて熱伝導率が高い金属製の一の導電体からなる大口径な電極端子を介して接地される。 The electrode terminals to correspond to the ground surface of the semiconductor device, the ground plane in contact with the semiconductor device back side provided with better thermal conductivity is high metallic one as compared with the semiconductor material constituting the semiconductor wafer of the metal-based It is grounded through a large-diameter electrode terminals made of a conductor. このように、ウエハの表面側に設けられた電極等より表面積の大きい大口径な電極端子をウエハの裏面側から設けるので、半導体装置の動作時に接地面に接続される電極端子が発熱する場合でも、斯かる熱が接地面との接続媒体となる半導体装置の裏面側に設けた大口径な電極端子により多くの熱エネルギーが吸収されることによって分散される。 Thus, the larger the large-diameter electrode terminals of the surface area than the electrode or the like provided on the surface side of the wafer so provided from the back side of the wafer, even when the electrode terminal connected to the ground surface during operation of the semiconductor device generates heat is distributed by such heat is more heat energy absorbed by the large-diameter electrode terminals arranged on the back surface side of the semiconductor device to which the connection medium to the ground plane. このため、半導体装置動作中に発生する熱エネルギーが大口径な裏面側電極端子を通じてリードフレーム等の実装用基板側に伝わり半導体装置そのものに熱がこもりにくくなる。 Therefore, heat is hardly confined to the semiconductor device itself transmitted to the mounting board side such as a lead frame through the thermal energy generated in the semiconductor device operating a large-diameter backside side electrode terminals. すなわち、半導体装置の動作時の廃熱効果を高めることができ、半導体装置のヒートアップにより、かかる半導体装置を備えた半導体アナログ集積回路等の機能の低下を防ぐことができる。 That is, it is possible to improve the waste heat effect during operation of the semiconductor device, the heat-up of the semiconductor device, it is possible to prevent deterioration of the function of such a semiconductor analog integrated circuit having such a semiconductor device.

上記課題を解決するために、本発明の別の観点によれば、接地面に設けられた半導体装置の半導体ウエハ上に配線および電極端子パターンを形成する工程後に、半導体装置を組み立てる工程を含む半導体装置の製造方法において、電極端子パターンが形成される面のうち、接地面と接続する電極端子パターン以外の部分を一のレジストで被膜する工程と、一のレジストで被膜されていない電極端子パターンを貫通するようにして半導体ウエハに導通孔を形成する工程と、電極端子パターンが形成される面の反対側の面に導通孔の各底部を包含可能な大きさの孔部を形成する部位以外に他のレジストを被膜する工程と、半導体ウエハの他のレジストで被膜されていない部位を半導体ウエハの反対側の面から導通孔の底部に届くまでエッチング処 In order to solve the above problems, according to another aspect of the present invention, after the step of forming the wiring and the electrode terminal pattern on a semiconductor wafer of a semiconductor device provided on the ground plane, the semiconductor comprising the steps of assembling the semiconductor device the method of manufacturing a device, among the surfaces of the electrode terminals pattern is formed, a step of coating a portion other than the electrode terminal pattern to be connected to the ground plane in one of the resist, an electrode terminal patterns which are not coated with one resist forming a through hole in the semiconductor wafer so as to penetrate, in addition site to form the size of the hole that can encompass the bottom of the through hole on the opposite side of the surface on which the electrode terminal pattern is formed a step of coating the other resist, etching processing sites that are not coated with another resist of a semiconductor wafer from the opposite side of the semiconductor wafer to reach the bottom of the through hole をする工程と、かかるエッチング処理により形成された孔部に導通孔の各底部および接地面を導通可能にするための一の導電体を設ける工程と、これら一のおよび他のレジストを除去して、形成された半導体装置の薄層化を行う工程と、を含むことを特徴とする、半導体装置の製造方法が提供される。 A step of and a step of providing an electrical conductor for allowing conduction of each bottom and the ground plane of the communication hole in the hole formed by the etching process, to remove these one and the other resist characterized in that it comprises a step of performing thinning of the formed semiconductor device, the method of manufacturing a semiconductor device is provided.

このとき、一の導電体は、導電性のめっきを所望の厚さになるまで成膜することにより形成されることとしてもよい。 In this case, one conductor may be be formed by depositing a conductive plating to the desired thickness.

このような構成とすることにより、半導体装置に設けられる接地面に接続する電極端子と接地面とを電気的に直接接続する導電体を設けることが容易にできるので、従来使用されていた半導体装置組立工程でのワイヤボンディングにおけるワイヤーの本数およびワイヤボンディング用電極端子数が低減され、半導体装置の小型化に伴う高密度化・高性能化が実現される。 With such a configuration, it an electrode terminal connected to the ground plane and the ground plane is easily possible to provide a conductor connecting electrically directly provided in the semiconductor device, a semiconductor device which is conventionally used the number and the wire bonding electrode terminals of each wire is reduced in the wire bonding in the assembly process, higher density and higher performance due to miniaturization of the semiconductor device can be realized. とりわけ、上記導電体を導電性のめっきを所望の厚さになるまで成膜する方法を使用することにより、かかる導電体を容易に形成できる。 Especially, the conductor by using a method of forming a conductive plating to the desired thickness can be easily formed such conductor.

以上説明したように本発明によれば、半導体装置組立工程でのワイヤボンディングにおけるワイヤー本数を低減することができる。 According to the present invention described above, it is possible to reduce the wire number in the wire bonding in the semiconductor device assembly process. また、ワイヤボンディング用電極端子数の低減により、電極端子の外周寸法の縮小によって、半導体装置の寸法を縮小し、小型化することができる。 Moreover, by reducing the electrode for wire bonding number of terminals, by the reduction of the peripheral dimensions of the electrode terminals, to reduce the size of the semiconductor device can be miniaturized. さらに、半導体装置の動作時における発熱を廃棄する廃熱効果が高まる。 Further increases the waste heat effect of discarding the heating during the operation of the semiconductor device.

以下に添付図面を参照しながら、本発明の好適な実施の形態について詳細に説明する。 Reference will now be described in detail preferred embodiments of the present invention. なお、本明細書および図面において、実質的に同一の機能構成を有する構成要素については、同一の符号を付することにより重複説明を省略する。 In the specification and drawings, components having substantially the same function and structure are a repeated explanation thereof by referring to the figures.

まず、本発明の半導体装置の構成について、図面を使用しながら説明する。 First, the configuration of a semiconductor device of the present invention will be described with reference to the drawings. 図1は、本発明の半導体装置の一実施形態の模式的な断面図である。 Figure 1 is a schematic cross-sectional view of one embodiment of a semiconductor device of the present invention. 本実施形態の半導体装置100は、GaAsやSi等からなる半導体ウエハ102の上に、CuやAl等からなる配線パターン104および電極端子パターン106がスパッタ法や蒸着法等により形成されている。 The semiconductor device 100 of this embodiment, on the semiconductor wafer 102 made of GaAs or Si or the like, the wiring pattern 104 and the electrode terminal pattern 106 made of Cu or Al or the like is formed by sputtering or evaporation. 電極端子パターン106のうち、リードフレーム等の電気信号をやり取りする際の基準電位(0V)とみなされる接地面(以下、GNDと称する)と接続する電極端子パターン106が形成されている部位には、かかる部位に設けられた電極端子パターン106を貫通するようにして半導体ウエハ102に導通孔となるVIAホール108がエッチング等により形成されている。 Of the electrode terminal pattern 106, a ground plane which is regarded as the reference potential when exchanging an electrical signal such as a lead frame (0V) to the site where the electrode terminal pattern 106 connecting (hereinafter, referred to as GND) and it is formed , VIA holes 108 in a conductive hole in the semiconductor wafer 102 so as to penetrate the electrode terminal pattern 106 provided on such sites are formed by etching or the like.

半導体ウエハ102の配線パターン104および電極端子パターン106が形成されている面102aと反対側の面となる裏面102bには、VIAホール108の各底部108aを包含可能な大きさの径を有する孔部である大口径ホール110が設けられ、この大口径ホール110は、半導体ウエハ102の裏面102bからVIAホール108の底部108aに達するまでの深さを有する。 On the back surface 102b of the surface 102a of the wiring pattern 104 and the electrode terminal pattern 106 of the semiconductor wafer 102 is formed opposite to the surface, the hole having a diameter of each bottom portion 108a capable inclusion size of VIA holes 108 large diameter hole 110 is provided is, the large-diameter hole 110 has a depth from the back surface 102b of the semiconductor wafer 102 to reach the bottom portion 108a of the VIA holes 108. この大口径ホール110には、VIAホール108の各底部108aおよびGNDを電気的に接続するための一の導電体として裏面側電極端子用メタル112が設けられている。 This large-diameter hole 110, the rear surface side electrode terminals for metal 112 as a conductor for electrically connecting the respective bottom portions 108a and GND VIA holes 108 are provided. この裏面側電極端子用メタル112は、本実施形態では、後述するように金(Au)等の導電性の大きい金属からなる導電性のめっきの成膜加工により形成されている。 The backside electrode terminal metal 112, in this embodiment, are formed by a deposition process of a conductive plating formed of an electrically conductive high metals such as gold (Au) as described below.

このように、GNDに対応する電極端子106と半導体装置100の裏面側からGNDとなるリードフレーム(図示せず)へ裏面側電極端子用メタル112を介して直接的に接続できるので、半導体装置組立工程でのワイヤボンディングにおけるワイヤーの本数およびワイヤボンディング用電極端子数が低減可能となる。 Thus, it is possible to directly connect via the electrode terminal 106 and the lead frame the back surface side electrode terminals for metal 112 (not shown) to be GND from the back side of the semiconductor device 100 corresponding to GND, the semiconductor device assembly the number and the wire bonding electrode terminals of each wire in the wire bonding in process can be realized reduction. このため、電極端子の外周寸法が縮小可能となるので、半導体装置100の小型化に伴う高密度化が実現される。 Therefore, since the outer peripheral dimension of the electrode terminal is reducible, densification accompanying the miniaturization of the semiconductor device 100 can be realized.

また、半導体装置100のGNDと対応させる電極端子106は、GNDと接する大口径な電極端子となる裏面側電極端子用メタル112を介して接地されることにより、半導体装置100の動作時にGNDに接続される電極端子106の発熱を裏面側電極端子用メタル112で分散されるので、前述の半導体装置100の動作時の発熱の廃熱効果が高まる。 The electrode terminal 106 to correspond to the GND of the semiconductor device 100, by being grounded through the backside electrode terminal metal 112 serving as a large-diameter electrode terminals in contact with GND, connected to GND during the operation of the semiconductor device 100 since the heat generation of the electrode terminal 106 to be dispersed by the rear surface side electrode terminal metal 112 increases the waste heat effect of heat generated during operation of the semiconductor device 100 described above. このため、半導体装置100のヒートアップによって、かかる半導体装置100を備えた半導体アナログ集積回路等の機能の低下を防ぐことができる。 Therefore, the heat-up of the semiconductor device 100, it is possible to prevent deterioration of the function of such a semiconductor analog integrated circuit having such a semiconductor device 100.

さらに、GNDと接する上述の大口径な電極端子を半導体材料からなる半導体ウエハ102に比べて熱伝導率が高い金(Au)等の金属系材質で表面積を大きく形成することによって、より多くの熱エネルギーを吸収できる。 Furthermore, by increasing formation surface area of ​​a metal-based material such as a high thermal conductivity of gold (Au) as compared with a semiconductor wafer 102 composed of a large-diameter electrode terminals described above in contact with GND of a semiconductor material, more heat It can absorb the energy. このため、結果的に半導体装置100の動作中に発生する熱エネルギーが大口径な裏面側電極端子用メタル112を通じてリードフレーム等の実装用基板側に伝わり、半導体装置100そのものに熱がこもりにくくなり、かかる廃熱効果の向上が実現される。 Therefore, consequently transmitted thermal energy generated during operation of the semiconductor device 100 through the large diameter of the rear surface side electrode terminal metal 112 on the mounting board side such as a lead frame, heat is hardly confined to the semiconductor device 100 itself , improvement of such waste heat effect is achieved.

次に、本実施形態の半導体装置100の製造方法について、図面を使用しながら説明する。 Next, a method of manufacturing the semiconductor device 100 of the present embodiment will be described with reference to the drawings. 図2は、本実施形態の半導体装置100の製造方法を説明するためのフローチャートであり、図3〜7は、図2で示すフローチャートの工程S10〜S18までの各工程における本実施形態の半導体装置100の模式的な断面図である。 Figure 2 is a flow chart for explaining the manufacturing method of the semiconductor device 100 of this embodiment, FIG. 3-7, the semiconductor device of this embodiment in each step to the flow chart of steps S10~S18 shown in FIG. 2 it is a schematic cross-sectional view of a 100.

本発明の半導体装置の製造方法は、半導体装置の配線・電極形成工程後に斯かる半導体装置を組み立てる各種のパッケージ形状による組立工程に特徴を有する。 The method of manufacturing a semiconductor device of the present invention is characterized by the assembly process according to various package shapes assembling a semiconductor device such after the wiring electrode formation process of the semiconductor device. 本実施形態の半導体装置100の製造方法において、図2で示す半導体装置100の組立工程では、半導体ウエハ102上に配線パターン104および電極端子パターン106を形成する工程後に、まず、電極端子パターン106が形成される面102aのうち、GNDに対応する電極端子パターン106以外の部分を図3に示すように第1のレジストとなるフォトレジスト114で被膜する(図2で示す工程S10)。 The method of manufacturing a semiconductor device 100 of this embodiment, the assembly process of the semiconductor device 100 shown in FIG. 2, after the step of forming a wiring pattern 104 and the electrode terminal pattern 106 on the semiconductor wafer 102, first, the electrode terminal pattern 106 among the surfaces 102a formed to coat the portion other than the electrode terminal pattern 106 corresponding to the GND in the photoresist 114 as a first resist as shown in FIG. 3 (step S10 shown in FIG. 2).

その後、図4に示すように、GNDに対応している電極端子パターン106、換言すると、フォトレジスト114で被膜されていない電極端子パターン106を貫通するようにして半導体ウエハ102にVIAホール108をエッチング処理等により形成する(図2で示す工程S12)。 Thereafter, as shown in FIG. 4, the electrode terminal pattern 106 corresponds to GND, and in other words, etching the VIA holes 108 in the semiconductor wafer 102 so as to penetrate the electrode terminal patterns 106 that are not coated with photoresist 114 formed by treatment such as (step S12 shown in FIG. 2). なお、このときのVIAホール108の深さは、100um以上の深さを確保することが製造過程において加工精度上厳しいため、100um以下を想定するものとする。 The depth of the VIA holes 108 at this time, since severe on processing accuracy in the manufacturing process to ensure the depth of at least 100um, shall assume the following 100um.

半導体ウエハ102にVIAホール108を形成後、電極端子パターン106が形成される面102aの反対側の面となる裏側面102bに工程S12で形成したVIAホール108の各底部108aを包含可能な大きさの孔部である大口径ホール110を形成するために、図5で示すように、大口径ホール110を形成する部位以外に、第2のレジストとなるフォトレジスト116を被膜する(図2で示す工程S14)。 After the formation of the VIA holes 108 in the semiconductor wafer 102, the size capable of encompass the bottom 108a of the VIA holes 108 formed in second process S12 on the back surface 102b on the opposite side of the surface 102a of the electrode terminal pattern 106 is formed a hole portion to form a large-diameter hole 110, as shown in Figure 5, in addition to the site for forming the large diameter hole 110, showing a photoresist 116 serving as the second resist film to (2 step S14).

その後、工程S14で半導体ウエハ102のフォトレジスト116で被膜されていない部位に対し、図6で示すように、半導体ウエハ102の反対側の面となる裏面102bからVIAホール108の底部となる底面108aが確認できる深さまでエッチング処理をすることにより、上記の大口径ホール110を形成する(図2で示す工程S16)。 Thereafter, to the sites that are not coated with photoresist 116 of the semiconductor wafer 102 in step S14, as shown in Figure 6, the bottom surface 108a consisting of the back surface 102b on the opposite side of the surface of the semiconductor wafer 102 and the bottom of the VIA holes 108 There by an etching process to a depth that can be confirmed, to form a large diameter hole 110 of the (step S16 shown in FIG. 2). これにより、各電極端子上から形成された各電極端子用VIAホール108と大口径ホール110の接続が可能となる。 This allows connection of the large diameter hole 110 and VIA holes 108 for each electrode terminal formed from the electrode terminals. なお、大口径ホール110は、製造条件の許容範囲内でなるべく大きく、かつ深く形成される程、上述した本発明の効果がより発揮されるので好ましい。 Incidentally, the large-diameter hole 110 is as large as possible within the allowable range of production conditions, and degree to be deeply formed, the effect of the present invention described above are exhibited more preferable.

次に、形成された大口径ホール110に対し、図7で示すように、VIAホール108の各底部108aとGNDとを電気的に接続するための一の導電体として、導電性のめっきを所望の厚さになるまで成膜することによって裏面側電極端子用メタル112が形成される(図2で示す工程S18)。 Next, with respect to large-diameter holes 110 formed, as shown in Figure 7, as a conductor for electrically connecting each bottom 108a and GND VIA hole 108, the conductive plated desired backside electrode terminal metal 112 is formed by depositing to a thickness of (step S18 shown in FIG. 2). このときの導電性めっきの好適な材質としては、電気伝導や熱伝導に非常に優れ、かつ酸化しにくいことによる経時変化が少ない点からして、金等が好ましいが、銅等の他の金属でも代用可能である。 Suitable material for the conductive plating at this time, electrically very good conductivity and thermal conductivity, and in terms aging is small due to the difficult oxidation, although gold or the like is preferred, other metals such as copper But it is possible to substitute. なお、このとき形成される裏面側電極端子用メタル112の厚さは、次の工程S20での薄層化における目標基板厚よりもやや厚めになるような厚さとすることが好ましい。 The thickness of the back-side electrode terminal metal 112 formed at this time, it is preferable that the such that slightly larger than the desired substrate thickness thickness at thin at the next step S20.

その後、オゾン溶解法等によりフォトレジスト114、116を除去してから、形成された半導体装置100を所望の厚さになるまでの薄層化を行い(図2で示す工程S20)、図1に示す装置の形態をもって半導体装置100の完成とし、かかる工程S20以降は、チップ化工程等を行うこととする。 Then, after removing the photoresist 114 and 116 by the ozone dissolution method, a semiconductor device 100 formed performs thinning to a desired thickness (step S20 shown in FIG. 2), in Figure 1 have the form of apparatus shown the completion of the semiconductor device 100, such steps S20 and later, and carrying out the chip step.

以上説明したように、本発明の半導体装置100の製造方法は、半導体ウエハ102の裏面側102bに半導体ウエハ102の表面側102aから形成した各VIAホール108を包含可能な大きさの大口径ホール110を形成してから、半導体装置100に設けられるGNDに接続する電極端子106とGNDとを電気的に直接接続する導電体となる裏面側電極端子用メタル112を導電性めっきの成膜加工で設けることにより、ウエハ102の表面側に設けた電極端子106とGNDが導通するので、従来のように半導体装置組立工程でのワイヤボンディングにおけるワイヤーの本数やワイヤボンディング用電極端子数が低減できる。 As described above, the manufacturing method of the semiconductor device 100 of the present invention, the back side 102b large diameter hole of the VIA holes 108 a can include size formed from the surface side 102a of the semiconductor wafer 102 to 110 of the semiconductor wafer 102 after forming, electrically providing the back surface side electrode terminal metal 112 to be directly connected to the conductor film formation process of the conductive plating and the electrode terminal 106 and the GND to GND provided in the semiconductor device 100 it allows the electrode terminal 106 and the GND provided on the surface side of the wafer 102 is conductive, can be reduced number of electrodes terminal number and wire bonding of the wire in the wire bonding in the conventional semiconductor device assembly process as.

また、半導体装置100のGNDと対応させる電極端子106が大口径な電極端子である裏面側電極端子用メタル112を介して接地されることによって、半導体装置100の動作時にGNDに接続される電極端子106の発熱を裏面側電極端子用メタル112で分散できる。 The electrode terminal electrode terminal 106 to correspond to the GND of the semiconductor device 100 is connected by being grounded through the backside electrode terminal metal 112 is a large diameter electrode terminals, to GND during the operation of the semiconductor device 100 the heating of 106 can be dispersed on the back-side electrode terminals for metal 112. このため、半導体装置の小型化に伴う高密度化を実現した上で前述の半導体装置100の動作時の発熱の廃熱効果を高めることができる。 Therefore, it is possible in terms of realizing higher density due to the miniaturization of the semiconductor device increase waste heat effect of the heat generated during operation of the semiconductor device 100 described above.

以上、添付図面を参照しながら本発明の好適な実施形態について説明したが、本発明は係る例に限定されないことは言うまでもない。 Having described the preferred embodiments of the present invention with reference to the accompanying drawings, it goes without saying that the present invention is not limited to the embodiment. 当業者であれば、特許請求の範囲に記載された範疇内において、各種の変更例または修正例に想到し得ることは明らかであり、それらについても当然に本発明の技術的範囲に属するものと了解される。 Those skilled in the art within the scope described in the claims, it would be appreciated by the can conceive modifications, combinations, and belong to the technical scope of the present invention as for their It is understood.

例えば、上述の実施形態では、半導体ウエハ102の裏面側から形成した大口径ホール110にVIAホール108の各底部108aとGNDを電気的に接続するために導電性めっきの成膜加工により形成された裏面側電極端子用メタル112が設けられているが、VIAホール108の各底部108aとGNDを電気的に接続できれば、成膜加工によって形成された裏面側電極端子用メタル112に限定されず、他の製造方法で形成された金属板等の一の導電体で代用することも可能である。 For example, in the embodiment described above, which is formed by a deposition process of the conductive plating for electrically connecting the bottom portion 108a and GND VIA holes 108 a large diameter hole 110 formed from the back surface side of the semiconductor wafer 102 Although the back surface side electrode terminal metal 112 is provided, if electrically connected to the bottom portion 108a and GND VIA holes 108 is not limited to the back surface side electrode terminal metal 112 formed by a film forming process, other it is also possible to substitute one of the conductor such as a metal plate formed by the manufacturing method of the.

本発明は、半導体装置、および斯かる半導体装置の製造方法に適用可能であり、特に、ワイヤボンディング方法を用いずにリードフレームGND部への実装接地が可能な半導体装置に適用可能である。 The present invention relates to a semiconductor device, and is applicable to the production method of such a semiconductor device, particularly applicable to a semiconductor device capable of mounting a ground to lead frame GND portion without using the wire bonding method.

本発明の半導体装置の一実施形態の模式的な断面図である。 It is a schematic cross-sectional view of one embodiment of a semiconductor device of the present invention. 同実施形態の半導体装置の製造方法を説明するためのフローチャートである。 It is a flowchart for explaining a method for manufacturing a semiconductor device of the embodiment. 同実施形態の半導体装置の製造方法の工程S10における半導体装置の模式的な断面図である。 It is a schematic sectional view of a semiconductor device in a step S10 in the method of manufacturing a semiconductor device of the embodiment. 同実施形態の半導体装置の製造方法の工程S12における半導体装置の模式的な断面図である。 It is a schematic sectional view of a semiconductor device in a step S12 in the method of manufacturing a semiconductor device of the embodiment. 同実施形態の半導体装置の製造方法の工程S14における半導体装置の模式的な断面図である。 It is a schematic sectional view of a semiconductor device in a step S14 in the method of manufacturing a semiconductor device of the embodiment. 同実施形態の半導体装置の製造方法の工程S16における半導体装置の模式的な断面図である。 It is a schematic sectional view of a semiconductor device in a step S16 in the method of manufacturing a semiconductor device of the embodiment. 同実施形態の半導体装置の製造方法の工程S18における半導体装置の模式的な断面図である。 It is a schematic sectional view of a semiconductor device in a step S18 in the method of manufacturing a semiconductor device of the embodiment. 従来技術であるワイヤボンディングに係る半導体装置の構造を示す説明図である。 Is an explanatory view showing a structure of a semiconductor device according to the wire bonding is prior art. 従来技術であるフリップチップボンディングに係る半導体装置の構造を示す説明図である。 Is an explanatory view showing a structure of a semiconductor device according to the flip chip bonding is prior art.

符号の説明 DESCRIPTION OF SYMBOLS

100 半導体装置102 半導体ウエハ102a 配線および電極端子パターンが形成されている面102b 配線および電極端子パターンが形成されている面と反対側の面(裏側面) 100 surface opposite to the surface on which the surface 102b wiring and the electrode terminal pattern semiconductor device 102 a semiconductor wafer 102a wiring and electrode terminal pattern is formed is formed (back surface)
104 配線パターン106 電極端子パターン108 導通孔(VIAホール) 104 wiring pattern 106 electrode terminal pattern 108 through hole (VIA hole)
108a (VIAホールの)底部110 孔部(大口径ホール) 108a (the VIA holes) bottom 110 holes (large diameter hole)
112 一の導電体(裏面電極端子用メタル) 112 one conductive member (metal for the back electrode terminals)
114 一のレジスト(フォトレジスト) 114 first resist (photoresist)
116 他のレジスト(フォトレジスト) 116 other resist (photoresist)

Claims (4)

  1. 接地面に設けられ、半導体ウエハ上に配線および電極端子パターンが形成されている半導体装置において、 Provided to the ground plane, a semiconductor device wiring and the electrode terminal pattern on a semiconductor wafer is formed,
    前記電極端子パターンのうち、前記接地面と接続する電極端子パターンが形成されている部位には、該部位に設けられた前記電極端子パターンを貫通するようにして前記半導体ウエハに導通孔が形成され、 Wherein one of the electrode terminal pattern, a portion where the electrode terminal pattern to be connected to the ground plane is formed, through hole in the semiconductor wafer so as to penetrate the electrode terminal pattern provided to the site is formed ,
    前記半導体ウエハには、該半導体ウエハの前記配線および電極端子パターンが形成されている面と反対側の面から前記導通孔の底部に達するまで、径が前記導通孔の各底部を包含可能な大きさである孔部が形成され、該孔部には前記各底部および前記接地面を電気的に接続する一の導電体が設けられていることを特徴とする、半導体装置。 Wherein the semiconductor wafer has a surface on which the wiring and the electrode terminal pattern of the semiconductor wafer is formed from the surface opposite to reach the bottom of the conduction hole-diameter can encompass the bottom of the conduction hole size is the hole is formed is being characterized in that the first conductor in the hole portion for electrically connecting each of said bottom and said ground plane is provided, the semiconductor device.
  2. 前記一の導電体は、成膜加工により形成されている導電性のめっきであることを特徴とする、請求項1に記載の半導体装置。 The one conductor, characterized in that a conductive plating formed by a deposition process, a semiconductor device according to claim 1.
  3. 接地面に設けられた半導体装置の半導体ウエハ上に配線および電極端子パターンを形成する工程後に、前記半導体装置を組み立てる工程を含む半導体装置の製造方法において、 After the step of forming the wiring and the electrode terminal pattern on a semiconductor wafer of a semiconductor device provided on the ground surface, in the manufacturing method of a semiconductor device including the step of assembling the semiconductor device,
    前記電極端子パターンが形成される面のうち、前記接地面と接続する電極端子パターン以外の部分を一のレジストで被膜する工程と、 Among the surfaces of the electrode terminal pattern is formed, a step of coating a portion other than the electrode terminal pattern to be connected to the ground plane in one of the resist,
    前記一のレジストで被膜されていない前記電極端子パターンを貫通するようにして前記半導体ウエハに導通孔を形成する工程と、 Forming a through hole in the semiconductor wafer so as to penetrate the electrode terminal pattern which is not coated with the first resist,
    前記電極端子パターンが形成される面の反対側の面に前記導通孔の各底部を包含可能な大きさの孔部を形成する部位以外に他のレジストを被膜する工程と、 A step of coating the other resist except portions for forming the hole portion of the bottom portion can include size of the conducting hole in the surface opposite to the surface on which the electrode terminal pattern is formed,
    前記半導体ウエハの前記他のレジストで被膜されていない部位を前記反対側の面から前記導通孔の底部に届くまでエッチング処理をする工程と、 A step of etching processing sites that are not coated with the other resist of the semiconductor wafer from the surface of the opposite side until it reaches the bottom of the conduction hole,
    前記エッチング処理により形成された前記孔部に前記導通孔の各底部および前記接地面を導通可能にするための一の導電体を設ける工程と、 A step of providing an electrical conductor for allowing conduction of each bottom and the ground plane of the conducting hole in the hole formed by the etching treatment,
    前記一のおよび他のレジストを除去して、形成された半導体装置の薄層化を行う工程と、 Wherein by removing one or other resist, and performing thinning of the semiconductor device formed,
    を含むことを特徴とする、半導体装置の製造方法。 Characterized in that it comprises a method of manufacturing a semiconductor device.
  4. 前記一の導電体は、導電性のめっきを所望の厚さになるまで成膜することにより形成されることを特徴とする、請求項3に記載の半導体装置の製造方法。 The one conductor, characterized in that it is formed by depositing a conductive plating to the desired thickness, a method of manufacturing a semiconductor device according to claim 3.
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