JP2002025948A - Dividing method of wafer, semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to handle a wafer and divided semiconductor chips with good reliability when the wafer is divided, and to greatly increase the number of chips taken from the wafer. SOLUTION: A plurality of aluminum pads 2 and a passivation film 3 are formed on a silicon substrate 1 with circular outline. A resist 4 formed on the silicon substrate 1 is patterned. Trench holes 5 as ditches for dividing the wafer are formed by dry etching in the silicon substrate 1 with the resist 4 as a mask. After the resist 4 is removed, a back grinding tape 6 is put on the side of the aluminum pad 2 of the silicon substrate 1, and the rear of the silicon substrate 1 is ground and polished until it reaches the trench hole 5. In this way, the separation width of the semiconductor chip in the wafer can be made small, and the layout of semiconductor devices on the wafer can be carried out without consideration on the chipping by dicing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of dividing a wafer, a semiconductor device, and a method of manufacturing a semiconductor device, and more particularly to a step of separating a plurality of semiconductor elements formed on a wafer into individual semiconductor chips. The method for dividing a wafer and the method for manufacturing a semiconductor device according to the present invention are suitable for thinning the chip and increasing the diameter of the wafer when stacking semiconductor chips to achieve multi-functionality and high performance of the semiconductor device. is there.

[0002]

2. Description of the Related Art Semiconductor device manufacturing processes include a process of forming various semiconductor patterns on a wafer (usually referred to as a pre-process) and a plurality of semiconductor elements formed on the wafer into individual semiconductor chips. It can be roughly divided into a mounting step of cutting and dividing the semiconductor chip, connecting a lead frame, TAB, or the like to the semiconductor chip and packaging it.

[0003] In recent years, in order to reduce the manufacturing cost of semiconductor devices, the diameter of wafers has been increased, and
A method of three-dimensionally stacking thin-film semiconductor elements in response to an increase in the mounting density of the semiconductor elements, and the integration and speeding up of devices has been adopted.

Conventionally, after dicing a wafer into individual semiconductor chips, the semiconductor chips are connected to a lead frame or a T-frame.
AB is connected by wire bonding, gang bonding or the like to perform packaging. In recent years, I
In response to the demand for thin-film devices such as C-cards, prior to separation of the wafer, the surface opposite to the surface on which the pattern is formed on the wafer is ground with a grindstone (back grinding) or with a free grindstone. To make the wafer thinner, and then dicing. In grinding or polishing the wafer, an adhesive sheet called a back grinding film has been applied to the surface of the wafer on which the semiconductor elements are formed, that is, the device surface, or a resist has been applied to protect the wafer.

However, when the above-described method is used to meet the demand for a larger diameter wafer and a further reduction in the thickness of semiconductor devices, the problem that the wafer is broken when handling or dicing the thinned wafer. Has come to the surface. In addition, chipping that occurs on the back surface of the wafer during dicing lowers the strength of the semiconductor chip separated from the wafer, causing a problem that the semiconductor chip is broken even in the mounting process. To cope with such a problem, Japanese Patent Application Laid-Open No. 9-213662 discloses a method in which a concave groove for separation is formed in advance on a surface of a wafer on which a semiconductor element is formed along a dicing line by dicing. A method of dividing a chip by back grinding for grinding and polishing the back surface (so-called pre-dicing) is disclosed. By such a method, cracking of the wafer due to dicing of a large-diameter wafer is prevented. Further, according to such a method, it is suggested that chipping due to dicing is extremely reduced, and the strength of a semiconductor chip and a semiconductor device is also increased.

However, the destruction of the semiconductor chip may be caused not only by chipping on the outer periphery of the semiconductor chip but also by microcracks that occur during back grinding. Usually, these microchips are polished or etched after grinding. A technique has been adopted in which cracks are removed to increase the strength of the semiconductor chip.

[0007] Further, in the future, when semiconductor devices are stacked and multifunction and high performance are achieved by stacking semiconductor elements, separation of semiconductor chips by dicing is limited to only a rectangle, and the rectangular shape of the semiconductor chips is limited to a stacked shape. The degree of freedom is reduced from the viewpoint of connection of semiconductor elements. Packaging technology for semiconductor devices has changed from QFP, in which a semiconductor chip is die-bonded to a lead frame and wire bonding of pads and leads, followed by ceramic or plastic molding, to area array types, such as BGA and CSP, which perform planar connections. In the direction of stacking devices three-dimensionally. The stacking of these devices is aimed at achieving multi-functionality by stacking devices with different functions (logic and memory), and the direction of aiming for higher performance by stacking devices with the same function, such as higher speed and higher memory capacity. There is.

As described above, when a plurality of devices are stacked and the devices are electrically connected to each other, if only the rectangular chips are stacked, the degree of freedom becomes extremely small. FIG. 11 shows an example of a semiconductor device of a three-dimensional package in which two types of semiconductor chips are stacked and electrically connected by wire bonding. In the semiconductor device shown in FIG. 11, a flash memory 109 as a semiconductor chip and an S-RAM (Static RAM) 110 are stacked in this order on an interposer 108 as a mounting substrate.

A flash memory 109 is die-bonded on the interposer 108 with a die bonding agent 111a, and an S-RAM 110 is die-bonded on the flash memory 109 with a die bonding agent 111b. In this semiconductor device, the upper and lower semiconductor chips are electrically connected to the pattern of the electrode portion formed on the interposer 108 by wire bonding with the gold wires 112a and 112b. BGA (Ball Grid Allay) provided with a plurality of solder balls 113 on the lower surface of the interposer 108
It is of the type. Flash memory 109 or S-
The RAM 110 and the gold wires 112a and 112b are sealed with a package material 114.

[0010]

However, in prior dicing in which the wafer is diced in advance as disclosed in Japanese Patent Application Laid-Open No. 9-213662, the dicing line is exposed on the back side of the wafer during grinding. Since etching and polishing cannot be performed, the microcracks cannot be removed, and it has been pointed out that the strength of the semiconductor chip is reduced. That is, the improvement of the breaking strength due to the reduction of chipping is effective in so-called flat splitting (holding both ends of the tip with two bars and applying a load to the center), but drum splitting (tip is made of a cylinder) Holding and applying a load to the center) hardly improves the strength, and has a problem in that the drum splitting strength is low as compared with a thin film chip from which microcracks have been removed. Further, a region of about 5 mm from the edge of the outer peripheral portion of the wafer is a region outside the guaranteed range of the film thickness by polishing at the time of forming the wafer, and is usually thin. Further, the region is a region where semiconductor elements are not formed due to wafer handling and the like.
In the pre-dicing, in which dicing is performed in advance as described above, after the wafer is divided, the wafer is attached to a back grinding tape and then back-ground,
The adhesive material of the back grinding tape cannot express sufficient adhesive strength to the divided area on the outer peripheral part of the wafer, so that during back grinding, so-called chip fly etc. occurs, destroying good chips There are problems such as getting lost.

[0011] In addition, the division by the dicer is performed by using a thickness (typically 50 μm) of a diamond blade or the like used for separation.
It was necessary to arrange the actual pattern at a position several tens of μm away from the dicing line so that the separation margin required for the cutting (about) and the chipping and shell cracks generated during dicing did not affect the pattern. These areas caused by dicing reduce the number of chips taken from a wafer, and will be a major cause of cost increase in a situation where semiconductor devices become smaller in the future.

On the other hand, when manufacturing the semiconductor device shown in FIG.
The size of the upper and lower chips is determined in consideration of the mounting accuracy of the upper and lower chips 110, the die bonding agents 111a and 111b that are adhesives for die bonding, the size of pads, and the like. Then, when performing wire bonding with the gold wires 112a and 112b, it is necessary to form a wire profile with a very low loop and a long distance, and the wires may fall down or short-circuit in a resin mold package in a later process. Need to be prevented. Here, if the design is made with a sufficient margin, there is a problem that the BGA package manufactured by lamination cannot be reduced in size and thickness.

Also, in response to recent demands for higher speed of semiconductor devices, a parasitic capacitance caused by a long connection by wire bonding causes a malfunction of the device, and is formed by forming a through hole in silicon of a semiconductor chip. A method of electrically connecting the stacked semiconductor chips using via holes is also being studied. However, there is no established technique for forming these through holes.

As described above, the conventional method of dividing a wafer secures sufficient reliability against the problem that the wafer is liable to be broken at the time of transportation and back grinding for a thin film semiconductor device whose use is to be expanded in the future. It is a situation that can not be done.

The present invention has been made in view of the above circumstances, and a main object of the present invention is to provide a method for manufacturing a semiconductor chip by dividing a wafer, a wafer having a plurality of thin-film semiconductor elements formed thereon, and an isolation method. It is an object of the present invention to provide a method of dividing a wafer and a method of manufacturing a semiconductor device, which can handle a semiconductor chip with high reliability and can greatly increase the number of chips that can be taken from the wafer.

Another object of the present invention is to increase the degree of freedom in designing a semiconductor device when a plurality of semiconductor chips are stacked to produce a multifunctional and high-performance semiconductor device. It is an object of the present invention to provide a possible wafer separation method, a semiconductor device, and a method for manufacturing a semiconductor device.

[0017]

In order to achieve the above object, a method of dividing a wafer according to the present invention is a method of dividing a wafer on which a plurality of semiconductor elements are formed into individual semiconductor chips. Forming a groove of a predetermined depth by dry etching at a position corresponding to the outer shape of the semiconductor chip on the surface of the wafer on which the semiconductor elements are formed, and attaching a holding sheet to the surface of the wafer on which the semiconductor elements are formed; Attaching the wafer, and grinding and polishing at least the back surface of the wafer opposite to the surface on which the semiconductor elements are formed, until the wafer reaches the groove, thereby separating the wafer into individual semiconductor chips.

In the step of forming the groove on the surface of the wafer on which the semiconductor elements are formed, a groove for separating the wafer into the individual semiconductor chips is formed in a portion other than an outer peripheral portion of the wafer. Is preferred.

Further, in the step of forming the groove on the surface of the wafer on which the semiconductor element is formed, the groove is formed so that an end of the individual semiconductor chip separated from the wafer has a comb shape. It may be formed.

Further, in the step of forming the groove on the surface of the wafer on which the semiconductor element is formed, the individual semiconductor chips separated by grinding and polishing the wafer to form via holes in the semiconductor chip. Forming a recess for forming the through-hole in the wafer simultaneously with the groove by dry etching so that a through-hole passing through the semiconductor chip is formed, and forming the groove and the recess in the wafer. Later, a step of forming an insulating film on the inner wall surface of the recess and a step of embedding a conductive material in the inside of the recess in which the insulating film is formed are individually ground by grinding and polishing the back surface of the wafer. May be provided before the step of separating into semiconductor chips.

In the above invention, when a wafer on which a plurality of semiconductor elements are formed is divided into individual semiconductor chips, a predetermined position is formed by dry etching at a position corresponding to the outer shape of the semiconductor chip on the semiconductor element formation surface of the wafer. After a groove having a depth is formed, and a holding sheet is attached to a surface on which the groove is formed, the separation width of the semiconductor chip in the wafer can be reduced by grinding and polishing the back surface of the wafer until the groove reaches the groove. At the same time, it is possible to lay out semiconductor elements on a wafer without considering chipping due to dicing of the wafer. In such wafer division using dry etching, it is possible to prevent cracking of the wafer during wafer transfer and back grinding compared to the conventional division method, and it is possible to handle the wafer with high reliability. Becomes At the same time, the semiconductor chip is prevented from being broken in the mounting process due to chipping by dicing as in the past, so that the strength of the separated semiconductor chip is increased and the semiconductor chip can be handled with high reliability. Becomes In addition, the separation of the semiconductor chip by such dry etching can reduce the area required for the separation to the limit,
The number of chips that can be obtained from a wafer can be greatly increased. Furthermore, chips with an outer shape other than rectangular can be manufactured, chips can be separated without dividing the outer periphery of the wafer, the degree of freedom in the separation shape can be increased, the separation process can be stabilized, and semiconductor chips can be mounted. The degree of freedom in the process increases.

As described above, the separation groove is formed in the portion except for the outer peripheral portion of the wafer, and the separation groove is not formed in the outer peripheral portion of the wafer, so that chip fly is prevented in the outer peripheral portion of the wafer. This makes it possible to reduce the thickness of the wafer with high reliability. In addition, by making the end shape of the semiconductor chip a comb shape, the degree of freedom in designing a semiconductor device by stacking semiconductor chips can be increased, and the yield and reliability of the semiconductor device can be improved. Further, if the process of dry etching is shared with processing other than chip separation, that is, formation of via holes for three-dimensional mounting of chips, it is possible to greatly reduce the number of steps.

Further, a semiconductor device according to the present invention includes a mounting substrate having an electrode portion, at least two semiconductor chips having an electrode portion, stacked on the mounting substrate, and an electrode portion of each of the semiconductor chips. In a semiconductor device having a bonding wire for electrically connecting to an electrode portion of the mounting substrate, at least one of the plurality of semiconductor chips on the mounting substrate has a comb-shaped end. Has become.

As described above, in a semiconductor device configured by laminating at least two semiconductor chips on a mounting substrate and electrically connecting the electrode portions of the semiconductor chip to the electrode portions of the mounting substrate by bonding wires, The shape of the end is a comb tooth shape,
As described above, the degree of freedom in designing a semiconductor device by stacking semiconductor chips can be increased, and the yield and reliability of the semiconductor device can be increased.

Further, a semiconductor device according to the present invention has a mounting substrate having an electrode portion and at least two semiconductor chips manufactured by using the above-described wafer dividing method and stacked on the mounting substrate. In a semiconductor device, an electrical connection between an electrode of the mounting substrate and each of the semiconductor chips and an electrical connection between the semiconductor chips are performed by via holes penetrating each of the semiconductor chips. .

In the above invention, in a semiconductor device configured by laminating at least two semiconductor chips on a mounting substrate, the semiconductor chips are manufactured by using the above-described wafer dividing method, and the electrodes of the mounting substrate are formed. The electrical connection between the semiconductor chip and each semiconductor chip and the electrical connection between the semiconductor chips are performed via the via holes. Therefore, when the semiconductor device is manufactured, the semiconductor chip is connected as described above. The dry etching process for separation is shared with the formation of via holes for three-dimensional mounting of the chip, and the process can be greatly reduced.
Therefore, the manufacturing cost of the semiconductor device can be reduced, and a multifunctional and high-performance semiconductor device can be obtained.

Further, in the method of manufacturing a semiconductor device according to the present invention, at least two semiconductor chips manufactured by dividing a wafer are stacked on a mounting substrate, and the electrode portions of each of the stacked semiconductor chips are connected to each other. In a semiconductor device manufacturing method for manufacturing a semiconductor device by electrically connecting to an electrode portion on a mounting substrate by a bonding wire,
In the step of manufacturing the semiconductor chip by dividing the wafer, the wafer is divided so that the end of the semiconductor chip has a comb shape.

In the above-described method for manufacturing a semiconductor device, the end of the semiconductor chip is formed into a comb shape when the wafer is divided in order to manufacture the semiconductor chip to be stacked on the mounting substrate. As described above, the degree of freedom in designing a semiconductor device can be increased, and the yield and reliability of the semiconductor device can be improved.

Further, the step of dividing the wafer comprises:
Forming a groove of a predetermined depth by dry etching at a position corresponding to the outer shape of the semiconductor chip on a surface of the semiconductor element forming surface of the wafer on which a plurality of semiconductor elements are formed; and forming the semiconductor element on the wafer A step of attaching a holding sheet to the surface, and a step of grinding and polishing the back surface of the wafer opposite to the formation surface at least until reaching the groove, and separating the wafer into individual semiconductor chips. Is preferred.

Further, a method of manufacturing a semiconductor device according to the present invention includes a mounting substrate having an electrode portion, and at least two semiconductor chips stacked on the mounting substrate, wherein an electrode of the mounting substrate and each of the Electrical connection with a semiconductor chip, and electrical connection between the semiconductor chips,
A method of manufacturing a semiconductor device, the method being performed by a via hole penetrating through each of the semiconductor chips, wherein an etching corresponding to an outer shape of the semiconductor chip is formed on a surface of the semiconductor element on a wafer on which a plurality of semiconductor elements are formed. Forming a groove having a predetermined depth along a line, and a concave portion for forming the via hole by dry etching; forming an insulating film on an inner wall surface of the concave portion of the wafer; A step of embedding a conductive material in the formed concave portion, and a back surface of the wafer opposite to a surface on which the semiconductor element is formed,
Grinding and polishing until reaching the grooves and recesses,
Separating the wafer into individual semiconductor chips.

In the above method for manufacturing a semiconductor device, at least two semiconductor chips are stacked on a mounting substrate,
When manufacturing a semiconductor device in which the electrodes of the mounting substrate are electrically connected to the respective semiconductor chips and the semiconductor chips are electrically connected to each other through via holes, a dry device for separating the semiconductor chips is used. By making the etching process common to the formation of via holes for three-dimensional mounting of the chip, the manufacturing process of a semiconductor device having a multifunctional and high-performance semiconductor chip stack can be greatly reduced.

[0032]

Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a cross-sectional view for explaining a basic process of separating a wafer into individual semiconductor chips by a wafer dividing method according to a first embodiment of the present invention. It is.

A plurality of semiconductor elements are formed on a silicon substrate 1 shown in FIG. 1A, which is a circular wafer having an outer shape. A plurality of aluminum pads 2 made of Al are formed as electrode portions on the surface of the silicon substrate 1 where semiconductor elements are formed. As shown in FIG. 1A, a passivation film 3 is formed on the surface of the silicon substrate 1 except for the aluminum pad 2 by patterning.

Next, as shown in FIG. 1 (b), a film of a resist 4 is formed on the aluminum pad 2 and on the surface of the passivation film 3, and a groove for separating a wafer corresponds to the outer shape of the semiconductor chip. The resist 4 is patterned to be formed at the position. By the patterning, a part of the resist 4 on the passivation film 3 is partially removed.

Next, as shown in FIG. 1C, the passivation film 3 and the silicon substrate 1 are dry-etched using the resist 4 as a mask, and the silicon substrate 1 is etched in a trench shape. A trench hole 5, which is a groove for dividing a wafer, is formed in the silicon substrate 1.

Next, as shown in FIG. 1D, after removing the resist 4 on the silicon substrate 1, the silicon substrate 1
After a back grinding tape 6 as a holding sheet is attached to the surface of the upper passivation film 3, the back surface of the silicon substrate 1 opposite to the surface on which the semiconductor element is formed is ground and polished until it reaches the trench hole 5. do it,
Perform back grinding. By grinding and polishing the back surface of the silicon substrate 1 in this manner, the silicon substrate 1
Is divided into individual semiconductor chips 21 by the trench holes 5.

Then, as shown in FIG. 1E, the back grinding tape 6 is peeled off from each semiconductor chip 21.

In the wafer dividing method described with reference to FIG. 1, a resist 4 corresponding to the outer shape of the semiconductor chip is directly applied to a silicon substrate 1 on which a passivation film is formed on a semiconductor element and an aluminum pad 2 is exposed. An etching pattern is formed at a position to be etched. After the passivation film 3 and the silicon substrate 1 are dry-etched, the silicon substrate 1 is back-ground.

For the dry etching in the step of FIG. 1C, a general-purpose dry etching technique using a fluorine-based or chlorine-based gas can be applied.
RIE (inductively coupled plasma reactive ion etchi
ng: inductively coupled plasma-reactive ion etching), which is a dry etching method capable of high-speed deep etching. In addition, ICP-RIE by a so-called Bosch process, in which the etching of ICP and the deposition of the protective film on the side wall of the etched portion are repeatedly performed at high speed, can be processed at high speed with a high aspect ratio without extremely undercut.

As a mask material at the time of dry etching, a general-purpose positive resist may be used, or a material having a selectivity with respect to silicon may be patterned by ordinary photolithography to form a mask. Generally, silicon compounds such as silicon oxide and silicon nitride, and metals such as aluminum, titanium, and tungsten can be used. In addition, the mask layer may be used also as a resist layer used when exposing the aluminum pad 2 for mounting, or the passivation film remaining after removing the resist may be used as the mask. It is to be noted that, when the etching is performed, it is preferable that the separation region of the semiconductor chip is formed of the same member, so that the recess can be formed at a high speed with a good shape. That is, if a wiring material or an interlayer insulating material is left in the separation region in the process of forming a semiconductor device, the etching selectivity with the material used as a mask cannot be obtained, the etching time becomes longer, or the etching shape becomes longer. Deteriorates. Of course, TEG (Test Element Group)
Is not preferable. For the etching, a commercially available ICP-RIE apparatus can be used, but 601E manufactured by Alcatel of France is used.
And those manufactured by STS in the United Kingdom can be suitably used.
These dry etchers use the Bosch process and can be judged to be the most mass-productive. At the time of etching, conventional SF ₆ and _{CF 4, C 2 F 6,} C 3 F 8 or fluorine-based etchant, to be able to use such as chlorine and the like to the trace oxygen and nitrogen in order to increase the etching rate You may mix them.

As described above, according to the method of dividing a wafer using dry etching, the width required for separation in the silicon substrate 1 can be made as small as possible, and the conventional method for avoiding chipping by dicing can be used. Since no area is required, semiconductor elements can be laid out on a wafer without considering chipping, and the number of chips to be taken can be increased. The width required for chip separation by the wafer dividing method of the present embodiment can be reduced to about 0.5 to 20 μm, and more preferably to about 0.5 to 5 μm.

As described above, in the division of the wafer using the dry etching, the cracking of the wafer during the transfer of the wafer and the back grinding can be prevented as compared with the conventional division method, and the wafer can be handled with high reliability. It becomes possible. At the same time, the semiconductor chip is prevented from being broken in the mounting process due to the conventional chipping by dicing,
The strength of the separated semiconductor chip is increased, and the semiconductor chip can be handled with high reliability.

FIG. 2 is a sectional view for explaining another example of the wafer dividing method according to the present embodiment. In the method of dividing the steps shown in FIG. 2, first, as shown in FIG. 2A, a passivation film 3 is formed on the entire surface of the silicon substrate 1 and the aluminum pad 2.

Next, as shown in FIG. 2B, by forming a resist 4 on the surface of the passivation film 3 and then patterning the resist 4, a portion of the resist 4 corresponding to the aluminum pad 2 is removed. At the same time, an etching pattern is formed on the resist 4 at a position corresponding to the outer shape of the semiconductor chip.

Next, as shown in FIG. 2C, the passivation film 3 and the silicon substrate 1 are dry-etched using the resist 4 as a mask, the silicon substrate 1 is etched in a trench shape, and the aluminum pad 2 is etched. Exposed, passivation film 3 and silicon substrate 1
Next, a trench hole 5, which is a groove for dividing the wafer, is formed.

Next, after removing the resist 4 on the passivation film 3 as shown in FIG.
A back grinding tape 6 is attached to the surface of the passivation film 3 as shown in FIG.

Thereafter, the back grinding of the silicon substrate 1 is performed in the same manner as described with reference to FIG. 1, so that the silicon substrate 1 is separated from the individual semiconductor chips 21 by the trench holes 5 as shown in FIG. Is divided into

In the method of dividing a wafer described with reference to FIG. 2, a dicing line pattern is formed on the silicon nitride layer used as the passivation film 3 in a resist process for exposing the aluminum pad 2, and this is applied to a mask. are doing.

FIG. 3 is a cross-sectional view for explaining still another example of the wafer dividing method according to the present embodiment. In the method of dividing the steps shown in FIG. 3, a barrier metal such as TiW is formed on the aluminum pad 2 in order to prevent the aluminum pad 2 from being exposed to ICP-RIE for a long time in the method described with reference to FIG. This is an example. Of course, in addition to these application examples, there are many variations depending on what is used as the mask material.

In this dividing method, first, as shown in FIG. 3A, a barrier metal 7 made of TiW is formed on the entire surface of the aluminum pad 2 on the silicon substrate 1, and further, the surface of the barrier metal 7 is formed. Whole and silicon substrate 1
A passivation film 3 is formed on the entire surface of the substrate.

Next, as shown in FIG. 3B, after forming a resist 4 on the surface of the passivation film 3, the resist 4 is patterned,
The part corresponding to the aluminum pad 2 is removed,
An etching pattern is formed on the resist 4 at a position corresponding to the outer shape of the semiconductor chip.

Next, as shown in FIG. 3C, the passivation film 3 and the silicon substrate 1 are dry-etched using the resist 4 as a mask, the silicon substrate 1 is etched in a trench shape, and the aluminum pad 2 is formed. Exposing the barrier metal 7 and the passivation film 3
Then, a trench hole 5 which is a groove for dividing a wafer is formed in the silicon substrate 1.

Next, after removing the resist 4 on the passivation film 3 as shown in FIG.
A back grinding tape 6 is attached to the surface of the passivation film 3 as shown in FIG.

Thereafter, the back grinding of the silicon substrate 1 is performed in the same manner as described with reference to FIG. 1, so that the silicon substrate 1 is separated from the individual semiconductor chips 21 by the trench holes 5 as shown in FIG. Is divided into

FIG. 4 is a plan view showing an example of a wafer separation pattern in the wafer dividing method of the present invention. As shown in FIG. 4, in this example, a separation pattern 42 having a rectangular external shape is formed on a portion of the wafer 41 other than the outer peripheral portion. Therefore, the surface of the outer peripheral portion of the wafer 41 on the side where the semiconductor elements are formed is a flat surface that is continuous over the entire periphery of the edge portion of the wafer 41. As a result, when back grinding the wafer, a plurality of semiconductor chips can be separated without separating the outer peripheral portion of the wafer.

The outer peripheral portion of the wafer 41 is usually thinner than the central portion of the wafer 41 due to polishing, etching, lapping, and the like at the time of producing the wafer. In the process of forming a device on the wafer 41, the outer peripheral portion of the wafer 41 is used for handling the wafer and abutting the wafer to a flat surface, so that the outer peripheral portion is a region where an actual device is not formed. As shown in FIG.
The fact that no separation line is formed in the outer peripheral portion of 1, that is, that no separation groove is formed in the outer peripheral portion of the wafer 41, eliminates the adverse effect of chip fly during back grinding and increases the strength of the thinned wafer 41. Thus, the reliability of handling the wafer 41 is also improved.

Further, according to the wafer dividing method of the present invention, a non-grid chip separation pattern can be formed. FIG. 12 is a plan view showing another example of a wafer separation pattern in the wafer dividing method of the present invention. As shown in FIG. 12, by forming the separation pattern 43 on the wafer 41 so that the semiconductor chips are alternately arranged, the number of chips to be taken can be increased.

Further, if the wafer is divided into semiconductor chips by grinding and polishing the wafer after the groove processing of the division pattern by dry etching as in the present embodiment, a semiconductor chip having a shape other than a rectangle can be easily manufactured. be able to. By manufacturing a semiconductor chip having a shape other than a rectangular shape, the degree of freedom in designing a semiconductor device by stacking semiconductor chips as described later in the second embodiment becomes extremely high. In this case, of course, the area of the wafer can be effectively used to increase the number of chips to be taken. Further, the chip separation pattern in the wafer can be freely changed. In particular, in the case where the outer peripheral portion of the wafer is not separated as shown in FIG. 4, the chips at the outer peripheral portion of the wafer do not fly out during back grinding of the wafer, and the chips can be separated with a high yield.

(Second Embodiment) FIGS. 5A and 5B are a top view and a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention. FIG. 5A is a top view of the semiconductor device. FIG. 5B is a cross-sectional view of the semiconductor device. In FIG. 5A, a package material for sealing the semiconductor chip is omitted.

In the semiconductor device of this embodiment, FIG.
As shown in FIG. 5A and FIG. 5B, a flash memory 9 and an S-RAM 10 which are semiconductor chips are stacked in this order on an interposer 8 which is a mounting substrate. Therefore, the semiconductor device of the present embodiment is a composite memory device of a three-dimensional mounting package configured by stacking the flash memory 9 and the S-RAM 10. The flash memory 9 is die-bonded on the interposer 8 by the die bonding agent 11a, and the S-RAM 10 is die-bonded on the flash memory 9 by the die bonding agent 11b.
Is die-bonded.

The outer shapes of the interposer 8 and the flash memory 9 are rectangular, and the shape of the end of the S-RAM 10 is a comb shape over the entire circumference of the S-RAM 10. The external shape of the flash memory 9 is the interposer 8
, And the outer shape of the S-RAM 10 is smaller than the outer shape of the flash memory 9. S-
An aluminum pad 2c as an electrode portion is formed on the surface of the protruding portion 10b at the end of the comb shape of the RAM 10.
In addition, at the end of the comb teeth of the S-RAM 10, the surface of the flash memory 9 is exposed at the concave portion 10 b interposed between the adjacent protrusions 10 a, and the electrode is formed on the exposed surface of the flash memory 9. An aluminum pad 2b is formed. A plurality of aluminum pads 2a are formed around the mounting portion of the flash memory 9 on the surface of the interposer 8 on the flash memory 9 side.

In this semiconductor device, the aluminum pad 2b of the flash memory 9 is bonded to the aluminum pad 2a corresponding to the aluminum pad 2b of the plurality of aluminum pads 2a of the interposer 8 by wire bonding using a gold wire 12a as a bonding wire. It is electrically connected. Further, the aluminum pad 2c of the S-RAM 10 is electrically connected to the aluminum pad 2a corresponding to the aluminum pad 2c among the plurality of aluminum pads 2a of the interposer 8 by wire bonding with a gold wire 12b as a bonding wire. I have. These flash memory 9, S-RAM 10, and gold wires 12a, 12b
Are sealed by the package material 14. And
The wiring is routed inside the interposer 8, and a plurality of solder balls 13 are provided on the lower surface of the interposer 8, so that the semiconductor device is a BGA (Ball Grid Allay).
It is of the type.

When a semiconductor device is manufactured by stacking semiconductor chips in this way, the end of the semiconductor chip has a comb-like shape like the S-RAM 10, so that the degree of freedom in designing the semiconductor device is extremely high. Get higher. For a complex external shape such as a comb tooth shape, the die bonding agent forms a meniscus at the end of the complex external shape of the semiconductor chip and stops flowing out of the die bonding agent when the die bonding agent protrudes at the time of die bonding of the chip Therefore, the area in anticipation of the protrusion of the die bonding agent can be significantly reduced. Also, it is possible to eliminate the need to form a long and low wire loop so as to avoid a short circuit between the end of the semiconductor chip and the wire or between the wires, thereby reducing the size of the semiconductor device and improving the reliability of the semiconductor device. Can be enhanced.

In the semiconductor device of the present embodiment, the end of the upper semiconductor chip has a comb-like shape, and the outer shape of the lower semiconductor chip has a rectangular shape. However, the present invention is not limited to these. For example, only a part of the end of the upper S-RAM 10 may be comb-shaped, and the end of the lower flash memory 9 may be comb-shaped. Also, depending on the number of aluminum pads, etc., S-RAM
10 and at least one at the end of the flash memory 9
One concave portion may be formed. Therefore, the outer shape of the semiconductor chip need not be simply rectangular, and the fact that the outer shape of the chip is not limited to a rectangle in this manner can increase the degree of freedom in manufacturing a semiconductor device by stacking chips. Therefore, the shape of the semiconductor chip may be any shape other than a rectangle so that the degree of freedom in designing a semiconductor device formed by stacking semiconductor chips is increased.

When manufacturing the semiconductor chip and the semiconductor device of the present embodiment, the semiconductor chip is manufactured by the wafer dividing method described in the first embodiment. As described above, if the wafer is divided into the semiconductor chips by grinding and polishing the wafer after the groove processing of the division pattern by dry etching on the wafer, the comb-shaped S-RAM 10 can be formed in the first embodiment. As described in the above section, a high yield can be easily achieved.

(Third Embodiment) FIG. 6 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention. The semiconductor device of the present embodiment is a composite memory device of a three-dimensional mounting package in which an interposer and a semiconductor chip, or stacked semiconductor chips are electrically connected to each other by a via hole penetrating a silicon substrate.

As an example of a three-dimensional stack of silicon chips, as shown in FIG. 6, a flash memory 29 as a semiconductor chip and an S-RAM 30 are stacked in this order on an interposer 28 as a mounting substrate. The flash memory 29 is die-bonded on the interposer 28 by the bump 16a, and the flash memory 29 is electrically connected to the aluminum pad of the interposer 28 via the bump 16a. Further, the S-RAM 30 is die-bonded on the flash memory 29 by the bump 16b, and the S-RAM 30 is electrically connected to the aluminum pad of the flash memory 29 via the bump 16b.

Flash memory 29 and S-RAM 30
Are rectangular in shape, and the flash memory 29 and the S-RAM 30 are almost the same size. In the flash memory 29, a plurality of via holes 15a each having a through-hole filled with a conductive material are formed, and a bump 16a is connected to a lower end surface of each via hole 15a. The S-RAM 30 also has a plurality of via holes 15b formed by filling the through holes with a conductive material, and bumps 16 are formed on the lower end surfaces of the respective via holes 15b.
b is connected. A plurality of aluminum pads as electrode portions are formed on the surface of the interposer 28 on the flash memory 29 side, and the corresponding bumps 16a are connected to the aluminum pads. A plurality of electrode portions are formed on the surface of the flash memory 29 opposite to the bump 16a side, and the corresponding bump portions 16b are connected to these electrode portions. In the case of FIG. 6, the flash memory 29 and the S-RAM 30 in which the bump 16b is connected to the upper end surface of the conductive material of the via hole 15a, and the bumps 16a and 16b are sealed with the package material. The wiring is routed in the interposer 28, and a plurality of solder balls 33 are provided on the lower surface of the interposer 28.
(Ball Grid Allay) type.

When a semiconductor chip such as the flash memory 29 or the S-RAM 30 is manufactured, the wafer dividing method described in the first embodiment is used. Then, in the step of dividing the wafer, a through hole is formed in the silicon chip, a conductive material is embedded in the through hole, and then a bump is formed on one end surface of the conductive material in the through hole. Then, the upper and lower semiconductor chips are connected via bumps. In a semiconductor device having such a configuration, wiring for electrical connection between semiconductor chips and electrical connection between the semiconductor chip and the interposer may be routed around pads on the outer periphery of the chip, or may be used to connect different chips. Need not be performed by wire bonding. Therefore, it is possible to connect between the transistors at the shortest distance, and such a configuration is expected to become the mainstream of semiconductor mounting technology for high-speed processing in the future. In this configuration, a step of forming a through hole in the silicon substrate is necessary, and if dry etching is applied to that step, the step of forming a through hole for a via hole is shared with the chip separation step according to the present invention, This greatly reduces the number of steps. The formation of the through hole can be dealt with only by changing the mask pattern at the time of dry etching as described in the first embodiment. When the semiconductor device has this configuration, it is necessary to add the following step in addition to the processing of the concave portion and the back grinding step.

First, in the semiconductor substrate, since the inner wall of the concave portion processed to form a via hole is made of a conductive material of silicon, a step of forming an insulating material on the inner wall of the concave portion is required. Then, a step of embedding a conductive material inside the concave portion where the insulating material is formed on the inner wall surface is required. At this time, the conductive material is buried only in the portion to be the via hole, or when the semiconductor chip is manufactured by the wafer dividing method described in the first embodiment, the conductive material is buried only in the separation line after back grinding. A step of removing the conductive material is required.

Next, a step of forming an insulating material on the inner wall of the through hole to form a via hole in the semiconductor chip will be described.

Examples of the insulating material include silicon compounds such as silicon oxide and silicon nitride, metal oxides such as aluminum, tungsten, titanium and tantalum, and organic compounds. Films made of these materials can be formed by a normal thin film forming method. That is, the plasma CV
Any method such as CVD such as D, normal pressure CVD, and LP-CVD, sputtering, vapor deposition, and solvent coating may be used.

Further, the silicon constituting the semiconductor substrate may be subjected to field oxidation as it is. Needless to say, a film formation method that requires a temperature and an electric charge to damage a semiconductor element formed on a semiconductor substrate cannot be adopted.

Most preferably, silicon nitride or low-temperature SiO ₂ film formation by LP-CVD can be mentioned. LP-
Since CVD forms a film at a low pressure, the free process of molecules is long, and a good quality film can be uniformly formed on the inner wall surface of the concave portion. When it is necessary to form a film at a low temperature, it is preferable to spin coat a commercially available organic passivation material as it is, or to dilute and apply the material.

At this time, it is necessary to optimize the conditions for diluting and coating the material so that air bubbles do not enter the bottom of the concave portion and unevenness in the film thickness does not occur. Further, the depth of the concave portion may be set to a predetermined depth or more, and the uneven portion of the insulating film formed on the inner wall surface may be removed during back grinding. Examples of these organic passivation materials include many materials such as polyetheramide and imide precursors such as HIMAL and PIQ provided by Hitachi Chemical Co., Ltd., and Photo Nice provided by Toray Industries, Inc.

The thickness of these insulating films may be any as long as the films have good insulating properties and do not have pinholes, etc., but are most preferably about 0.1 to 5 μm. When the film thickness is 0.1 μm or less, it is extremely difficult to obtain a film without pinholes, and when the film thickness is 5 μm or more,
In many cases, the strength of the semiconductor chip is reduced due to the internal stress of the film forming material or the difference in the coefficient of linear expansion from silicon.

Next, a process of embedding a conductive material inside a through hole to form a via hole in a semiconductor chip will be described.

Examples of the method of embedding the conductive material include plating, metal CVD, and application of a metal resin dispersion paste. In addition, any metal such as aluminum, tungsten, titanium, copper, silver, and gold may be used as the metal material. As a plating method, any method such as a method of performing electroplating after forming a plating base metal by sputtering or the like, or a method of performing electroplating after performing electroless nickel plating may be used. Metal C
In recent years, various types of VDs have been developed for semiconductors, using tungsten using WF ₆ , aluminum using Al (CH ₃ ) _3, etc., and Cu-HFAC-TMVS (hexafluoroacetylacetonate-trimethylvinylsilane). Copper etc. can be mentioned. Alternatively, a resin varnish of a conductive material such as a general-purpose silver paste or a carbon paste may be applied and then baked and hardened.

In a configuration in which a conductive material is embedded in the through hole serving as a via hole and the conductive member is not embedded in the separation portion, a mask may be formed in the groove of the separation line before the conductive material is embedded. After embedding the conductive material, it is necessary to mask the conductive material in the concave portion for the via hole to remove the conductive material in the separation portion.

FIGS. 7 to 10 are sectional views showing an example of a process flow for simultaneously forming a via hole penetrating a silicon substrate and separating a semiconductor chip.

As shown in FIG. 7A, a plurality of aluminum pads 52 serving as electrode portions and a plurality of passivation films 53 are formed on a silicon substrate 51 which is a wafer having a circular outer shape. A resist 54a is formed on each surface of the aluminum pad 52 and the passivation film 53 by patterning. On the surface of the silicon substrate 51, a portion corresponding to the separation groove along the division line and a portion corresponding to the via hole are exposed.

Next, as shown in FIG. 7B, ICP-RI is applied to the silicon substrate 51 using the resist 54a as a mask.
E, that is, trench etching is performed to form in the silicon substrate 51 a trench hole 55a which is a dividing groove of the silicon substrate 51 and a concave portion 55b for forming a via hole penetrating the silicon substrate 51. The depths of the trench hole 55a and the concave portion 55b are substantially the same.

Next, as shown in FIG. 7C, a resist 5 on the aluminum pad 52 and the passivation film 53 is formed.
4a is peeled off and removed.

Next, as shown in FIG. 8A, the entire inner wall of each of trench hole 55a and concave portion 55b, the entire surface of aluminum pad 52, and the entire surface of passivation film 53 are covered with an insulating material made of an insulating material. A film 19 is formed.

Next, as shown in FIG. 8B, the conductive material 20 is formed on the entire surface of the insulating film 19 so that the conductive material 20 is embedded in the trench holes 55a and the concave portions 55b.

Next, as shown in FIG. 8C, unnecessary portions are removed by metal polishing for polishing the conductive material 20. At this time, by polishing up to the passivation film 53, all unnecessary metals on the film are removed.

Next, as shown in FIG. 9A, except for the surface of the conductive material 20 connected to the trench hole 55a, the surface of the conductive material 20 in other portions and the surface of the passivation film 53 are formed. A resist 54b is formed by patterning. Using this resist 54b as a mask,
After the conductive material 20 in the trench hole 55a is removed by etching, the resist 54b is removed as shown in FIG.

Next, as shown in FIG.
A connection bump 76 is formed on the surface of the conductive material 20 connected to the inside, that is, on the surface of the electrode pad portion.

Next, as shown in FIG. 10A, a back grinding tape 56 as a holding sheet was attached to the entire bump 76 side of the silicon substrate 51, that is, the surface of the passivation film 53 and the bumps 76. Thereafter, the back surface of the silicon substrate 52 on the side opposite to the bump 76 side is ground and polished until it reaches the trench hole 55a and the concave portion 55b, and the silicon substrate 52 is thinned by back grinding. At this time, the silicon substrate 52 is thinned so that the conductive material 20 in the concave portion 55b is exposed on the back surface of the silicon substrate 51 and an opening end of the trench hole 55a is formed on the back surface of the silicon substrate 51. This allows
The recess 55 b is formed in a through hole 55 penetrating the silicon substrate 51.
c, and a via hole 75 formed by filling the through hole 55 c with the conductive material 20 is formed in the silicon substrate 5.
1 and at the same time, the silicon substrate 51
Is divided into a plurality of semiconductor chips 81 by trench holes 55a.

Next, as shown in FIG. 10B, the back grinding tape 56 is peeled off from each of the semiconductor chips 81.

Then, as shown in FIG. 10C, the conductive material 20 in the via hole 75 is electrically connected to the aluminum pad of the interposer 88 as the mounting substrate via the bump 76a. The semiconductor chip 81 is mounted on the interposer 88 via the plurality of bumps 76a. Next, the semiconductor chip 81a is stacked on the semiconductor chip 81 via the bumps 76 on the semiconductor chip 81. The configuration of the semiconductor chip 81a is almost the same as the configuration of the semiconductor chip 81.
The main difference is that no bump is formed on the conductive material 20 in the via hole 75 formed in the semiconductor chip 81a. The conductive material 20 in the via hole 75 in the semiconductor chip 81a is
6 and is electrically connected to the conductive material 20 in the via hole 75 in the semiconductor chip 81.

Through the above steps, the interposer 88
A semiconductor device in which semiconductor chips 81 and 81a are three-dimensionally stacked and packaged thereon is manufactured.

Of course, in these basic steps, the use of lift-off or the use of a mask material as described above employs more developed examples in the film configuration and process of the device to be applied. be able to.

For the back grinding of the silicon substrate and the subsequent handling of the chip, the conventional technique may be applied as it is. These technical contents are disclosed in
No. 213662. General-purpose devices for grinding and polishing silicon substrates are provided by DISCO Corporation, Tokyo Seimitsu Co., Ltd., and Okamoto Machine Tool Co., Ltd.

[0096]

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited to these Examples.

Example 1 A semiconductor wafer having a structure in which an aluminum pad 2 was formed on a silicon substrate 1 as shown in FIG. 3A was used. Note that, in the semiconductor wafer, the film configuration below the aluminum wiring is omitted in FIG. On the surface of the aluminum pad 2, TiW is formed as a barrier metal 7 to a thickness of 2000 mm, and a passivation film 3 is formed.
The thickness of silicon nitride by plasma CVD is 5
A μm film was formed.

On the above-mentioned wafer, OFPR-800 manufactured by Tokyo Ohka Kogyo Co., Ltd. was applied as a general-purpose positive resist to a thickness of 7 μm, and then exposed to form a separation line pattern. The resist was applied by spin coating, baking was performed at 90 ° C. for 3 minutes, and exposure was performed by MPA-600FA manufactured by Canon Inc. at 1 J / cm ² . The development was performed using a developing solution NMD-3 manufactured by Clariant Co., Ltd., and hard baking was not performed. ICP manufactured by ULVAC Co., Ltd. using the resist pattern formed on the semiconductor wafer as a mask.
With a dry etching apparatus NLD-800, a silicon nitride film as a passivation film was processed.

The etching gas used was a gas obtained by adding 5 Vol% of oxygen to CF ₄ , the input power was 1000 W, the bias was 100 W, and the pressure of the etching gas was 0.8 Pa. Next, the resist was dissolved and removed with a dedicated remover (1112A manufactured by Tokyo Ohka Kogyo Co., Ltd.).

The processing of the concave grooves for separating the semiconductor chips was performed using an ICP-RIE apparatus E601 manufactured by ALCATEL. The apparatus is compatible with the Bosch process. Etching is performed using SF ₆ gas at an input power of 1200 W, a bias of 50 W, and a gas pressure of 1 Pa for 6 seconds, and a deposit of a protective film on the side wall of the etched portion is formed using C ₃ F _8. Input power 800W, bias 5
0W, gas pressure 5Pa, alternately repeat 2 seconds, Fukahori (De
ep) Trench etching was performed.

The width of the groove for separating the semiconductor chips, that is, the width of the etched portion was 10 μm, and the depth of the etched portion was 100 μm. The time required for this etching was 10 minutes.

Next, a back grinding tape was attached to the wafer surface side. FS-3323- made by Furukawa Electric Co., Ltd. as back grinding tape
330 was used. The tape is made by coating an acrylic adhesive on a polyolefin substrate, and the adhesive force of the adhesive is reduced by UV irradiation, so that a thinned semiconductor chip is picked up by the tape. It is easy to do. Wafer back grinding was performed using GNX200E manufactured by Okamoto Machine Tool Co., Ltd. In the apparatus, an etcher for performing etching with a mixed solution of hydrofluoric acid and nitric acid after back grinding is inlined, but no etching was performed in this embodiment. The back grind is performed by grinding the silicon substrate to a thickness of 90 μm with a # 350 diamond grinder and then # 200.
The silicon substrate was thinned to 70 μm with a No. 0 grinder.

Next, the back grinding tape was peeled off from the semiconductor chip by irradiating the semiconductor chip with an ultraviolet ray of ² J / cm ² using a UV irradiator UVM-200 manufactured by Furukawa Electric Co., Ltd. and separated by a chip separation pattern. Semiconductor chip was obtained.

Embodiment 2 In this embodiment, an example will be described in which a through hole is formed in a semiconductor substrate in a step of separating a semiconductor chip from a wafer, and a via hole for laminating the semiconductor chips is simultaneously formed.

In this embodiment, a semiconductor wafer having a structure in which an aluminum pad 2 is formed on a silicon substrate 1 as shown in FIG. 3A was used. On the surface of the aluminum pad 2, TiW is formed as a barrier metal 7 to a thickness of 2000 mm.
As the passivation film 3, silicon nitride was formed to a thickness of 5 μm by plasma CVD.

A 7 μm-thick OFPR-800 manufactured by Tokyo Ohka Kogyo Co., Ltd. was applied as a general-purpose positive resist on the wafer as described above, and then exposed to form a separation line pattern. The resist was applied by spin coating, baking was performed at 90 ° C. for 3 minutes, and exposure was performed by MPA-600FA manufactured by Canon Inc. at 1 J / cm ² . The development was performed using the above-mentioned developer NMD-3, and no hard baking was performed. ICP dry etching equipment NL manufactured by ULVAC, using the resist pattern formed on the semiconductor wafer as a mask.
In D-800, a silicon nitride film as a passivation film was processed.

The etching gas used was a gas obtained by adding 5 Vol% of oxygen to CF ₄ , the input power was 1000 W, the bias was 100 W, and the pressure of the etching gas was 0.8 Pa. Next, the resist was dissolved and removed with a dedicated remover (1112A manufactured by Tokyo Ohka Kogyo Co., Ltd.).

The processing of the concave grooves for separating the semiconductor chips was performed using an ICP-RIE device E601 manufactured by ALCATEL. The apparatus is compatible with the Bosch process. Etching is performed using SF ₆ gas at an input power of 1200 W, a bias of 50 W, and a gas pressure of 1 Pa for 6 seconds, and a deposit of a protective film on the side wall of the etched portion is formed using C ₃ F _8. Input power 800W, bias 5
0W, gas pressure 5Pa, alternately repeat 2 seconds, Fukahori (De
ep) Trench etching was performed. The cross section of the concave portion for forming the through hole for the via hole was a circle of φ20 μm, the width of the etched portion was 10 μm, and the depth of the etched portion was 100 μm. The time required for this etching was 10 minutes.

The aluminum pad was hardly etched by the barrier metal TiW formed on the surface of the aluminum pad. Next, a silicon nitride film was formed by LP-CVD in order to form an insulating film on the side wall of the recess for the via hole. LP-CVD is VERT manufactured by Kokusai Electric Inc.
Using EX-II, the deposition temperature was 750 ° C., the flow rate of SiH ₂ Cl ₂ gas was 70 cc / min, and the flow rate of nitrogen gas was 700 cc.
/ Min at a pressure of 100 Pa in the chamber.
The thickness of the insulating film formed on the inner wall of the recess was 0.5 μm. Next, copper was buried as a conductive material inside the concave portion where the insulating film was formed. LP-CV
A metal CVD method using a D apparatus was used. The LP-CV
VERTEX-II manufactured by Kokusai Electric Co., Ltd. was used as the D apparatus, and Cu- (HFAC-TMVS) was used as the gas. The substrate temperature is 300 ° C., the flow rate is 700 cc / min, and the gas pressure is 50
At 0 Pa, embedding of the conductive material in the recess was performed for 300 minutes. In this step, the thickness of the deposit (deposited film) is 15
However, since the conductive material is also formed isotropically from the side wall in the concave portion, the entire concave portion was filled with Cu.

Next, the back surface of the wafer was polished.
In the polishing, SPP-600AT manufactured by Okamoto Machine Tool Co., Ltd. was used, and alumina was used as a slurry. Polishing of the wafer was performed only for 17 μm, whereby Cu on the passivation film was completely removed. Then, using the above-described OFPR-800 as a photoresist, Cu in the groove of the etching line was removed by etching again. The patterning condition of the photoresist was hard baked at 120 ° C. after pattern formation in the same manner as described above. Next, Cu in the etched portion, that is, Cu in the groove of the etching line was removed by etching with an aqueous ferric chloride solution, and the resist on the wafer was removed by a plasma asher.

When three-dimensional mounting by lamination of semiconductor chips is performed, it is necessary to form bumps on pad portions here. However, the present invention relates to separation of semiconductor chips, and such mounting was not performed. . The bumps may be formed by any of the bump forming methods such as printing of cream solder, mounting of solder balls, transfer bump method of solder, and stud bump by gold wire.

Next, a back grinding tape was attached to the wafer surface side. FS-3323- made by Furukawa Electric Co., Ltd. as back grinding tape
330 was used. The tape is a polyolefin substrate coated with an acrylic adhesive, and the adhesive strength of the adhesive has been reduced by UV irradiation, so that thinned semiconductor chips are picked up by the tape. It is easy to do. Wafer back grinding was performed using GNX200E manufactured by Okamoto Machine Tool Co., Ltd. In the apparatus, an etcher for performing etching with a mixed solution of hydrofluoric acid and nitric acid after back grinding is inlined, but no etching was performed in this embodiment. The back grind is performed by grinding the silicon substrate to a thickness of 90 μm with a # 350 diamond grinder and then # 200.
The silicon substrate was thinned to 70 μm with a No. 0 grinder. As a result of this grinding, copper burrs embedded in the through holes for via holes were generated. Therefore, the copper burrs were removed by performing a light etch for 30 seconds with the above-mentioned ferric chloride solution.

Finally, the back grinding tape was separated from the semiconductor chip by irradiating it with ² J / cm ^{2 of} ultraviolet light using a UV irradiation apparatus UVM-200 manufactured by Furukawa Electric Co., Ltd. to obtain a separated semiconductor chip. Was. The semiconductor chips can be three-dimensionally stacked by forming bumps on the surface as described above. For example, when solder bumps are formed on a semiconductor chip, if a plurality of semiconductor chips are stacked and reflowed, electrical connection and fixing of the chip are performed by soldering, and then a general-purpose underfill agent is poured. Thus, an area array in which devices are stacked can be formed.

(Embodiment 3) In the present embodiment, a semiconductor chip having a non-rectangular outer shape is manufactured at the time of manufacturing a semiconductor device, and the chip can be laminated on an interposer and wire-bonded. explain.

In the same manner as in Example 1, a chip separation pattern for forming the S-RAM 10 having the comb-tooth shape shown in FIG. 5 was formed on the wafer. Next, as in Example 1, the wafer was divided to separate semiconductor chips. Glass epoxy (glass epoxy resin) was used as a constituent material of the interposer. As a lower semiconductor chip of the semiconductor chips stacked on the interposer, a rectangular flash memory created by a general-purpose dicing technique is die-bonded on the interposer, and the flash memory is used in this embodiment. The fabricated S-RAM having a comb-like outer shape was die-bonded. Die bonding was performed using E3032 manufactured by Emerson & Cumming as an epoxy die bonding material. Cure of die bonding agent is 1
Performed at 20 ° C. for 1 hour. At this time, the protrusion of the adhesive stopped due to the formation of a meniscus in the concave portion of the comb teeth, and the adhesive did not run on the pad portion of the lower semiconductor chip at all. Next, the upper and lower chips were wire-bonded to pads on the interposer with gold wires of φ30 μm, packaged by transfer molding, and solder balls were mounted on the lower surface of the interposer to produce a BGA. The configuration of the wire bond according to the present embodiment is shown in FIG. 5B in comparison with an example of a conventional semiconductor device configured by stacking only rectangular semiconductor chips. With such a configuration, a three-dimensional mounting device having a small chip area can be manufactured with high reliability.

[0116]

As described above, according to the present invention,
When dividing the wafer into individual semiconductor chips, a groove having a predetermined depth is formed by dry etching along the etching line on the formation surface of the semiconductor element on the wafer, and after attaching a holding sheet to the formation surface, Since the back surface of the wafer is ground and polished until it reaches the groove, the separation width for separating the semiconductor chips can be reduced, and the conventional chipping by dicing is not considered.
The layout of semiconductor devices on the wafer becomes possible,
The number of chips to be taken can be greatly increased.

[0117] In addition, except for the outer peripheral portion of the wafer,
By forming grooves for separating the wafer into individual semiconductor chips and not forming grooves for separation on the outer peripheral part of the wafer, it is possible to prevent chip jumps on the outer peripheral part of the wafer, and to improve the reliability of the wafer. Can be made thinner.

Further, since it is possible to manufacture a semiconductor chip having an outer shape other than a rectangular shape, for example, by making the end shape of the semiconductor chip into a comb shape, it is possible to design a semiconductor device by stacking semiconductor chips. The degree of freedom can be increased, and the yield and reliability of the device can be increased. Also, when stacking semiconductor chips, the process of dry etching for forming grooves for wafer separation is shared with the formation of via holes for three-dimensional mounting of chips, and is combined with the process of forming via holes penetrating the chips. Thus, the additional load of the dry etching step can be almost eliminated.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a basic process of separating a wafer into individual semiconductor chips by a wafer dividing method according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining another example of a wafer dividing method.

FIG. 3 is a sectional view for explaining still another example of a method of dividing a wafer.

FIG. 4 is a plan view showing an example of a separation pattern of a wafer.

FIG. 5 is a top view and a cross-sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 shows formation of a via hole penetrating a silicon substrate;
It is sectional drawing which shows an example of the process flow which performs isolation | separation of a semiconductor chip simultaneously.

FIG. 8 shows formation of a via hole penetrating a silicon substrate;
It is sectional drawing which shows an example of the process flow which performs isolation | separation of a semiconductor chip simultaneously.

FIG. 9 shows formation of a via hole penetrating a silicon substrate;
It is sectional drawing which shows an example of the process flow which performs isolation | separation of a semiconductor chip simultaneously.

FIG. 10 is a cross-sectional view showing an example of a process flow for simultaneously forming a via hole penetrating a silicon substrate and separating a semiconductor chip.

FIG. 11 is a cross-sectional view illustrating an example of a semiconductor device of a three-dimensional package in which two types of semiconductor chips are stacked and electrically connected by wire bonding.

FIG. 12 is a plan view showing an example of a wafer separation pattern.

[Explanation of symbols]

 1, 51 silicon substrate 2, 52 aluminum pad 3, 53 passivation film 4, 54a, 54b resist 5, 55a trench hole 6, 56 back grinding film 7 barrier metal 8, 28, 88 interposer 9, 29 flash memory 10, 30 S-RAM 10a Protrusion 10b, 55b Recess 11a, 11b Die bond 12a, 12b Gold wire 13, 33, 93 Solder ball 14, 34, 94 Package material 15a, 15b, 75 Via hole 16a, 16b, 76, 76a Bump 17 Wafer 18 Separation line 19 Insulating film 20 Conductive material 21, 81 Semiconductor chip 41 Wafer 42, 43 Separation pattern 55c Through hole

Claims (9)

[Claims] 1. A wafer dividing method for separating a wafer on which a plurality of semiconductor elements are formed into individual semiconductor chips, wherein the wafer is divided at a position corresponding to an outer shape of the semiconductor chip on a surface of the wafer on which the semiconductor elements are formed. Forming a groove of a predetermined depth by dry etching, affixing a holding sheet to the surface of the wafer on which the semiconductor elements are formed, and applying a back surface on the wafer opposite to the surface on which the semiconductor elements are formed, Grinding and polishing at least until the groove is reached, and separating the wafer into individual semiconductor chips. 2. In the step of forming the groove on the surface of the wafer on which the semiconductor element is formed, a groove for separating the wafer into the individual semiconductor chips is formed in a portion other than an outer peripheral portion of the wafer. The method for dividing a wafer according to claim 1. 3. The step of forming the groove on the surface of the wafer on which the semiconductor element is to be formed, wherein the groove is formed so that the end of the individual semiconductor chip separated from the wafer has a comb shape. 3. The method for dividing a wafer according to claim 1, wherein the wafer is formed. 4. In the step of forming the groove on the surface of the wafer on which the semiconductor element is formed, the individual semiconductor chips separated by grinding and polishing the wafer to form via holes in the semiconductor chip. Forming a recess for forming the through hole in the wafer simultaneously with the groove by dry etching so that a through hole penetrating the semiconductor chip is formed; and forming the groove and the recess in the wafer. A step of forming an insulating film on the inner wall surface of the concave portion, and a step of embedding a conductive material in the concave portion in which the insulating film is formed, separately grinding and polishing the back surface of the wafer to separate the wafer. 3. The method for dividing a wafer according to claim 1, which is provided before the step of separating into wafers. 5. A mounting substrate having an electrode portion, at least two semiconductor chips having an electrode portion and stacked on the mounting substrate, and an electrode portion of each of the semiconductor chips being an electrode portion of the mounting substrate. In a semiconductor device having a bonding wire for electrical connection, at least one of the plurality of semiconductor chips on the mounting substrate has a comb-shaped end portion. Semiconductor device. 6. A mounting substrate having an electrode portion, and at least two semiconductor chips produced by using the method of dividing a wafer according to claim 1, and stacked on the mounting substrate. A semiconductor device, wherein an electrical connection between an electrode of the mounting board and each of the semiconductor chips and an electrical connection between the semiconductor chips are performed by via holes penetrating each of the semiconductor chips. Semiconductor device. 7. At least two semiconductor chips produced by dividing a wafer are stacked on a mounting substrate, and the electrode portions of each of the stacked semiconductor chips are bonded to the electrode portions on the mounting substrate by bonding wires. In a semiconductor device manufacturing method for manufacturing a semiconductor device by electrically connecting, in the step of manufacturing the semiconductor chip by dividing the wafer, the shape of an end portion of the semiconductor chip becomes a comb-like shape. A method for manufacturing a semiconductor device, comprising dividing a wafer. 8. The step of dividing the wafer, wherein a groove having a predetermined depth is formed by dry etching at a position corresponding to the outer shape of the semiconductor chip on a surface of the semiconductor element forming surface of the wafer on which a plurality of semiconductor elements are formed. Forming, attaching a holding sheet to the surface of the wafer on which the semiconductor element is formed, grinding and polishing the back surface of the wafer opposite to the formation surface at least until the groove is reached, Separating the semiconductor device into individual semiconductor chips. 9. A mounting substrate having an electrode portion, and at least two semiconductor chips stacked on the mounting substrate, wherein an electrical connection between the electrodes of the mounting substrate and each of the semiconductor chips is provided, and A method of manufacturing a semiconductor device, wherein electrical connection between the semiconductor chips is performed by via holes penetrating each of the semiconductor chips, wherein a semiconductor element is formed on a surface of a wafer on which a plurality of semiconductor elements are formed. Forming a groove having a predetermined depth along an etching line corresponding to the outer shape of the semiconductor chip, and a concave portion for forming the via hole by dry etching; and insulating the inner wall surface of the concave portion of the wafer on the inner wall surface. A step of forming a film; a step of embedding a conductive material in the recess in which the insulating film is formed; The opposite back surface of the forming surface of the semiconductor element, the groove and the ground and polished until the recess, a method of manufacturing a semiconductor device and a step of separating the wafer into individual semiconductor chips that.