US8178977B2 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- US8178977B2 US8178977B2 US12/483,751 US48375109A US8178977B2 US 8178977 B2 US8178977 B2 US 8178977B2 US 48375109 A US48375109 A US 48375109A US 8178977 B2 US8178977 B2 US 8178977B2
- Authority
- US
- United States
- Prior art keywords
- hole
- concave portion
- insulating film
- semiconductor substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 239000004065 semiconductor Substances 0.000 title claims description 230
- 238000004519 manufacturing process Methods 0.000 title claims description 73
- 239000000758 substrate Substances 0.000 claims description 115
- 238000000034 method Methods 0.000 claims description 59
- 239000011229 interlayer Substances 0.000 claims description 37
- 239000010410 layer Substances 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 23
- 238000007747 plating Methods 0.000 claims description 22
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 description 25
- 238000000206 photolithography Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000000576 coating method Methods 0.000 description 9
- 239000010936 titanium Substances 0.000 description 9
- 238000004380 ashing Methods 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 239000003960 organic solvent Substances 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000007772 electrode material Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 230000012447 hatching Effects 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229960002050 hydrofluoric acid Drugs 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 238000004566 IR spectroscopy Methods 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000012945 sealing adhesive Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01018—Argon [Ar]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Definitions
- the present invention relates to a semiconductor device and a technique of manufacturing the same. More particularly, the present invention relates to a semiconductor device having a plurality of semiconductor chips stacked three-dimensionally.
- SiP System in Package
- chip semiconductor chips
- various packaging structures have been proposed. More particularly, the development of a stacked-type package which can realize a significant downsizing by stacking a plurality of chips has been promoted actively.
- the wire boding is used for the electrical connection between chips. This is because the wire bonding has high degree of freedom in layout and is effective for the connection of the plurality of semiconductor chips.
- Patent Document 1 discloses such a technique that electrodes obtained by burying solder or low melting point metal into the through-hole portions formed inside the chips by the electrolytic or electroless plating method are provided on upper and lower portions of the chips, and the chips are stacked and then heated, so that the chips are three-dimensionally stacked by the fusion bonding of the buried electrodes.
- Patent Document 2 discloses such a technique that a stud bump formed in an upper chip is deformed and injected into a hollow through-hole electrode formed in a lower chip by pressure welding, and the stud bump and the through-hole electrode are geometrically caulked, so that the chips are stacked.
- electrode materials are provided on an inner surface of the hole penetrating through the semiconductor substrate and in the periphery of the hole on a rear surface side of the semiconductor substrate in order to ensure a conductive path.
- the electrode material provided on the side surface of the hole is an inner electrode
- the electrode material provided in the periphery of the hole is a rear-surface wiring pad.
- Patent Document 2 Japanese Patent Application Laid-Open Publication No. 2007-053149
- Patent Document 2 Japanese Patent Application Laid-Open Publication No. 2007-053149
- the rear-surface wiring pad is formed outer than the rear surface of the semiconductor substrate, that is, on the rear surface of the semiconductor substrate, a convex portion caused by the rear-surface wiring pad is provided on the rear surface of the semiconductor substrate.
- the inventors of the present invention have found that air leakage is caused by the convex portion when the chip is sucked and this causes a reduction of a sucking force. Therefore, it is considered that a manufacturing yield of the semiconductor device is reduced.
- FIG. 1 is a schematic plan view of a rear surface of a chip 1 C which the inventors have studied. Note that hatching is attached in a part of FIG. 1 for easily understanding its configuration.
- a plurality of through-hole electrodes 4 are provided in a semiconductor substrate 1 configuring the chip 1 C, and a planar shape of each through-hole electrode is shown by a circular shape.
- a rear-surface wiring pad 4 d is provided in the periphery of the through-hole electrode 4 on a rear surface of the semiconductor substrate 1 , and it is electrically connected to the through-hole electrode 4 .
- a rear-surface wire 4 e is provided on the rear surface of the semiconductor substrate 1 so as to electrically connect between the rear-surface wiring pads 4 d . Note that the rear-surface wiring pad 4 d and the rear-surface wire 4 e are made of the same electrode material, and they are formed at the same time from the viewpoint of process efficiency.
- the convex portion is provided on the rear surface of the semiconductor substrate 1 as described above, and therefore, air leakage is caused when the chip 1 C is sucked and the reduction of the sucking force is caused.
- dummy rear-surface wiring pads 4 f are formed in a region where the rear-surface wiring pad 4 d and the rear-surface wire 4 e are not provided on the rear surface of the chip 1 C and a frame-shaped dummy rear-surface wire 4 g is formed in a peripheral region on the rear surface of the chip 1 C to arrange dummy rear-surface wiring pads on the whole rear surface of the chip.
- the method of providing the rear-surface wiring pad 4 d , the rear-surface wire 4 e , the dummy rear-surface wiring pad 4 f , and the dummy rear-surface wire 4 g for example, when an electrode material such as Au (gold) is used, Au is arranged on the whole rear surface of the chip 1 C, and therefore, there is a problem of the increase in the manufacturing cost of the through-hole electrode 4 . Further, there is also a problem that the thin and long pattern with the frame shape is likely to peel.
- An object of the present invention is to provide a technique capable of improving the manufacturing yield of the semiconductor device.
- Another object of the present invention is to provide a technique capable of reducing the manufacturing cost of the semiconductor device.
- a concave portion is provided so as to be wider than the patterns of a rear-surface wiring pad and a rear-surface wire on a rear surface side of a semiconductor substrate, and the rear-surface wiring pad and the rear-surface wire are provided inside the concave portion.
- a manufacturing yield of a semiconductor device can be improved.
- FIG. 1 is a schematic plan view of a rear surface of a semiconductor chip which the inventors of the present invention have studied;
- FIG. 3 is a schematic plan view of a principal part of a semiconductor device according to an embodiment of the present invention.
- FIG. 4 is a schematic sectional view of the semiconductor device in a line X 1 -X 1 of FIG. 3 ;
- FIG. 5 is a schematic sectional view of a principal part of a semiconductor device in a manufacturing process according to an embodiment of the present invention
- FIG. 6 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 5 ;
- FIG. 7 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 6 ;
- FIG. 8 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 7 ;
- FIG. 9 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 8 ;
- FIG. 10 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 9 ;
- FIG. 11 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 10 ;
- FIG. 12 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 11 ;
- FIG. 13 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 12 ;
- FIG. 14 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 13 ;
- FIG. 15 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 14 ;
- FIG. 16 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 15 ;
- FIG. 17 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 16 ;
- FIG. 18 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 17 ;
- FIG. 19 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 18 ;
- FIG. 20 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 19 ;
- FIG. 21 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 20 ;
- FIG. 22 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 21 ;
- FIG. 23 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 22 ;
- FIG. 24 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 23 ;
- FIG. 25 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 24 ;
- FIG. 26 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 25 ;
- FIG. 27 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 26 ;
- FIG. 28 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 27 ;
- FIG. 29 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 28 ;
- FIG. 30 is a schematic plan view of a principal part of a semiconductor device according to another embodiment of the present invention.
- FIG. 31 is a schematic sectional view of the semiconductor device in a line X 2 -X 2 of FIG. 30 ;
- FIG. 32 is a schematic plan view of a principal part of a semiconductor device according to still another embodiment of the present invention.
- FIG. 33 is a schematic sectional view of the semiconductor device in a line X 3 -X 3 of FIG. 32 ;
- FIG. 34 is a schematic sectional view of a principal part of a semiconductor device in a manufacturing process according to still another embodiment of the present invention.
- FIG. 35 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 34 ;
- FIG. 36 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 35 ;
- FIG. 37 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 36 ;
- FIG. 38 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 37 ;
- FIG. 39 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 38 ;
- FIG. 40 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 39 ;
- FIG. 41 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 40 ;
- FIG. 42 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 41 ;
- FIG. 43 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 42 ;
- FIG. 44 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 43 ;
- FIG. 46 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 45 ;
- FIG. 48 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 47 ;
- FIG. 49 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 48 ;
- FIG. 50 is a schematic sectional view of the principal part of the semiconductor device in the manufacturing process continued from FIG. 49 ;
- FIG. 52 is a schematic sectional view of a principal part of a semiconductor device according to still another embodiment of the present invention.
- FIG. 53 is a schematic plan view showing the semiconductor device of FIG. 52 in an exploded manner.
- a resist mask for forming a concave portion is formed on a rear surface (second surface) which is located on an opposite side to the main surface.
- a resist mask (second resist mask) for opening a hole is formed at a position inside the concave portion corresponding to a main-surface wiring pad (first conductive film) electrically connected to the semiconductor element on the main surface.
- a hole (first hole) reaching an interlayer insulating film on a surface of the semiconductor wafer is formed by the dry etching with using this resist mask, and then, after a process gas is changed, the hole (first hole) is formed further in the interlayer insulating film at least between the main-surface wiring pad and a boundary between silicon of the semiconductor wafer and the interlayer insulating film.
- the wafer is rinsed after the etching, and an insulating film is formed on an inner surface of the hole and on the rear surface of the semiconductor wafer by CVD method. Then, an Al (aluminum) film is formed for protecting the insulating film.
- a resist mask (third resist mask) having the opening portion in a part of a bottom surface of the hole is formed by the photolithography technique, and the Al film and the insulating film on the bottom surface of the hole and the interlayer insulating film on the bottom surface of the hole are processed by etching, so that a contact hole (second hole) reaching an electrode on the surface of the semiconductor wafer is formed.
- a metal seed layer is formed on the rear surface of the semiconductor wafer including inner surfaces and bottom surfaces of the concave portion, the hole, and the contact hole, and a resist mask (fourth resist mask) for plating to form the rear-surface wire and the rear-surface wiring pad is formed on the formed metal seed layer by the photolithography technique, and then, a plating layer is formed by the plating method.
- a cover of a resist mask (fifth resist mask) for protecting is provided on the rear-surface wiring pad and the rear-surface wire, and the metal seed layer is etched, thereby forming the rear-surface wire and the rear-surface wiring pad (second conductive film).
- FIG. 2 is a schematic plan view of the rear surface of the semiconductor chip to which the present invention is applied. Note that hatching is attached in a part of FIG. 2 for easily understanding the configuration.
- a concave portion 100 is provided so as to be wider than the patterns of a rear-surface wiring pad 4 d and a rear-surface wire 4 e , and the rear-surface wiring pad 4 d and the rear-surface wire 4 e are provided inside the concave portion 100 , so that the surface of the rear-surface wiring pad is prevented from being formed outer than the rear surface of the semiconductor substrate 1 (chip 1 C), thereby preventing the formation of the convex portion on the rear surface of the chip.
- the present invention in a semiconductor chip configuring a semiconductor device such as a microcomputer chip, the case where the present invention is applied when a through-hole electrode is provided in the semiconductor chip mounting a highly-integrated circuit (semiconductor element) will be described.
- the semiconductor chip is provided by cutting off from a wafer-like semiconductor substrate (semiconductor wafer) after forming the semiconductor element on the semiconductor substrate.
- the through-hole electrode is formed in the semiconductor chip in the wafer state.
- FIG. 3 is a schematic plan view of a principal part of a semiconductor device according to the present embodiment
- FIG. 4 is a schematic sectional view of the semiconductor device in a line X 1 -X 1 of FIG. 3 .
- the semiconductor substrate 1 has a main surface 1 x and a rear surface 1 y located on an opposite side of the main surface.
- a semiconductor element (not shown) is formed on the main surface 1 x of the semiconductor substrate 1 , and an interlayer insulating film 2 is formed on the main surface 1 x of the semiconductor substrate 1 so as to cover the semiconductor element.
- a main-surface wiring pad 4 a is formed on a topmost surface of the interlayer insulating film 2 and is provided via the interlayer insulating film 2 on the main surface 1 x of the semiconductor substrate 1 .
- a stud bump (bump electrode) 3 is formed on the main-surface wiring pad 4 a.
- the concave portion 100 is formed on the rear surface 1 y side of the semiconductor substrate 1 .
- a hole 5 reaching a portion between a surface of the interlayer insulating film 2 and the main-surface wiring pad 4 a is formed so as to penetrate through an inside of the semiconductor substrate 1 from a bottom surface of the concave portion 100 , and a contact hole 6 having a hole diameter smaller than that of the hole 5 is formed from the bottom surface of the hole 5 to the main-surface wiring pad 4 a so as to penetrate through an inside of the interlayer insulating film 2 .
- an insulating film 7 is formed on the rear surface 1 y of the semiconductor substrate 1 including the bottom surfaces and side surfaces of the hole 5 and the concave portion 100 . Since a stacked film (conductive film) of a metal seed layer 4 b and an Au film (configuring an inner electrode 4 c and a rear-surface wiring pad 4 d ) is configured along the concave portion 100 and the hole 5 via the insulating film 7 and along the contact hole 6 , the main-surface wiring pad 4 a , the metal seed layer 4 b , the inner electrode 4 c , and the rear-surface wiring pad 4 d are electrically connected to each other. Note that, although the Au film used in the present embodiment is a plating layer formed by the plating method, the film may be not only the Au film but also an Au/Ni stacked film and the like.
- the through-hole electrode 4 includes: the insulating film 7 formed on the bottom surface and side surface of the hole 5 and on the bottom surface of the concave portion 100 ; the rear-surface wiring pad 4 d formed on the bottom surface and side surface of the hole 5 and on the bottom surface of the concave portion 100 via the insulating film 7 and formed on the bottom surface of the contact hole 6 so as to be electrically connected to the main-surface wiring pad 4 a ; the metal seed layer 4 b ; and the inner electrode 4 c.
- the main-surface wiring pad 4 a is formed on a front surface side of the interlayer insulating film 2 via the interlayer insulating film 2 on the main surface 1 x of the semiconductor substrate 1 .
- the main-surface wiring pad 4 a is electrically insulated by the interlayer insulating film 2 from the semiconductor element formed on the main surface of the semiconductor substrate 1 , and can be formed from, for example, an Al film by using the photolithography method, the sputtering method, and the like.
- the thickness thereof when the thickness thereof is reduced to, for example, approximately 10 to 50 ⁇ m, the depth of the through-hole electrode to be formed is reduced, and the process difficulty is decreased.
- a reduction in thickness causes the reduction of substrate strength and the reduction of manufacturing yield due to the substrate warpage.
- back grinding process is performed to thinly grind the thickness of the semiconductor substrate 1 .
- the grinding method there are grinding, polishing, and the like. Since the flatness after grinding affects the accuracy of the formation of the rear-surface wiring pad to be formed on the rear surface 1 y of the substrate, it is preferable to perform dry polishing, etching, or CMP (Chemical Mechanical Polish).
- a photoresist is coated on the rear surface 1 y of the semiconductor substrate 1 , and a resist mask 102 for processing the concave portion is formed by the photolithography method.
- the resist coating method for example, the spinner coating is used. Note that a position of the mask formation is determined by confirming a device pattern on the main surface 1 x of the semiconductor substrate 1 by the Infrared Spectroscopy method.
- the concave portion 100 is formed by etching on the rear surface 1 y of the semiconductor substrate 1 with using the resist mask 102 by the dry etching equipment. More specifically, the concave portion 100 is formed by the performing anisotropic etching of the ICP-RIE (Inductively coupled plasma-Reactive ion etching). Note that SF 6 and C 4 F 8 are used as the process gas. A depth of the concave portion 100 is equal to or larger than a thickness (for example, approximately 2 ⁇ m) of the rear-surface wiring pad 4 d formed in later steps.
- ICP-RIE Inductively coupled plasma-Reactive ion etching
- the hole 5 is formed by performing the anisotropic etching of the ICP-RIE.
- SF 6 and C 4 F 8 are used as the process gas. Since silicon is normally etched with using a silicon oxide film as a mask in the dry etching of silicon, the etching by SF 6 and C 4 F 8 stops by the interlayer insulating film 2 mainly made of a silicon oxide film. A depth of the hole 5 at this time is determined by the thickness of the semiconductor substrate 1 .
- the hole 5 reaching the main-surface wiring pad 4 a may be formed by continuing the process of the interlayer insulating film 2 , but since the interlayer insulating film 2 contacting to the main-surface wiring pad 4 a is removed, the strength of the main-surface wiring pad 4 a is reduced. Therefore, as described later, the contact hole 6 having a hole diameter smaller than that of the hole 5 formed in the silicon portion is formed in an area reaching the main-surface wiring pad 4 a from a lower surface portion of the interlayer insulating film 2 .
- the insulating film 7 is formed by, for example, the CVD (Chemical vapor deposition) method on the whole rear surface 1 y of the semiconductor substrate 1 including the bottom surface and the side surface of each of the hole 5 and the concave portion 100 .
- the insulating film 7 is formed along an inner wall of the hole 5 and the rear surface 1 y of the semiconductor substrate 1 so as to cover these surfaces.
- silicon oxide, silicon nitride, and polyimide resin can be used as the insulating film 7 .
- an Al (aluminum) film 11 for protecting the insulating film is formed by, for example, the sputtering method so as to cover the insulating film 7 including the inner wall of the hole 5 and the concave portion 100 .
- the forming method thereof may be the vapor deposition.
- a photoresist (resist mask 12 ) is coated in a region including the inner wall of the hole 5 and the concave portion 100 .
- a coating method of the resist for example, there are the coating by a spinner and the coating by a spray.
- the spinner coating it is preferable to use a resist which can be coated to a thickness of 5 to 30 ⁇ m for filling the hole 5 .
- the resist can be coated along the hole 5 unlike the case of the spinner coating.
- the resist coated on the inner wall of the hole 5 is patterned to form the resist mask 12 for opening the contact hole on the bottom surface of the hole 5 .
- the resist mask 12 is formed to have a small opening diameter. Note that the Al film 11 for protecting the insulating film appears in the opening portion of the resist mask 12 .
- the inner electrode 4 c and an Au film (plating layer) 15 to be the rear-surface wiring pad 4 d are formed by, for example, the electrolytic plating method.
- the thickness of the plating film to be formed is preferably 1 ⁇ m or larger in view of the electrical resistance
- an inner diameter of the through-hole electrode 4 is adjusted so as to be a predetermined diameter by the thickness of the Au film 15 .
- the electroless plating method, the sputtering method, and the like are considered.
- a conductive film configuring the metal seed layer 4 b and the rear-surface wiring pad 4 d formed on the bottom surface of the concave portion 100 via the insulating film 7 and electrically connected to the main-surface wiring pad 4 a on the bottom surface of the contact hole 6 is formed.
- the resist mask 16 for protection is removed, thereby completing the process of the semiconductor substrate 1 .
- the supporting substrate 9 is peeled off from the semiconductor substrate 1 .
- the adhesive layer 8 has a thermoplastic property
- the peeling off is performed by heating.
- the wafer-like semiconductor substrate 1 is diced into the chips 1 C by the blade dicing. The dicing into the chip can be performed even in a state where the semiconductor substrate 1 is stuck to the supporting substrate 9 , but if the supporting substrate 9 is diced together with the semiconductor substrate 1 , the supporting substrate 9 cannot be reused. Although the handling thereof becomes difficult, the supporting substrate 9 can be reused when the semiconductor substrate 1 is diced after peeling off from the supporting substrate 9 .
- the present invention is applied when the through-hole electrode 4 is formed as described above, the formation of the convex portion on the rear surface 1 y of the chip 1 C (semiconductor substrate 1 ) can be prevented, so that the reduction of the sucking force of the chip can be prevented. Also, the reduction of the sucking force of the chip can be prevented at low cost as compared with the case of forming the frame-shaped dummy rear-surface wire and dummy rear-surface wiring pad of the rear-surface wiring pad 4 d on the rear surface 1 y of the chip 1 C. Accordingly, in the semiconductor device according to the present embodiment, the manufacturing yield can be improved and the manufacturing cost can be reduced.
- the present embodiment in a semiconductor chip configuring a semiconductor device such as a microcomputer chip, the case where the present invention is applied when a plurality of through-hole electrodes adjacent to each other are provided in the semiconductor chip mounting a highly-integrated circuit (semiconductor element) will be described. More specifically, while the case where one through-hole electrode is provided inside one concave portion has been described in the first embodiment, the case where a plurality of through-hole electrodes are provided inside one concave portion will be described in the present embodiment. Note that, since only a point of providing the plurality of through-hole electrodes inside one concave portion is different from the first embodiment, the same descriptions as those of the first embodiment will be omitted.
- FIG. 30 is a schematic plan view of a principal part of a semiconductor device according to the present embodiment
- FIG. 31 is a schematic sectional view of the semiconductor device in a line X 2 -X 2 of FIG. 30 .
- one to three through-hole electrodes 4 are provided inside the one concave portion 100 .
- the plurality of the through-hole electrodes 4 are provided on the semiconductor substrate 1 , for example, one through-hole electrode 4 can be provided inside the one concave portion 100 .
- the narrow pitch of the through-hole electrodes 4 is achieved by providing a plurality of through-hole electrodes 4 inside one concave portion 100 .
- the present invention in a semiconductor chip configuring a semiconductor device such as a microcomputer chip, the case where the present invention is applied when a through-hole electrode and a rear-surface wire for wire extension are provided in the semiconductor chip mounting a highly-integrated circuit (semiconductor element) will be described. Note that, since only a point of providing the rear-surface wire for wire extension in addition to the through-hole electrode inside the concave portion is different from the first embodiment, the same descriptions as those of the first embodiment will be omitted.
- FIG. 32 is a schematic plan view of a principal part of a semiconductor device according to the present embodiment
- FIG. 33 is a schematic sectional view of the semiconductor device in a line X 3 -X 3 of FIG. 32 .
- a semiconductor element (not shown) is formed on the main surface 1 x of the semiconductor substrate 1 , and the interlayer insulating film 2 is formed so as to cover the semiconductor element.
- the concave portion 100 is provided on the rear surface 1 y of the semiconductor substrate 1 , and the rear-surface wire 4 e configured of the metal seed layer 4 b and the inner electrode 4 c is provided inside the concave portion 100 .
- the rear-surface wire 4 e is formed inside the concave portion 100 , and the main surface 101 of the rear-surface wire 4 e is positioned inner than the rear surface 1 y of the semiconductor substrate 1 .
- the planar shape of the concave portion 100 is not limited to the illustrated shape as long as the concave portion 100 is larger than the rear-surface wire 4 e in a plan view.
- the concave portion 100 is provided so as to be wider than the pattern of the rear-surface wire 4 e and the rear-surface wire 4 e is provided inside the concave portion 100 , so that the main surface 101 of the rear-surface wire 4 e can be prevented from being formed outer than the rear surface 1 y of the semiconductor substrate 1 , and it is possible to prevent the formation of the convex portion on the rear surface 1 y of the semiconductor substrate 1 . Also, since the flatness of the rear surface 1 y of the semiconductor substrate 1 can be ensured, the reduction of the sucking force can be prevented when the substrate is handled as the chip 1 C. By this means, in the manufacture of the semiconductor device, the manufacturing yield can be improved and the manufacturing cost can be reduced.
- FIGS. 34 to 50 a manufacturing method of the semiconductor device shown in FIG. 33 , more particularly, a manufacturing method of the rear-surface wire 4 e will be described with reference to FIGS. 34 to 50 . Note that the description of FIGS. 5 to 7 which is the same steps as those of the first embodiment is omitted, and the subsequent steps will be described.
- a photoresist is coated on the semiconductor substrate 1 , and the resist mask 10 is formed by the photolithography method so as to cover the concave portion.
- the resist mask 10 is formed by the photolithography method so as to cover the concave portion.
- the residual resist mask 10 is rinsed by the organic solvent and oxygen ashing ( FIGS. 38 and 12 ).
- the insulating film 7 is formed by, for example, the CVD (Chemical vapor deposition) method on the whole rear surface 1 y of the semiconductor substrate 1 including the concave portion 100 .
- the insulating film 7 is formed along the inner wall and bottom surface inside the hole 5 so as to cover these surfaces ( FIG. 14 ).
- the Al film 11 is formed by, for example, the sputtering method so as to cover the insulating film 7 including the concave portion 100 .
- the Al film 11 for protecting the insulating film is formed also on the inner surface and bottom surface of the hole 5 ( FIG. 15 ).
- the forming method may be the vapor deposition method.
- the resist mask 12 is formed so as to cover the concave portion 100 .
- the Al film 11 for protecting the insulating film is removed by an etching solution for Al ( FIG. 43 ).
- the metal seed layer 13 is formed on the insulating film 7 as shown in FIG. 44 .
- the resist mask 14 for plating is formed by the photolithography technique on the metal seed layer 13 .
- the Au film 15 to be the rear-surface wire 4 e is formed by, for example, the electrolytic plating method on the metal seed layer 13 exposed from the opening portion of the resist mask 14 .
- the Au film 15 configures the inner electrode 4 c and the rear-surface wiring pad 4 d ( FIG. 24 ).
- the resist mask 14 for plating is removed from the semiconductor substrate 1 by the organic solvent and oxygen ashing ( FIG. 47 ).
- the resist is patterned by the photolithography process to form the resist mask 16 for protection on the metal seed layer 13 .
- the resist mask 16 for protection is formed so as to cover the hole 5 and the rear-surface wiring pad 4 d ( FIG. 26 ).
- the Au film and the Ti film which are the exposed metal seed layer 13 are removed by an etching solution for Au and an etching solution for Ti, respectively.
- the process of the semiconductor substrate 1 is completed ( FIG. 50 ).
- the rear-surface wire 4 e configured of the stacked film of the metal seed layer 13 and the Au film 15 is formed on the bottom surface of the concave portion 100 at the same time with the rear-surface wiring pad 4 d described in the first embodiment.
- the supporting substrate 9 is peeled off from the semiconductor substrate 1 .
- the adhesive layer 8 has a thermoplastic property
- the peeling off is performed by heating ( FIG. 51 ).
- the wafer-like semiconductor substrate 1 is diced into the chips 1 C by the blade dicing ( FIG. 33 ).
- the present invention is applied when the rear-surface wire 4 e is formed as described above, the formation of the convex portion on the rear surface 1 y of the chip 1 C (semiconductor substrate 1 ) can be prevented, so that the reduction of the sucking force of the chip can be prevented. Accordingly, in the semiconductor device according to the present embodiment, the manufacturing yield can be improved and the manufacturing cost can be reduced.
- FIG. 52 is a schematic sectional view of the semiconductor device according to the present embodiment
- FIG. 53 is a schematic plan view showing the semiconductor device of FIG. 52 in an exploded manner.
- an interposer chip 22 for rewiring is inserted between the two chips, and they are mounted on a wiring substrate 23 .
- the stud bump 3 formed in an upper chip is deformed and injected into the hollow through-hole electrode 4 formed in a lower chip by pressure welding, and the stud bump and the through-hole electrode are geometrically caulked, so that the chips are electrically connected to each other.
- Solder bumps 24 are formed on a lower side of the wiring substrate 23 and are used for external connection.
- the through-hole electrode 4 of the microcomputer chip 20 and the stud bump 3 of the interposer chip 22 are geometrically caulked, and the interposer chip 22 is stacked on the rear surface 1 y of the microcomputer chip 20 .
- the through-hole electrode 4 of the interposer chip 22 and the stud bump 3 of the SDRAM chip 21 are geometrically caulked, and the SDRAM chip 21 is stacked on the rear surface 1 y of the interposer chip 22 .
- a rear-surface wire 26 is formed on the rear surface 1 y of each of the chips, and the wires of the chips are three-dimensionally connected to each other via the through-hole electrode 4 to configure the three dimensional wiring. Therefore, the rear-surface wire 26 can be used as a same potential line, and the use as a ground line, a power supply line, and a signal line is conceivable. Since a wire inductance of the whole semiconductor device can be reduced by such a use, an operation speed can be increased.
- the present invention can be applied also to the case of caulking the through-hole electrode and a solder bump or a plating bump instead of the stud bump.
- the present invention is widely used for a semiconductor device, more particularly, for the manufacturing industry of a semiconductor device having a plurality of semiconductor chips stacked three-dimensionally.
Abstract
Description
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008-157844 | 2008-06-17 | ||
JP2008157844A JP4601686B2 (en) | 2008-06-17 | 2008-06-17 | Semiconductor device and manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090309218A1 US20090309218A1 (en) | 2009-12-17 |
US8178977B2 true US8178977B2 (en) | 2012-05-15 |
Family
ID=41413981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/483,751 Active 2030-03-12 US8178977B2 (en) | 2008-06-17 | 2009-06-12 | Semiconductor device and method of manufacturing the same |
Country Status (5)
Country | Link |
---|---|
US (1) | US8178977B2 (en) |
JP (1) | JP4601686B2 (en) |
KR (1) | KR20090131258A (en) |
CN (1) | CN101609828B (en) |
TW (1) | TWI390688B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140008815A1 (en) * | 2012-07-05 | 2014-01-09 | Samsung Electronics Co., Ltd. | Semiconductor Devices |
US9478512B2 (en) * | 2015-02-11 | 2016-10-25 | Dawning Leading Technology Inc. | Semiconductor packaging structure having stacked seed layers |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011171567A (en) * | 2010-02-19 | 2011-09-01 | Elpida Memory Inc | Method of manufacturing substrate structure, and method of manufacturing semiconductor device |
JP5423572B2 (en) * | 2010-05-07 | 2014-02-19 | セイコーエプソン株式会社 | Wiring board, piezoelectric oscillator, gyro sensor, and manufacturing method of wiring board |
JP5447316B2 (en) * | 2010-09-21 | 2014-03-19 | 株式会社大真空 | Electronic component package sealing member and electronic component package |
US8193015B2 (en) * | 2010-11-17 | 2012-06-05 | Pinecone Energies, Inc. | Method of forming a light-emitting-diode array with polymer between light emitting devices |
FR2970117B1 (en) * | 2010-12-29 | 2013-09-20 | St Microelectronics Crolles 2 | METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT CHIP WITH REAR-SIDE CONNECTION |
JP5810921B2 (en) * | 2012-01-06 | 2015-11-11 | 凸版印刷株式会社 | Manufacturing method of semiconductor device |
JP7353748B2 (en) | 2018-11-29 | 2023-10-02 | キヤノン株式会社 | Semiconductor device manufacturing method and semiconductor device |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5229647A (en) * | 1991-03-27 | 1993-07-20 | Micron Technology, Inc. | High density data storage using stacked wafers |
JP2000260934A (en) | 1999-03-05 | 2000-09-22 | Seiko Epson Corp | Manufacture for semiconductor device |
US20020047210A1 (en) * | 2000-10-23 | 2002-04-25 | Yuichiro Yamada | Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device |
US20020151171A1 (en) * | 2001-03-28 | 2002-10-17 | Seiko Epson Corporation | Semiconductor device and manufacturing method therefor, circuit substrate, and electronic apparatus |
US6608371B2 (en) * | 2000-08-04 | 2003-08-19 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment |
US20030160325A1 (en) * | 2002-02-22 | 2003-08-28 | Fujitsu Limited | Semiconductor device substrate and manufacturing method thereof and semiconductor package |
US20040061238A1 (en) * | 2002-09-30 | 2004-04-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6936913B2 (en) * | 2002-12-11 | 2005-08-30 | Northrop Grumman Corporation | High performance vias for vertical IC packaging |
US20050221601A1 (en) * | 2004-03-31 | 2005-10-06 | Nec Electronics Corporation | Semiconductor device and method for manufacturing the same |
JP2007053149A (en) | 2005-08-16 | 2007-03-01 | Renesas Technology Corp | Semiconductor wafer and its manufacturing method |
US20070052067A1 (en) * | 2005-08-31 | 2007-03-08 | Sanyo Electric Co., Ltd | Semiconductor device, method of manufacturing the same, circuit board, and method of manufacturing the same |
CN101055857A (en) | 2006-04-14 | 2007-10-17 | 夏普株式会社 | Semiconductor apparatus and method of producing the same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3629902B2 (en) * | 1997-06-30 | 2005-03-16 | 沖電気工業株式会社 | Wiring structure of semiconductor element and manufacturing method thereof |
TWI239629B (en) * | 2003-03-17 | 2005-09-11 | Seiko Epson Corp | Method of manufacturing semiconductor device, semiconductor device, circuit substrate and electronic apparatus |
JP4289146B2 (en) * | 2003-03-27 | 2009-07-01 | セイコーエプソン株式会社 | Manufacturing method of three-dimensional mounting type semiconductor device |
JP4441328B2 (en) * | 2004-05-25 | 2010-03-31 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
JP2006032518A (en) * | 2004-07-14 | 2006-02-02 | Sony Corp | Semiconductor device and its manufacturing method |
US20070035026A1 (en) * | 2005-08-15 | 2007-02-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via in semiconductor device |
-
2008
- 2008-06-17 JP JP2008157844A patent/JP4601686B2/en active Active
-
2009
- 2009-02-19 TW TW098105312A patent/TWI390688B/en active
- 2009-06-05 CN CN2009101426602A patent/CN101609828B/en active Active
- 2009-06-12 US US12/483,751 patent/US8178977B2/en active Active
- 2009-06-16 KR KR1020090053269A patent/KR20090131258A/en not_active Application Discontinuation
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5229647A (en) * | 1991-03-27 | 1993-07-20 | Micron Technology, Inc. | High density data storage using stacked wafers |
JP2000260934A (en) | 1999-03-05 | 2000-09-22 | Seiko Epson Corp | Manufacture for semiconductor device |
US6608371B2 (en) * | 2000-08-04 | 2003-08-19 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment |
US20020047210A1 (en) * | 2000-10-23 | 2002-04-25 | Yuichiro Yamada | Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device |
US20020151171A1 (en) * | 2001-03-28 | 2002-10-17 | Seiko Epson Corporation | Semiconductor device and manufacturing method therefor, circuit substrate, and electronic apparatus |
US20030160325A1 (en) * | 2002-02-22 | 2003-08-28 | Fujitsu Limited | Semiconductor device substrate and manufacturing method thereof and semiconductor package |
US20040061238A1 (en) * | 2002-09-30 | 2004-04-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6936913B2 (en) * | 2002-12-11 | 2005-08-30 | Northrop Grumman Corporation | High performance vias for vertical IC packaging |
US20050221601A1 (en) * | 2004-03-31 | 2005-10-06 | Nec Electronics Corporation | Semiconductor device and method for manufacturing the same |
JP2007053149A (en) | 2005-08-16 | 2007-03-01 | Renesas Technology Corp | Semiconductor wafer and its manufacturing method |
US20070052067A1 (en) * | 2005-08-31 | 2007-03-08 | Sanyo Electric Co., Ltd | Semiconductor device, method of manufacturing the same, circuit board, and method of manufacturing the same |
US7646079B2 (en) * | 2005-08-31 | 2010-01-12 | Sanyo Electric Co., Ltd. | Semiconductor device, method of manufacturing the same, circuit board, and method of manufacturing the same |
CN101055857A (en) | 2006-04-14 | 2007-10-17 | 夏普株式会社 | Semiconductor apparatus and method of producing the same |
US20070241457A1 (en) | 2006-04-14 | 2007-10-18 | Sharp Kabushiki Kaisha | Semiconductor apparatus and method of producing the same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140008815A1 (en) * | 2012-07-05 | 2014-01-09 | Samsung Electronics Co., Ltd. | Semiconductor Devices |
US8836142B2 (en) * | 2012-07-05 | 2014-09-16 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US9478512B2 (en) * | 2015-02-11 | 2016-10-25 | Dawning Leading Technology Inc. | Semiconductor packaging structure having stacked seed layers |
Also Published As
Publication number | Publication date |
---|---|
TWI390688B (en) | 2013-03-21 |
JP2009302453A (en) | 2009-12-24 |
JP4601686B2 (en) | 2010-12-22 |
CN101609828A (en) | 2009-12-23 |
KR20090131258A (en) | 2009-12-28 |
TW201001645A (en) | 2010-01-01 |
CN101609828B (en) | 2012-04-25 |
US20090309218A1 (en) | 2009-12-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8178977B2 (en) | Semiconductor device and method of manufacturing the same | |
US7973415B2 (en) | Manufacturing process and structure of through silicon via | |
US9691739B2 (en) | Semiconductor device and method of manufacturing same | |
US8110900B2 (en) | Manufacturing process of semiconductor device and semiconductor device | |
US8283737B2 (en) | MEMS package and method of manufacturing the MEMS package | |
KR100671921B1 (en) | Semiconductor device and manufacturing method thereof | |
US9337097B2 (en) | Chip package and method for forming the same | |
KR100840502B1 (en) | Semiconductor device and manufacturing mathod thereof | |
KR20000059861A (en) | A wire arrayed chip size package and the fabrication method thereof | |
US20100327448A1 (en) | Semiconductor with Bottom-Side Wrap-Around Flange Contact | |
US10014240B1 (en) | Embedded component package and fabrication method | |
JP2002025948A (en) | Dividing method of wafer, semiconductor device and manufacturing method thereof | |
JP5101157B2 (en) | Manufacturing method of semiconductor device | |
US20080142945A1 (en) | Semiconductor package with redistribution layer of semiconductor chip directly contacted with substrate and method of fabricating the same | |
JP4511148B2 (en) | Manufacturing method of semiconductor device | |
WO2022052072A1 (en) | Fan-out type packaging structure and production method therefor | |
US20090324906A1 (en) | Semiconductor with top-side wrap-around flange contact | |
JP2012134526A (en) | Semiconductor device | |
JP2008016527A (en) | Semiconductor device and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: RENESAS TECHNOLOGY CORP., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KAWASHITA, MICHIHIRO;YOSHIMURA, YASUHIRO;TANAKA, NAOTAKA;AND OTHERS;SIGNING DATES FROM 20090417 TO 20090511;REEL/FRAME:022820/0196 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: MERGER AND CHANGE OF NAME;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:024953/0672 Effective date: 20100401 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: TESSERA ADVANCED TECHNOLOGIES, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RENESAS ELECTRONICS CORPORATION;REEL/FRAME:032892/0212 Effective date: 20140318 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: ROYAL BANK OF CANADA, AS COLLATERAL AGENT, CANADA Free format text: SECURITY INTEREST;ASSIGNORS:INVENSAS CORPORATION;TESSERA, INC.;TESSERA ADVANCED TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040797/0001 Effective date: 20161201 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., NORTH CAROLINA Free format text: SECURITY INTEREST;ASSIGNORS:ROVI SOLUTIONS CORPORATION;ROVI TECHNOLOGIES CORPORATION;ROVI GUIDES, INC.;AND OTHERS;REEL/FRAME:053468/0001 Effective date: 20200601 |
|
AS | Assignment |
Owner name: DTS LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: TESSERA, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: DTS, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: IBIQUITY DIGITAL CORPORATION, MARYLAND Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.), CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: INVENSAS CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: PHORUS, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS), CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: TESSERA ADVANCED TECHNOLOGIES, INC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |