JP2000260934A - Manufacture for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively perform many laminations by forming thick lands at through holes of chips and at electrode parts on the front and rear surface of pad parts, next by laminating each chip and after that by contacting and junctioning conductive material on the front surface of the lower side chip and on the rear surface of the upper side chip by heat melting. SOLUTION: Lands in which conductive material is implanted are formed at through holes 13 of semiconductor chips 16, 17 and 18 at electrode 12 parts on the front and rear surfaces of pad parts. The conductive material by which the lands of electrode 12 parts are formed is made thicker than the height of the elements, and each semiconductor chip 16, 17 and 18 is laminated more than two layers. After that, each conductive material which forms the lands on the surface of the lower side chip and which forms the lands on the surface of the upper side chip is melted by heating and is contacted and junctioned. By the means many laminations can effectively be performed and a three dimensional module can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a plurality of single elements are mounted in a hierarchical structure.

[0002]

2. Description of the Related Art In response to recent demands for high-density LSIs, three-dimensional LSI modules in which a plurality of LSI chips are stacked and integrated and electrically connected to each other have been proposed. Conventionally, this type of three-dimensional LSI module has a structure shown in FIG. In the configuration of FIG. 4, the first chip 41a of the LSI is mounted on the printed wiring board 40, and the second and third chips 41b and 41c are further mounted thereon.
Is mounted. Then, the electrode extraction pads 42a, 42b, 42c of the respective 41a, 41b, 41c and the electrode pads 42d on the printed wiring board 40 are electrically connected to each other by the metal wires 43 or the leads formed on the film carrier. However, in the configuration of these modules, since the LSIs to be modularized are connected by wires or leads, a mounting area for the wires or leads is required in addition to the size of the LSI chip. There is a problem that it is not advantageous in reducing the size of the device. In order to solve this problem, wireless and leadless structures that do not require wires or leads have been proposed (JP-A-5-63137, JP-A-8-264712). FIG. 5 shows an example of the three-dimensional LSI module. In FIG. 5, LSI chips 51a and 51b are stacked and mounted on a printed wiring board 50, and each chip is directly connected to an interconnect electrode provided between the chips. 57 is an internal circuit, and 58 is an insulating film. The configuration is such that interconnection electrode pads 52a and 52a between chips are provided.
Penetrating conductive layers 55 and 56 are formed above and below a 'and 52b and 52b'. Each L constituting the module
Between the SI chips 51a, 51b and the printed wiring board 50, wiring 54 between the electrode pads 52a 'and 52b for interconnection between bumps and between the electrode pads 52b' and 52b 'and external terminals.
They are connected by solder bumps 53a and 53b provided between them.

[0003]

With the structure shown in FIG. 5, the above-mentioned mounting area for wires or leads is unnecessary, so that an LSI module having a minimum necessary three-dimensional structure can be realized. However, in the above-described prior art, a conductive material electrically connected to each other is formed on both the front and back surfaces of each LSI chip constituting the module, and electrodes and bumps for connecting the upper chip back surface and the lower chip surface are formed. It had to be made separately. In addition, there is another problem that at least two chips must be stacked and connected to each other because it is necessary to perform pressure bonding depending on the metal used for the bumps.

Accordingly, it is an object of the present invention to solve the above-mentioned problems and to provide a highly integrated semiconductor device by efficiently stacking a larger number of devices.

[0005]

SUMMARY OF THE INVENTION The present invention is to solve the above-mentioned problems, and comprises the following means.

In the method of manufacturing a semiconductor device according to the present invention, a plurality of semiconductor chips are stacked at predetermined intervals in the height direction, and the through holes penetrating through the chip are formed on the front and back surfaces of electrode extraction pad portions of the chip. In a semiconductor device having electrodes to be connected and having a structure in which chips are connected to each other by the electrodes, a) a conductive material is buried in electrode portions on the front surface and the back surface of the through hole and the pad portion of the chip. Form a land
Further, the conductive material of the electrode portion is formed thicker than the element height. B) After at least two layers of the chips are stacked, the conductive material on the lower chip surface and the conductive material on the upper chip back surface are removed. It is characterized in that it is bonded and connected by melting by heating. That is, by adopting the structure of a), the conductive material formed in the through hole can be used as it is as the connection electrodes on the upper and lower portions of the chip. Further, by forming the conductive material to be thicker than the element, the conductive material on the front surface and the back surface can be surely brought into contact with the electrodes made of the conductive material on the upper and lower chips. According to the connection method b), the chips can be connected only by heating, so that no special device is required. Further, it is characterized in that the electrode is formed by electrolytic or electroless plating using solder or a low melting point metal as the conductive material. That is, by using the plating method, the embedding of the conductive material in the through hole and the electrode for connection can be simultaneously formed. Further, the present invention is characterized in that a plurality of the chips on which the electrodes have already been formed are laminated in a state where the electrode extraction pad portions are positioned, and these are simultaneously melted by heating to be bonded and connected. That is, a plurality of chips can be connected at the same time, and the manufacturing process can be shortened.

The inventors of the present invention have invented a method of manufacturing a semiconductor device having the above structure, and have succeeded in providing a highly integrated semiconductor device by efficiently stacking a larger number of semiconductor devices.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 2 shows a process of manufacturing a land of a conductive material for explaining an embodiment of the present invention. First, as shown in FIG. 1A, reference numeral 20 denotes a first chip having a thickness of 5 mm.
00 μm is used. 21 is an internal circuit, and 22 is a chip lead electrode. The lead electrode pad part of the chip is Al
Using, thickness 1μm, width 100μm, length 100μm
And The chip thickness and the size of the electrode portion can be freely changed depending on the chip to be designed. Further, as shown in FIG. 3B, a through hole 23 is formed in the chip lead electrode portion by laser irradiation. A through hole may be formed by anisotropic etching. At least a through hole having a diameter smaller than that of the chip routing electrode 22 is opened. Further, FIG.
An insulating film 24 such as a SiO ₂ film or a SiON film is formed on the side wall of the opened through hole by a vapor phase method as shown in FIG.
Grow about 00Å. Further, as shown in FIG. 3D, a photosensitive dry film 25 is applied to the front and back surfaces of the chip by 5 μm.
Exposure and development are performed to a thickness of m to expose the chip routing electrode section 26 and the electrode section 27 on the back surface. Thereafter, a Pd nucleus is formed on the electrode 26, the inside 28 of the through hole, and the electrode portion 27 on the back surface by the sensitizing and activating methods. Thereafter, the dry film is peeled off. Further, as shown in FIG. 3E, an electroless Pd plating solution (palladium chloride 2 g / L, ammonium hydroxide 1
The first chip 20 is immersed in 60 g / L, ammonium chloride 26 g / L, sodium phosphinate 10 g / L, and the solution temperature is 50 ° C., and Pd29 having a thickness of 1 μm is plated. Further, as shown in FIG. 2F, the chip 20 is immersed in solder (Pd: Sn = 38: 62%) melted at 200 ° C.
The solder land 29a was formed by filling the through hole 28 with solder. According to the above method, the lands described in claims 1 and 2 can be formed.

FIG. 1 shows a process of manufacturing a three-dimensional module for explaining an embodiment of the present invention. First, as shown in FIG. 1A, the first chip 10, the internal circuit 11,
It comprises a chip routing AL electrode 12, a through hole 13 for embedding a conductive material, and an insulating film 14. The first chip 10, the internal circuit 11, the electrodes 12 for interconnecting bumps, the formation of through holes, and the formation of an insulating film are shown in FIG.
It was manufactured through the processes of (b) and (c). Next, as shown in FIG. 1B, a conductive material 15 for connecting inside the through hole 13 and between chips is simultaneously formed to form a land. The land formation of the conductive material is shown in FIG.
It was manufactured through the processes of (e) and (f). Next, as shown in FIG. 1 (c), a first conductive material land is formed.
The chip 16, the second chip 17, the third chip 18 on which lands are formed by the same process, and the printed wiring board 19, which is formed by plating a conductive material in advance on the electrode, with the electrode portions positioned and the land portions in contact with each other Laminate. Next, the conductive materials of the first chip 16, the second chip 17, the third chip 18, and the printed wiring board 19 positioned as shown in FIG. In the first embodiment, three chips are stacked, but a plurality of chips can be stacked at the same time depending on the manufacturing mode. The three-dimensional module according to claim 1 and claim 3 can be formed by the above method.

(Embodiment 2) FIG. 3 shows a process of manufacturing a land of a conductive material for explaining an embodiment of the present invention. First, as shown in FIG. 1A, reference numeral 30 denotes a first chip having a thickness of 5 mm.
00 μm is used. 31 is an internal circuit, 32 is a chip lead-out electrode made of Al, having a thickness of 1 μm and a width of 100 μm.
μm and a length of 100 μm are used. The chip thickness and the size of the electrode portion can be freely changed depending on the chip to be designed. Further, as shown in FIG. 3B, a through hole 33 is formed in the chip lead electrode portion by laser irradiation.
A through hole may be formed by anisotropic etching. At least a through hole having a diameter smaller than that of the chip routing electrode 32 is opened. Further, an insulating film 34 such as a SiO ₂ or SiON film is grown on the side wall of the through hole opened as shown in FIG. Further, as shown in FIG. 2D, Au35 is grown on the chip surface and in the through hole by about 2000.degree. By a vapor phase method to form an electrode for plating. If the Au film does not sufficiently adhere to the inside of the through hole on the back side and the electrode portion on the back side, Au is further applied from the back side of the chip by a vapor phase method.
Is precipitated. Further, as shown in FIG. 3E, a photosensitive resist 36 is applied to a thickness of 2 μm and prebaked, and then exposed and developed to expose the chip lead-out electrode 32, the through hole 33 and the electrode portion 37 on the back surface. Further, the solder is electroplated (tin (Sn ²⁺ ) 40 g / L, lead (P
b) 15 g / L, free boric acid 100 g / L, formalin (37%) 10 g / L, dispersant 40 g / L: temperature 2
0 ° C., cathode current density 3 A / dm ² , anode Sn70-Pb
30) chip leading electrode 32, through hole 33
It is formed on the inner and back electrode portions 37. Further, as shown in FIG. 2F, the solder land 38 was formed by removing the photosensitive resist and etching the Au electrode. According to the above method, the lands described in claims 1 and 2 can be formed.

Further, as shown in FIG. 1C, a first chip 16 on which a land of a conductive material is formed, a second chip 17 on which a land is formed by the same process as in FIG.
A printed wiring board 19 in which a conductive material is previously formed by plating on the third chip 18 and the electrode portion is laminated with the electrode portion positioned and the land portion in contact. Next, the first chip 16 and the second chip 16 positioned as shown in FIG.
Chip 17, third chip 18, and printed wiring board 19
The conductive material was melted at 200 ° C. by batch heating and connected. In the second embodiment as well, the chips to be stacked are three layers, but more chips can be stacked at the same time depending on the form of manufacture. The three-dimensional module according to claim 1 and claim 3 can be formed by the above method.

[0013]

As described above, according to the present invention, a conductive material electrically connected to both the front and back surfaces of each of the LSI chips constituting the three-dimensional module is formed, and the electrodes for connecting the front and back surfaces are simultaneously formed. It has become possible to produce.
Also, it has become possible to connect a plurality of LSI chips simultaneously. As a result, a large number of LSI chips can be efficiently stacked and a highly integrated semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a manufacturing method of the present invention.

FIG. 2 is a diagram for explaining a land manufacturing method of the present invention.

FIG. 3 is a view for explaining a land manufacturing method according to the present invention.

FIG. 4 is a diagram for explaining a configuration of a conventional LSI module manufacturing apparatus.

FIG. 5 is a diagram for explaining a configuration of a conventional LSI module manufacturing apparatus.

[Explanation of symbols]

 10 first chip 11 internal circuit 12 chip routing electrode 13 through hole 14 insulating film 15 conductive material 16 first chip 17 second chip 18 third chip 19 printed wiring board 20 first chip 21 internal circuit 22 chip routing electrode Reference Signs List 23 through hole 24 insulating film 25 photosensitive dry film 26 chip lead electrode 27 back electrode 28 through hole 29 palladium 29a solder land 30 first chip 31 internal circuit 32 chip lead electrode 33 through hole 34 insulating film 35 gold 36 photosensitive Resist 37 Back surface electrode 38 Solder land 40 Printed wiring board 41a First chip 41b Second chip 41c Third chip 42a Electrode extraction pad 42b Electrode extraction pad 42c Electrode extraction pad 42d Electrode extraction pad 43 Metal wire 50 Printed wiring board 51 aLSI chip 51b LSI chip 52a Inter-chip interconnection electrode 52a 'Inter-chip interconnection electrode 52b Inter-chip interconnection electrode 52b' Inter-chip interconnection electrode 53a Solder bump 53b Solder bump 54 External terminal connection wiring 55 Penetrating conductive layer 56 penetrating conductive layer 57 internal circuit 58 insulating film

Continued on the front page F term (reference) 5F033 HH07 HH08 HH13 MM30 PP27 PP28 QQ16 QQ37 QQ53 QQ73 QQ75 RR04 RR08 SS11 VV07 XX00 XX33 XX34

Claims (3)

[Claims] 1. A semiconductor device comprising: a plurality of semiconductor chips stacked at predetermined intervals in a height direction; and electrodes connected to through-holes penetrating the chip on front and back surfaces of electrode extraction pad portions of the chip. A semiconductor device having a structure in which connection between chips is performed by electrodes, a) forming a land in which a conductive material is embedded in electrode portions on the front surface and the back surface of the through hole and the pad portion of the chip; B) forming at least two layers of the conductive material of the electrode portion thicker than the element height, and then heating the conductive material on the lower chip surface and the conductive material on the upper chip back surface by heating. A method for manufacturing a semiconductor device, characterized by bonding and connecting by melting. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said conductive material for forming said electrode is formed by electrolytic or electroless plating using solder or a low melting point metal. 3. A plurality of chips on which electrodes have already been formed are stacked in a state where electrode extraction pad portions are positioned, and are bonded and connected by simultaneously melting them by heating. 3. A method for manufacturing a semiconductor device according to claim 1.