JP2006287211A - Semiconductor device, stacked semiconductor device and method of fabricating the devices - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide semiconductor devices improved to enable reducing a resistance rise and a contact failure. <P>SOLUTION: In the semiconductor devices 150a, 150b and 150c having wiring layers 106, there exists a through-hole 110 that reaches the reverse surface from the upper surface of the semiconductor devices, and on an inner wall of the through-hole 110, each of the wiring layers exposes a part of its side wall. A conductive material 112 is placed inside the through-hole 110. The conductive material 112 is electrically connected to the part of the side wall of each wiring layer 106 inside the through-hole 110. According to the present invention, since it is enabled in stacking the semiconductor devices 150a, 150b, and 150c to make an arrangement without making any increase in the number of masks for forming the through-hole to be made by an increase in the number of stacked layers and since it is also enabled to form all the semiconductor devices through the use of a through-hole 110 of the same design size, down-sizing of the areas of the semiconductors is also feasible. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device that provides a stacked semiconductor device that is highly functional and miniaturized. The present invention also relates to a method for manufacturing such a semiconductor device and a stacked semiconductor device.

  Along with the higher functionality and smaller size of electronic devices, a stacked semiconductor device has been proposed in which a plurality of semiconductor devices are stacked and installed in the same package, thereby improving the functionality and size of the semiconductor device. .

  FIG. 11 is a cross-sectional view of a conventional stacked semiconductor device described in Patent Document 1, for example.

  Referring to FIG. 11, the conventional stacked semiconductor device includes a semiconductor device 201 a. 201 b and 201 c are stacked with an insulating film 202 interposed therebetween. An electrode 203 is provided in the exposed region of the surface of each layer, and the respective semiconductor devices 201 a, 201 b, 201 c are connected by wire wiring 204.

  However, in such a connection structure, when the number of stacked layers increases, the area of the semiconductor device on the upper layer side decreases due to the connection structure of the semiconductor devices between the upper and lower sides. With such a lamination method, semiconductor devices having the same area and the same structure cannot be laminated, and the lamination structure of the semiconductor device and the routing of the wire wiring 204 become complicated. Further, since the area of the upper semiconductor device is reduced, the number of wires connecting the upper and lower semiconductor devices is limited, the interval between the wire wirings 204 is narrowed, and there is a risk of a short circuit between the wire wirings 204. .

  Therefore, in order to overcome the problems of the area reduction of the upper-layer side semiconductor device to be stacked in the above-described stacked semiconductor device and the problem of short-circuiting between the wire wirings, for example, it is formed in the semiconductor device as disclosed in Patent Document 2. There has been proposed a method of connecting a semiconductor device by wiring using a through hole.

  FIG. 12 is a cross-sectional view of the stacked semiconductor device disclosed in Patent Document 2.

  Referring to FIG. 12, in this method, after stacking a plurality of semiconductor devices 301a, 301b, 301c via a first insulating film 302, the uppermost semiconductor device 301a is formed with a first mask pattern (not shown). A first through hole 306a is formed in the wiring electrode 303b to expose the wiring electrode 303b. After the removal of the first mask pattern, a second through hole 306b smaller than the first through hole previously opened with a second mask pattern (not shown) is formed, and the wiring electrode 303c is exposed. In the case of three or more layers, the third through hole 306c and the fourth through hole are formed in the same procedure. In this case, the size of the through hole to be formed becomes smaller as the lower layer is formed. A second insulating film 304 is formed on the side walls of the through holes 306a, 306b, and 306c.

  Next, the through holes 306a, 306b, and 306c formed by the above process are filled with a conductive material, and the semiconductor devices 301a, 301b, and 301c in each layer are electrically connected. According to the present technique, the through holes 306a. The conductive material can be filled into 306b and 306c at the same time, and the number of processes can be reduced at the same time.

JP-A-6-37250

JP 2001-44357 A

  However, in the method for forming a semiconductor device described in Patent Document 2, when the semiconductor devices are stacked, the upper semiconductor device needs to have a wider through hole than the lower semiconductor device. When manufacturing the devices 301a, 301b, and 301c, it is necessary to open through holes having different diameters for each layer, and there is a problem that masks having different opening diameters are required. Further, since the exposed areas of the wiring electrodes 303a, 303b, and 303c that form the connection holes are defined by the diameter of the uppermost through hole 306a of the stacked semiconductor device, there is a problem in reducing the area of the semiconductor device if this is increased. .

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device having a through-hole that can provide a stacked semiconductor device with a reduced semiconductor device area. To do.

  Another object of the present invention is to provide an improved semiconductor device so as to increase resistance and reduce contact failure.

  An object of the present invention is to provide a stacked semiconductor device formed by stacking such semiconductor devices.

  Another object of the present invention is to provide a method for manufacturing such a semiconductor device and a stacked semiconductor device.

  In the semiconductor device according to the present invention, in the semiconductor device having a wiring layer, there is a through hole reaching from the front surface to the back surface, and a part of the side wall of the wiring layer constituting the semiconductor device is exposed on the inner wall of the through hole. A conductive material exists in the through hole, and the conductive material is electrically connected to a part of the side wall of the wiring layer in the through hole.

  According to the present invention, since the side wall of the wiring layer is exposed on the inner wall of the through hole, semiconductor devices having the same design dimensions are stacked with the through holes connected to each other, and a plug is collectively formed in the through hole. A plurality of semiconductor devices can be easily connected, and high resistance and contact failure can be reduced. Further, there is no increase in the number of through-hole forming masks due to an increase in the number of stacked layers when stacking semiconductor devices. Furthermore, since all semiconductor devices can be formed with through holes having the same design dimensions, the area of the semiconductor device can be reduced.

  According to a preferred embodiment of the present invention, a plurality of wiring layers exposing the side wall at the inner wall of the through hole are formed in layers. In this case, it is preferable that the opening diameter of the upper end of the through hole is larger than the opening diameter of the portion exposing the side wall of the lower wiring layer.

  A laminated semiconductor device according to a preferred embodiment of the present invention is a semiconductor device obtained by laminating the above-described laminated semiconductor device and a semiconductor device in which a part of a wiring layer for connection is exposed on the substrate surface and there is no through hole. Therefore, the semiconductor device without the through hole is located in the lowermost layer of the stacked semiconductor, and the conductive material is formed to extend to the connection wiring layer of the lowermost semiconductor device. It is characterized by being connected.

  A method according to another aspect of the present invention relates to a method for manufacturing a semiconductor device in which a side wall of a wiring layer is exposed and is formed from a front surface to a back surface and a through hole is filled with a conductive material. First, a first insulating film is formed on the substrate surface. The first insulating film is selectively etched using a first mask pattern having a pattern for forming a wiring groove and a pattern of a through hole forming portion for forming the through hole, A wiring groove is formed. A conductor is embedded in the wiring groove to form a first wiring layer. A second insulating film is formed on the entire surface so as to cover the first wiring layer. A second mask pattern having an opening that is 0.1 to 20% larger in diameter than the through-hole forming portion is formed on the second insulating film above the through-hole forming portion. Using the second mask pattern, the second insulating film is removed by selective etching until the surface of the first wiring is exposed. Further, using the second mask pattern and the exposed first wiring layer as a mask, the through hole forming portion of the first insulating film is etched, and a part of the side wall of the first wiring layer is etched. Then, the substrate is etched to the back surface to form the through hole. A third insulating film is formed on the entire surface including the inside of the through hole. The surface side is etched back, and the third insulating film covering the side wall of the first wiring layer is removed. A fourth insulating film is formed on the back surface of the substrate. The through hole is filled with a conductive material, and a part of the side wall of the first wiring layer exposed in the through hole is electrically connected to the conductive material filled in the through hole.

  According to the method of the present invention, there is no increase in the number of through-hole forming masks due to an increase in the number of stacked layers when stacking semiconductor devices. Further, since all semiconductor devices can be formed with through holes having the same design dimensions, the area of the semiconductor device can be reduced. Furthermore, by making the opening of the second mask pattern 0.1 to 20% larger than the through hole forming portion, a part of the upper surface of the first wiring layer can be exposed.

  A method according to still another aspect of the present invention is a method of manufacturing a semiconductor device in which a side wall of a wiring layer is exposed and formed from a front surface to a back surface and a through hole is filled with a conductive material. A first insulating film is formed. A first conductive film is formed on the first insulating film. A first mask pattern having a pattern for forming a wiring layer and a pattern of a through hole forming portion for forming the through hole is formed on the first conductive film. The first wiring layer is formed by selectively etching the first conductive film using the first mask pattern. After removing the first mask pattern, a second insulating film is formed on the entire surface so as to cover the first wiring layer. A second mask pattern having an opening that is 0.1 to 20% larger in diameter than the through-hole forming portion is formed on the second insulating film above the through-hole forming portion. Using the second mask pattern, the second insulating film is removed by selective etching until the surface of the first wiring layer is exposed. Further, using the second mask pattern and the exposed first wiring layer as a mask, the through hole forming portion of the first insulating film is etched, and a part of the side wall of the first wiring layer is etched. Then, the substrate is etched to form the through hole. A third insulating film is formed on the entire surface including the inside of the through hole. The surface side is etched back, and the third insulating film covering the side wall of the first wiring layer is removed. A fourth insulating film is formed on the back surface of the substrate. The through hole is filled with a conductive material, and a part of the side wall of the first wiring layer exposed in the through hole is electrically connected to the conductive material filled in the through hole.

  In the above two types of manufacturing methods, the same step as the step of forming the first wiring layer on the first insulating film is repeated to form two or more wiring layers, and a plurality of wiring layers are formed on the inner wall of the through hole. It is preferable to expose the side wall of the wiring layer. According to this invention, it is possible to increase the contact area with the conductive material by installing a plurality of wiring sidewalls in the through hole in the manufacturing process, and it is possible to respond to the reduction of the diameter of the through hole. In this case, it is preferable to make the through hole opening diameter of the upper wiring portion larger than the through hole opening diameter of the lower wiring portion.

  Further, in the above method, the formation of the through hole is completed by etching the substrate using the first wiring layer as a mask when the depth of the hole falls within a range of 0.1 to 95% of the substrate film thickness. Then, after the step of forming the third insulating film and the step of removing the third insulating film, polishing may be performed from the back surface of the substrate until the holes are exposed.

  Further, in the above method, prior to the step of filling the through hole with a conductive material, a plurality of semiconductor substrate devices are stacked by stacking through holes of the same design, and are collectively conducted into the connected through holes. The material may be filled and the side wall of the wiring layer exposed in the through hole may be electrically connected to the conductive material filled in the through hole.

  In the method of filling the through hole with the conductive material, it is preferable to insert the conductive material into the through hole and melt the conductive material in the through hole.

  According to another preferred embodiment, before the step of filling the through hole with a conductive material, a part of the wiring layer for connection is exposed on the substrate surface, and the semiconductor for the bottom layer without the through hole Prepare the equipment separately. On the semiconductor device for the lowermost layer, a plurality of semiconductor devices having the through holes of the same design are overlaid and stacked, and the conductive material is melted and filled in the through holes. The wiring layer for connection of the semiconductor device for the lowermost layer is electrically connected to the semiconductor device of each layer.

  According to the present invention, by exposing the wiring to the side wall of the inner wall of the through hole, it is possible to stack the through holes of the same design dimensions and collectively form the through hole plugs to easily connect a plurality of semiconductor devices. And process simplification. Further, since there is no need to change the through-hole diameter for each semiconductor device, the number of masks to be created can be reduced and the area of the semiconductor device can be reduced. Further, by providing a plurality of wiring sidewalls exposed in the through hole, it is possible to suppress a decrease in contact area with the conductive material due to a reduction in the diameter of the through hole. Further, by using a metal (Cu, W, Au, etc.) having a high selectivity with respect to the substrate at the time of etching the Si substrate as a mask, deep through-holes can be formed more easily than using an insulating film mask.

  FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

  With reference to FIG. 1, a semiconductor device 150 includes a semiconductor substrate 101. Insulating films 102 and 107 are provided on the semiconductor substrate 101 so as to cover elements (not shown) provided on the semiconductor substrate 101. A wiring layer 106 is formed in a wiring groove 104 formed on the surface of the insulating film 102. In the semiconductor device, a through hole 110 is provided so as to expose the side wall 106a of the wiring layer from the front surface to the back surface. An exposed wall surface of the semiconductor substrate 101 exposed by the through hole 110 is covered with a sidewall insulating film 109. By exposing the wall surface 106a of the wiring layer 106 to the inner wall of the through hole 110, as will be described later, semiconductor devices having through holes of the same design dimension are stacked, and plugs are collectively formed in the through hole 110. Thus, a plurality of semiconductor devices can be easily connected.

  A method for manufacturing a semiconductor device according to an example will be described below with reference to the drawings.

  As shown in FIG. 2A, a first insulating film 102 is deposited so as to cover an element (not shown) on the semiconductor substrate 101, and a first mask for forming a wiring groove thereon is formed. A pattern 103 is formed. By using the first mask pattern 103 to dry-etch the first insulating film 102, a first wiring groove 104 is formed on the surface of the first insulating film 102.

The first insulating film 102 is an oxide film derived from TEOS and is formed by a CVD method within a thickness range of 100 to 1000 nm. In this embodiment, the first insulating film 102 is formed at a temperature of 50 to 100 ° C., a gas is TEOS / O ₂ , a supply amount is 680 mg / 650 cc, a pressure is 8.5 Torr, and a power is 800 W. , 800 nm deposited. The depth of the first wiring groove 104 is in the range of 100 to 1000 nm (400 nm in this embodiment).

  In a region where a through-hole serving as a wiring portion is formed in a later process, with reference to FIGS. 2A and 2A illustrated from above, insulation of a portion that is later etched away to become a wiring opening portion The film 105 is left. As will be described later, the insulating film 105 is removed by etching using the wiring layer as a mask at the time of later through-hole processing. The size of the insulating film 105 is in the range of 10 to 100 μm (in this embodiment, 50 μm square).

  Referring to FIGS. 2A and 2B, the first mask pattern 103 is removed, a conductive material is deposited on the entire surface, embedded in the first wiring groove 104, and a CMP method, an etch back method, or the like. The conductive material is removed by using means until the surface of the first insulating film 102 is exposed, and the first wiring layer 106 is formed in the first wiring groove 104.

  In this embodiment, Cu is used as the conductive material for the first wiring layer 106 in consideration of the selection ratio when the semiconductor substrate (silicon substrate) is etched. However, W, Au, or Ag is used. May be. Next, as shown in FIG. 2B and a plan view thereof, FIG. 2B, a second mask having an opening 108a for depositing a second insulating film 107 and forming a through hole is deposited. The pattern 108 is formed so that the opening 108 a overlaps the region of the insulating film 105.

  The second insulating film 107 is formed in a thickness range of 100 to 5000 nm (in this embodiment, 4000 nm deposition) under the same conditions as the first insulating film 102. The size of the opening 108a of the second resist mask 108 is larger than the range of the insulating film 105 (51 μm square in this embodiment).

  Next, referring to FIGS. 2B and 2C, the second insulating film 107 is removed using the second mask pattern 108 until the upper surface of the first wiring layer 106 is exposed. Then, using the second mask pattern 108 and the first wiring layer 106 as a mask, the insulating film 105 is dry-etched to expose a part 106a of the sidewall of the first wiring layer 106, and the surface of the semiconductor substrate 101 To expose. Thereafter, the second mask pattern 108 is removed.

Dry etching of the second insulating film 107 was performed under the conditions of gas C ₅ F ₈ / O ₂ / Ar, supply amounts 16/16/800 sccm, pressure 30 mmTorr, and RF-Power 1800 W, respectively. .

  Next, referring to FIG. 3D, using the second insulating film 107 and the first wiring layer 106 as a mask, the surface of the semiconductor substrate 101 is dry-etched to form a hole 101a having a depth of 10 to 100 μm. The third insulating film 109 is formed over the entire surface including the wall surface of the hole 101a, and then the third insulating film 109 is completely dried so as to expose a part 106a of the side wall of the first wiring layer 106. Etching is performed to form a sidewall 109 of the third insulating film. Here, conditions are selected so that this dry etching does not penetrate the semiconductor substrate 101, but may be penetrated.

Etching of the surface of the semiconductor substrate 101 is performed using SF ₆ / O ₂ gas. For example, the conditions according to the present embodiment are that the temperature is 50 to 100 ° C., the gas is SF ₆ / O ₂ , 150 cc, the pressure is 100 to 300 mTorr, and the RF-Power is 100 to 500 W. The depth of the hole 101a is 80 μm in this embodiment.

  The third insulating film 109 is formed in a thickness range of 50 to 500 nm (in this embodiment, 250 nm deposition) under the same conditions as the first insulating film 102. As the conditions for the entire surface dry etching for forming the sidewall 109 of the third insulating film, the same conditions as the etching of the second insulating film 107 in this embodiment are used.

  Next, with reference to FIGS. 3D and 3E, the back surface of the semiconductor substrate 101 is polished by chemical mechanical polishing (CMP) until the hole 101a is exposed, thereby forming the through hole 110. A fourth insulating film 111 is deposited on the back side of the semiconductor substrate 101 to form a semiconductor device 150.

  In the above-described embodiment, the processing using CMP for exposing the hole on the back surface is illustrated. However, the present invention is not limited to this, for example, processing using grinding, polishing, plasma etching, gas etching, or a combination thereof. May be.

The fourth insulating film 111 is an oxide film using TEOS and is formed by a CVD method within a thickness range of 100 to 1000 nm. In this embodiment, the fourth insulating film 111 is formed at a temperature of 50 to 100 ° C., a gas is TEOS / O ₂ , a supply amount is 680 mg / 650 cc, a pressure is 8.5 Torr, and a power is 800 W. , 100 nm deposited.

  Next, as shown in FIG. 4F, a plurality of semiconductor devices 150a and 150b of the same design formed as described above are stacked with the through-holes 110 overlapped, and the lowermost layer portion is separately provided. The prepared semiconductor device 151 having no through hole but having an opening 151a exposing a part of the connection wiring is stacked so that the through hole 110 and the opening 151a overlap. In the present embodiment, as a method of laminating the semiconductor devices 150a and 150b, the through hole and the upper layer through hole arranged in the lower layer are overlapped by visual observation from the upper surface, and the shift amount of the through hole is corrected to correct the lower layer semiconductor device. 151 and fix it.

  Next, as shown in FIG. 4G, a soldering wire 112 made of a conductive material is inserted into the through hole 110 and the opening 151a, bonded to the wiring portion 106 of the lowermost semiconductor device 151, and penetrated. The solder wire 112 is melted in the hole 110 to fill the through hole 110, and the side wall 106 a of the first wiring layer 106 exposed in the through hole 110 and the conductive material filled in the through hole 110 are electrically connected. Connect.

  In this embodiment, the through-holes 110 are provided with an interval of 100 μm so that the melt of the wire does not come into contact with the conductive material in the adjacent through-holes through the gap between the stacked semiconductor devices. ing.

  In the first embodiment, the first wiring layer having the embedded wiring structure is illustrated. However, as shown in FIG. 5A, the first insulating film 102 is deposited and then the conductive film 106 is deposited, and the third mask pattern 113 is used. The conductive film 106 is dry-etched to form the first wiring layer 106, and the subsequent steps are the same as in the above embodiment, so that FIG. 5B corresponding to the apparatus of FIG. A semiconductor device as shown can be formed. In the semiconductor device illustrated in FIG. 5B, the same or corresponding portions as those in the semiconductor device illustrated in FIG. 3E are denoted by the same reference numerals, and description thereof is not repeated. Even in this case, in the mask pattern 113 for forming the first wiring layer 106, a through hole corresponding to the opening 108a as shown in FIG. An opening 113a is provided for this purpose.

  In the above embodiment, the case where the semiconductor device 151 having no through hole in the lowermost layer is used in the formation of the stacked semiconductor device is illustrated. However, as shown in FIG. 6, the semiconductor device 150a having the through hole 110 according to the first embodiment. , 150b, and 150c, a conductive material wire 112 is inserted into the through hole 110, the wire 112 is melted to fill the through hole 110, and the first wiring layer exposed in the through hole 110 is exposed. The stacked semiconductor device may be configured by electrically connecting the side wall 106a of 106 and the conductive material filled in the through hole 110.

  In the figure, the case where the laminated semiconductor device has three layers is shown. However, if the laminated semiconductor structure of this embodiment is used, the connection can be made in the same manner even when four or more layers of semiconductor devices are used.

  In the above embodiment, the case where the number of wiring layers is one is exemplified, but a plurality of layers of two or more layers may be formed. FIG. 7 is a cross-sectional view of the semiconductor device according to the fourth embodiment. A plurality of wiring layers 407 and 403 are formed on the inner wall of the through hole 411 to expose the side wall. By providing a plurality of wiring sidewalls in the through hole 411, the contact area with the conductive material filled in the through hole 411 can be increased.

  Next, a manufacturing method will be described.

  Referring to FIG. 8A, a first insulating film 402 is formed so as to cover an element provided on a semiconductor substrate 401, and a wiring groove is provided on the surface of the first insulating film 402. The wiring layer 403 is formed. The first wiring layer 403 is provided with a through hole forming portion 404 that is an opening for forming a through hole in a later process. The process up to this point is the same as in the first embodiment. Next, a second insulating film 405 is deposited on the first insulating film 402, a second wiring groove is formed using a second mask pattern (not shown), and a second wiring 407 is formed. In addition, the second wiring 407 is provided with a through hole forming portion 408 which is an opening for forming a through hole in a later process. The through-hole forming portion 404 is superposed on the through-hole forming portion 404.

  Next, a third insulating film 409 is deposited on the second insulating film 405. Thereafter, a third mask pattern 410 for forming a through hole is formed so as to overlap the region of the through hole forming portion 408. Here, the second insulating film 405 and the third insulating film 409 are formed in a thickness range of 100 to 5000 nm (in this embodiment, 4000 nm deposition) under the same conditions as the first insulating film 402. The size of the opening 410a of the third mask pattern 410 is formed in a size larger than the through-hole forming portion 408 (51 μm square in this embodiment).

  Next, referring to FIGS. 8A and 8B, the third insulating film 409 is removed using the third mask pattern 410 until a part of the surface of the second wiring 407 is exposed. Then, using the third mask pattern 410 and the second wiring 407 as a mask, the second insulating film 405 and the through-hole forming portions 408 and 404 of the first insulating film 402 are dry-etched, and the second mask The side wall of the wiring layer 407 and a part of the side wall of the first wiring layer 403 are exposed, and the surface of the semiconductor substrate 401 is exposed. The dry etching conditions for the first to third insulating films 402, 405, and 409 are the same as the conditions in the above embodiment.

  Thereafter, through the same steps as in FIGS. 3D and 3E described above, a fourth insulating film 412 is formed on the back surface of the semiconductor substrate 401 as shown in FIG. A semiconductor device 450 is completed in which the inner wall of the substrate 401 is covered with the sidewall insulating film 410 and the side wall of the second wiring layer 407 and a part of the side wall of the first wiring layer 403 are exposed in the through hole 411.

  The present embodiment is related to the improvement of the fourth embodiment. FIG. 9 is a cross-sectional view of the semiconductor device according to the fifth embodiment. Referring to FIG. 9, the side walls of two or more layers of wirings 407 and 403 are exposed in the through hole 411, and the opening 408 of the upper layer wiring 407 is made wider than the opening 404 of the lower layer wiring 403. The exposure failure of the wiring side wall in the subsequent process due to the misalignment caused by the multilayer wiring formation is suppressed.

  Next, a manufacturing method will be described.

  Referring to FIG. 10A, a first insulating film 402 and a first wiring 403 are formed over a semiconductor substrate 401. A first wiring opening 404 is formed in the first wiring 403 for a through hole formed in a later process. Next, a second insulating film 405 is deposited, a second wiring groove is formed using a second mask pattern (not shown), and the second wiring 407 is embedded in the wiring groove. Form. A second wiring opening 408 is formed in the second wiring 407 for a through hole formed in a later process. The second wiring opening 408 is formed so as to overlap the first wiring opening 404. The dimension of the second wiring opening 408 is formed in a size larger than the first wiring opening 404 (51 μm square in this embodiment).

  Next, referring to FIG. 10B, a third insulating film 409 is deposited on the second insulating film 405, and a third mask pattern 410 having a pattern hole 410a for forming a through hole is formed. Are overlaid on the region of the second wiring opening 408. The second insulating film 405 and the third insulating film 409 are formed with a thickness of 100 to 5000 nm (in this embodiment, 4000 nm deposition) under the same conditions as the first insulating film 402. The dimension of the pattern hole 410 a for forming the through hole of the third mask pattern 410 is formed in a size larger than the second wiring opening 408 (52 μm square in this embodiment).

  Next, referring to FIG. 10C, the third insulating film 409 is removed using the third mask pattern 410 until the second wiring 407 is exposed. Using the second wiring 407 as a mask, the first insulating film 402 in the first wiring opening 404 is dry-etched to expose a side wall of the second wiring 407 and a part of the side wall of the first wiring 403, and Then, the surface of the semiconductor substrate 401 is exposed. The dry etching conditions for the first to third insulating films are the same as those in the above embodiment.

  Next, the semiconductor device 451 shown in FIG. 9 is completed through steps similar to those shown in FIGS.

  It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the present invention, when the semiconductor devices are stacked, the number of masks for forming the through holes is not increased even if the number of stacked layers is increased. In addition, since a stacked semiconductor device can be formed using semiconductor devices having through holes with the same design dimensions, the area of the semiconductor device can be reduced.

1 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention. (A) It is a partial cross section figure of the semiconductor device explaining the 1st process of the manufacturing method of the semiconductor device concerning Example 1. FIG. (B) It is a partial cross section figure of the semiconductor device explaining the 2nd process of the manufacturing method of the semiconductor device concerning Example 1. FIG. (C) It is a partial cross section figure of the semiconductor device explaining the 3rd process of the manufacturing method of the semiconductor device concerning Example 1. FIG. (A) It is a top view of the process of FIG. 2 (A). FIG. 2B is a plan view of the step of FIG. (D) It is a partial cross section figure of the semiconductor device explaining the 4th process of the manufacturing method of the semiconductor device concerning Example 1. FIG. (E) It is a partial cross section figure of the semiconductor device explaining the 5th process of the manufacturing method of the semiconductor device concerning Example 1. FIG. (F) It is a partial cross section figure of the semiconductor device explaining the 6th process of the manufacturing method of the semiconductor device concerning Example 1. FIG. (G) It is a partial cross section figure of the semiconductor device explaining the 7th process of the manufacturing method of the semiconductor device concerning Example 1. FIG. (A) It is sectional drawing of the semiconductor device concerning the 1st process of the manufacturing method of the semiconductor device concerning Example 2. FIG. (B) It is sectional drawing of the semiconductor device concerning Example 2. FIG. 7 is a cross-sectional view of a laminated semiconductor device according to Example 3. FIG. 7 is a cross-sectional view of a semiconductor device according to Example 4. FIG. 12 is a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 4. FIG. 7 is a cross-sectional view of a semiconductor device according to Example 5. FIG. FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device according to Example 5; It is sectional drawing of the conventional semiconductor device. It is sectional drawing of the semiconductor device concerning another prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101: Semiconductor substrate 102: 1st insulating film 103,113: 1st mask pattern 104: 1st wiring groove 105: Insulating film of wiring opening part 106: 1st wiring layer 107: 2nd insulating film 108 : Second mask pattern 109: sidewall of third insulating film 110: through hole 111: fourth insulating film 112: wire 150 a to 150 c: semiconductor device formed in this example 151: semiconductor device without through hole 201a, 201b, 201c: Semiconductor device 202: Insulating film 203: Electrode 204: Wire 301a, 301b, 301c: Semiconductor device 302: Insulating film 303: Electrode 304: Through-hole insulating film 305: Conductive material 401: Semiconductor substrate 402: First insulating film 403: first wiring layer 404: first wiring opening 405: second insulating film 407: second Wiring layer 408: second wiring opening 409: third insulating film 410: third mask pattern 411: fourth insulating film 412: fifth insulating film 451: semiconductor device

Claims (13)

In a semiconductor device having a wiring layer,
There is a through-hole that reaches from the front surface to the back surface,
A part of the side wall of the wiring layer constituting the semiconductor device is exposed on the inner wall of the through hole,
A semiconductor device, wherein a conductive material exists in the through hole, and the conductive material is electrically connected to a part of the side wall of the wiring layer in the through hole. A stacked semiconductor device in which a plurality of the semiconductor devices according to claim 1 are stacked so that the through holes are connected to each other,
A laminated semiconductor device, wherein the through holes connected to each other have the same design dimension. The semiconductor device according to claim 1,
A semiconductor device, wherein a plurality of wiring layers exposing a side wall at an inner wall of the through hole are formed in layers. The semiconductor device according to claim 3.
An opening diameter at an upper end of the through hole is made larger than an opening diameter of a portion exposing a side wall of a lower wiring layer. A laminated semiconductor device according to claim 2 and a semiconductor device in which a part of a wiring layer for connection is exposed on a substrate surface and a semiconductor device without a through hole is laminated,
The semiconductor device without the through hole is located in the lowermost layer of the stacked semiconductor, and the conductive material is formed to extend to the connection wiring layer of the lowermost semiconductor device. A stacked semiconductor device which is connected. A method of manufacturing a semiconductor device in which a side wall of a wiring layer is exposed, formed from a front surface to a back surface, and a through hole is filled with a conductive material,
Forming a first insulating film on the substrate surface;
The first insulating film is selectively etched using a first mask pattern having a pattern for forming a wiring groove and a pattern of a through hole forming portion for forming the through hole, Forming a wiring groove;
Burying a conductor in the wiring groove and forming a first wiring layer;
Forming a second insulating film over the entire surface so as to cover the first wiring layer;
Forming a second mask pattern having an opening larger than the through hole forming part by 0.1 to 20% on the second insulating film above the through hole forming part;
Removing the second insulating film by selective etching until the surface of the first wiring is exposed, using the second mask pattern;
Further, using the second mask pattern and the exposed first wiring layer as a mask, the through hole forming portion of the first insulating film is etched, and a part of the side wall of the first wiring layer is etched. Exposing and further etching the substrate to the back surface to form the through hole; and
Forming a third insulating film on the entire surface including the inside of the through hole;
Etching back the surface side and removing the third insulating film covering the side walls of the first wiring layer;
Forming a fourth insulating film on the back surface of the substrate;
Filling the through hole with a conductive material, and electrically connecting a part of the side wall of the first wiring layer exposed in the through hole and the conductive material filled in the through hole; A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device in which a side wall of a wiring layer is exposed, formed from a front surface to a back surface, and a through hole is filled with a conductive material,
Forming a first insulating film on the substrate surface;
Forming a first conductive film on the first insulating film;
Forming a first mask pattern having a pattern for forming a wiring layer and a pattern of a through hole forming portion for forming the through hole on the first conductive film;
Forming a first wiring layer by selectively etching the first conductive film using the first mask pattern;
Forming a second insulating film on the entire surface so as to cover the first wiring layer after removing the first mask pattern;
Forming on the second insulating film a second mask pattern having an opening that is 0.1 to 20% larger in diameter than the through-hole forming portion above the through-hole forming portion; Removing the second insulating film by selective etching using the mask pattern 2 until the surface of the first wiring layer is exposed;
Further, using the second mask pattern and the exposed first wiring layer as a mask, the through hole forming portion of the first insulating film is etched, and a part of the side wall of the first wiring layer is etched. Exposing and further etching the substrate to form the through hole; and
Forming a third insulating film on the entire surface including the inside of the through hole;
Etching back the surface side and removing the third insulating film covering the side walls of the first wiring layer;
Forming a fourth insulating film on the back surface of the substrate;
Filling the through hole with a conductive material, and electrically connecting a part of the side wall of the first wiring layer exposed in the through hole to the conductive material filled in the through hole. A method for manufacturing a semiconductor device. In the manufacturing method of Claims 6-7,
Repeating the same step as the step of forming the first wiring layer on the first insulating film, forming two or more wiring layers;
A method of manufacturing a semiconductor device, comprising exposing a side wall of a plurality of wiring layers to an inner wall of a through hole. In the manufacturing method of Claim 8,
A method of manufacturing a semiconductor device, wherein an opening diameter of a through hole in an upper wiring portion is larger than an opening diameter of a through hole in a lower wiring portion. In the manufacturing method of Claims 6-9,
The formation of the through hole is completed when etching the substrate using the first wiring layer as a mask when the depth of the hole is in the range of 0.1 to 95% of the substrate film thickness.
A method of manufacturing a semiconductor device, comprising: polishing after the step of forming the third insulating film and the step of removing the third insulating film until the hole is exposed from the back surface of the substrate. In the manufacturing method of Claims 6-10,
Prior to the step of filling the through hole with a conductive material, a plurality of semiconductor substrate devices are stacked with the same design of through holes,
A conductive material is collectively filled in connected through-holes, and the side wall of the wiring layer exposed in the through-hole is electrically connected to the conductive material filled in the through-hole. Production method. In the manufacturing method of the laminated semiconductor device according to claim 6,
The method of filling a conductive material into the through hole is a method of manufacturing a semiconductor device, wherein a conductive material is inserted into the through hole, and the conductive material is melted and filled in the through hole. In the manufacturing method of Claims 6-12,
Before the step of filling the through hole with a conductive material, a part of the wiring layer for connection is exposed on the substrate surface, and a semiconductor device for the lowermost layer having no through hole is separately prepared. A plurality of semiconductor devices having the through holes of the same design are stacked and stacked on the semiconductor device for
A semiconductor characterized in that a conductive material is melted and filled in the through-hole, and the conductive material electrically connects the wiring layer for connection of the semiconductor device for the lowermost layer and the semiconductor device of each layer. Device manufacturing method.

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