TW201515148A - Method of fabricating interconnection - Google Patents

Abstract

Provided is a method of fabricating an interconnection including the following steps. A substrate is provided, wherein a first dielectric layer is formed on the substrate and two plugs are formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer. A trench is formed in the second dielectric layer to expose the two plugs. A metal line is formed on each plug.

Description

Method of making interconnects

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating an interconnect in a semiconductor device.

In current semiconductor processes, tungsten is often used to fill contact vias to form so-called plugs or metal lines to connect metal layers to germanium or to connect different metal layers. Ideally, it would be desirable to have a lower resistivity of the material contacting the window to achieve a faster current conduction rate.

As the size of the IC components is reduced, the contact holes between the wiring layers become smaller and narrower, thereby increasing the gap-fill capability for the W metal line. Requirements. If the filling capacity of the tungsten wire is not good, a void or a seam is formed in the wire, which causes the resistance value of the tungsten wire to rise and the component performance to decrease.

Since tungsten is not adsorbed on the surface of cerium oxide when tungsten is formed by chemical vapor deposition (CVD), sometimes titanium oxide (TiN) is first filled in tungsten to ensure adhesion of tungsten. And when the formation of tungsten by the CVD method is prevented, the fluorine in the reactant tungsten hexafluoride (WF ₆ ) gas reacts with the cerium oxide. However, the resistance value of titanium nitride is higher than that of tungsten, which causes the resistance value of the tungsten wire to rise, resulting in a decrease in component performance.

The invention provides an interconnect structure and a manufacturing method thereof, and can manufacture a metal interconnect with high conductivity.

The method of fabricating the interconnect of the present invention includes the following steps. A substrate is provided on which a first dielectric layer has been formed and two plugs have been formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer. A trench exposing the two plugs is formed in the second dielectric layer. A metal wire is formed on each plug separately.

In an embodiment of the invention, the direction in which the trench extends is substantially perpendicular to the direction in which the two plugs are connected.

In an embodiment of the invention, a method of forming a metal wire on each plug respectively comprises: conformally forming a metal layer on the substrate; and the metal layer on the second dielectric layer and the location The metal layer between the two plugs.

In an embodiment of the invention, a method of forming a metal wire on each plug respectively includes forming a metal layer in the trench, the metal layer including a first portion and a second portion formed on opposite sidewalls of the trench And a third portion connecting the first portion and the second portion and formed at the bottom of the trench; and removing the third portion.

In an embodiment of the invention, after removing the third portion, the first portion forms a metal wire electrically connected to one of the two plugs, and the second portion forms and the two plugs The other of the other is electrically connected to another metal wire.

In an embodiment of the invention, a dielectric material is filled between the first portion and the second portion after the third portion is removed.

In an embodiment of the invention, prior to forming a metal wire on each plug, the method of fabricating the interconnect further includes conformally forming a barrier layer on the substrate.

In an embodiment of the invention, the method for fabricating the interconnect further includes removing the The barrier layer on the second dielectric layer and the barrier layer between the two plugs.

In an embodiment of the invention, the second dielectric layer is a composite dielectric layer comprising two different dielectric materials.

The interconnect structure of the present invention includes a first dielectric layer, a second dielectric layer, a plug, a wire, and a barrier layer. The second dielectric layer is disposed on the first dielectric layer. The plug is disposed in the first dielectric layer and extends to the second dielectric layer. The wire is disposed in the second dielectric layer and is located on the plug. The wires have opposite sides, and a barrier layer is disposed between one side of the wires and the second dielectric layer, and there is no barrier layer between the other side of the wires and the second dielectric layer.

Based on the above, the present invention provides an interconnect structure and a manufacturing method thereof, which can solve the problem that voids or gaps are formed inside the wires due to poor gap filling ability of the wire material, and the conductivity of the wires can be improved.

The above described features and advantages of the present invention will be more apparent from the following description.

100‧‧‧First dielectric layer

101‧‧‧ Cover layer

102‧‧‧ Plug

104‧‧‧Second dielectric layer

104a‧‧‧ lower dielectric layer

104b‧‧‧Upper dielectric layer

106‧‧‧ Ditch

108‧‧‧Barrier layer

110‧‧‧metal layer

110a‧‧‧Part 1

110b‧‧‧ part two

110c‧‧‧Part III

111‧‧‧Metal wire

112‧‧‧Dielectric materials

D‧‧‧ spacing

W‧‧‧Width

1A to FIG. 1I are flowcharts showing a method of fabricating an interconnect according to a first embodiment of the present invention.

A first embodiment of the present invention provides a method of fabricating an interconnect. FIG. 1A to FIG. 1I are schematic cross-sectional views showing the first embodiment.

Referring to FIG. 1A, in a first embodiment, a method of fabricating an interconnect includes providing a substrate. The substrate may be any type of semiconductor substrate, such as a germanium substrate or a blanket insulator (SOI) substrate, and various semiconductor components may have been formed in the substrate and communicated The plug and circuit layer of the component. Since the substrate can have a variety of variations, and regardless of how it varies, it is within the scope of the invention to be protected, and thus is not shown in the drawings.

A first dielectric layer 100 has been formed on the substrate, and at least two plugs 102 have been formed in the first dielectric layer 100. The material of the first dielectric layer 100 is, for example, hafnium oxide (SiO ₂ ); the material of the plug 102 is, for example, polycrystalline germanium or tungsten. The plug 102 will electrically connect the wires to be formed on the first dielectric layer 100 and the components that have been formed under the first dielectric layer 100. The manner in which the first dielectric layer 100 and the plugs 102 are formed is well known to those of ordinary skill in the art and will not be described herein.

Next, a second dielectric layer 104 is formed on the first dielectric layer 100. As shown in FIG. 1A, in the present embodiment, the second dielectric layer 104 is a composite dielectric layer including two different dielectric materials. Specifically, the second dielectric layer 104 may include a lower dielectric layer 104a and an upper dielectric layer 104b, wherein the material of the lower dielectric layer 104a is different from the first dielectric layer 100, such as tantalum nitride (SiN), The material of the upper dielectric layer 104b may be the same as the first dielectric layer 100, such as cerium oxide. Of course, the invention is not limited thereto, and the second dielectric layer 104 may also be a dielectric layer formed of a single material. Methods of forming the second dielectric layer 104 are also well known, for example, chemical vapor deposition (CVD) can be used, and other known methods are not described herein.

It should also be noted that the plug 102 extends from the first dielectric layer 100 to the second dielectric layer 104. In the present embodiment where the second dielectric layer 104 is a composite dielectric layer, the plug 102 is covered by the lower dielectric layer 104a of the second dielectric layer 104.

Referring to FIG. 1B, a patterned mask layer 101 is then formed on the second dielectric layer 104 to define the location of the trench to be formed. The mask layer 101 may be a photoresist (PR) or a hard mask, and may be formed by a lithography process or a lithography process with a dielectric etch process.

Referring to FIG. 1C, a trench 106 is formed in the second dielectric layer 104 by a dry etching method. Specifically, the dielectric layer 104a is used as an etch stop layer. The dielectric layer 104b is etched and the lower dielectric layer 104a is etched until the plug 102 is exposed. Each of the trenches 106 just exposes two plugs 102. 1C is a cross-sectional view of the trench 106. In other words, the direction in which the trench 106 extends (z direction) is substantially perpendicular to the plane of the paper, and is also perpendicular to the direction of the line connecting the two plugs 102 (x direction). At the same time, it should be noted that in the present embodiment, the width W of the trench 106 and the pitch D of the two plugs 102 are very close, but the former is slightly larger than the latter, so that the metal layer formed on the trench 106 may be located substantially at the plug. Above the 102, a wire electrically connecting the plug 102 is formed. More details on this point are provided below.

After the trench 106 is formed, the mask layer 101 can be removed.

Referring to FIG. 1D, a barrier layer 108 is conformally formed on the substrate. The material of the barrier layer 108 is selected to have a better affinity between the second dielectric layer 104 and the wire material to be filled in the trench 106, so that the wire material can be smoothly attached. On the side wall of the trench 106. In addition, the source gas of the wire material may react with the material of the second dielectric layer 104 during filling of the wire material, and the barrier layer 108 may also avoid this phenomenon. In this regard, in the case where the material of the second dielectric layer 104 is cerium oxide, and the material of the wire to be filled in the trench 106 is tungsten, the barrier layer 108 may be titanium/titanium nitride (Ti/TiN). The composite layer structure is formed by, for example, conformally forming a layer of titanium metal on the substrate, and then forming a layer of titanium nitride conformally covering the layer of titanium metal. Further, a method of forming a titanium metal layer and a titanium nitride layer may be performed by a reactive sputtering method or a nitridation reaction method.

Although the formation of the barrier layer 108 has the above advantages, the conductivity of the barrier layer 108 is generally inferior to that of the wire material. Therefore, the formation of the barrier layer 108 may also cause an increase in the resistance value of the entire wire, resulting in a decrease in component performance. This problem can be solved by the method of fabricating the interconnects proposed by the present invention, the details of which are as follows.

Referring to FIG. 1E, a metal layer 110 is conformally formed on the substrate. The material of the metal layer 110 is, for example, tungsten, and the formation method thereof is, for example, a chemical vapor deposition process using tungsten hexafluoride (WF ₆ ) as a source gas. Wherein, the metal layer 110 formed in the trench 106 includes a first portion 110a and a second portion 110b formed on opposite sidewalls of the trench 106, and connects the first portion 110a and the second portion 110b and is formed at the bottom of the trench 106. The third part 110c. As previously described, since the width of the trench 106 is substantially equivalent to the distance between the two plugs 102, the first portion 110a and the second portion 110b formed on the sidewalls of the trench 106 are substantially located in each of the first portion 110a and the second portion 110b. Above the plug 102.

Referring to FIG. 1F, the metal layer 110 over the second dielectric layer 104 is removed, and the third portion 110c of the metal layer 110 between the two plugs 102 is simultaneously removed. In the embodiment depicted in Figure 1F, the method of removal is dry etching. In addition to the third portion 110c, in addition, a portion of the top portions of the first portion 110a and the second portion 110b may also be removed. At this time, the remaining first portion 110a forms a metal wire electrically connected to its corresponding plug 102. Likewise, the remaining second portion 110b forms a metal wire that is electrically connected to the corresponding plug 102.

Referring to FIG. 1G, the barrier layer 108 over the second dielectric layer 104 is removed, and at the same time, the barrier layer 108 between the two plugs 102 at the bottom of the trench 106 is removed to avoid adjacent plugs. A short circuit is formed between the 102 due to the barrier layer 108. The method of removing the barrier layer 108 may be dry etching in the present embodiment.

Referring to FIG. 1H, a dielectric material 112 is then filled between the first portion 110a and the second portion 110b. The dielectric material 112 may be the same material as the second dielectric layer 104; or, in the embodiment where the second dielectric layer 104 is a composite layer, the dielectric material 112 may be the upper dielectric layer 110b Materials of the same material, such as cerium oxide. The method of forming the dielectric material 112 may be chemical vapor deposition, and it may be filled to the extent that the first portion 110a and the second portion 110b are covered.

Referring to FIG. 1I, then, a planarization process is performed to remove the excess dielectric material 112, exposing the first portion 110a and the second portion 110b, which are respectively the plug 102. The metal wire 111 is electrically connected to complete the fabrication of the metal interconnect. The planarization process is, for example, a chemical mechanical planarization (CMP) process.

Based on the manufacturing method described above, the present invention also provides an interconnect structure, which will be described below with reference to FIG. 1I, and will further explain the improvement of the interconnect structure of the present invention and its manufacturing method compared to the prior art. Where.

In general, the known method of making a wire on a plug is to first form a ditch for each plug, and then fill the wire material in each ditch. Taking FIG. 1I as an example, a total of four trenches respectively corresponding to one plug 102 are formed, and then the wire material is filled in the trench. With the miniaturization of semiconductor components, the distance between the plug and the plug is getting closer and closer, and the allowable width of the trench is getting smaller and smaller. When the wire material is filled in a small-sized trench, there may be a void or a seam inside the finally formed plug due to the limited gap filling ability of the wire material. These defects increase the resistance of the plug and may trap process gases and by-products such as WF ₃ , H _{2 ,} and HF, which may later diffuse out and cause metal corrosion, component damage, and reduced wafer reliability. . The aforementioned problems are particularly pronounced when the trench width is less than 40 nm.

Conversely, the method of the present invention does not form a trench corresponding to a single plug, but forms a trench corresponding to two plugs, and later forms a metal layer on the sidewall of the trench as a wire. Thereby, the width of the ditch is greatly improved. If, for example, FIG. 1I, the width of the trench can be increased from approximately equal to the width of the plug 102 to approximately equal to the distance between the two plugs 102. This largely solves the problem of limited gap filling ability of materials.

In addition, by observing any of the plugs 102 of FIG. 1I and their corresponding metal wires 111, it can be found that on the opposite sides of the metal wires 111, only one of the barrier layers between the one side and the second dielectric layer 104 is present. There is no barrier layer 108 between the other side and the second dielectric layer 104. Taking the leftmost metal wire 111 as an example, there is a barrier layer between the left side and the second dielectric layer 104. 108, and there is no barrier layer 108 between the right side and the second dielectric layer 104. Of course, this is a unique structure derived from the special process method of the present invention. Although the contact between the metal wire 111 and the dielectric material 112 may be slightly inferior on the side without the barrier layer 108, this does not affect the overall structural stability of the component. Moreover, since the metal wire 111 has a barrier layer 108 having a poor conductivity on one side, the metal wire 111 of the present invention can have a higher conductivity than a conventional metal wire having a barrier layer on both sides. Ability to further improve component performance.

In summary, the present invention provides an interconnect structure and a manufacturing method thereof, which can solve the problem that voids or gaps formed inside the wire due to poor gap filling ability of the wire material, and can improve the conductivity of the wire. .

Although the present invention has been described above by way of examples, it is not intended to limit the invention. Any changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of this application is subject to the definition of the scope of the patent application attached.

100‧‧‧First dielectric layer

102‧‧‧ Plug

104‧‧‧Second dielectric layer

104a‧‧‧ lower dielectric layer

104b‧‧‧Upper dielectric layer

106‧‧‧ Ditch

108‧‧‧Barrier layer

110‧‧‧metal layer

110a‧‧‧Part 1

110b‧‧‧ part two

110c‧‧‧Part III

Claims (10)

A method for fabricating an interconnect, comprising: providing a substrate on which a first dielectric layer has been formed, and two plugs have been formed in the first dielectric layer; forming a first layer on the first dielectric layer a dielectric layer; a trench exposing the two plugs is formed in the second dielectric layer; and a metal wire is formed on each plug. The method for fabricating an interconnect according to claim 1, wherein the direction in which the trench extends is substantially perpendicular to a direction in which the two plugs are connected. The method for fabricating an interconnect according to claim 1, wherein the method of forming a metal wire on each of the plugs comprises: forming a metal layer conformally on the substrate; and removing the The metal layer on the two dielectric layers and the metal layer between the two plugs. The method of fabricating an interconnect according to claim 1, wherein the method of forming a metal wire on each plug separately comprises: forming a metal layer in the trench, the metal layer comprising a trench formed in the trench a first portion and a second portion on opposite side walls, and a third portion connecting the first portion and the second portion and formed at a bottom of the trench; and removing the third portion. The method of fabricating an interconnect according to claim 4, wherein after removing the third portion, the first portion forms a metal wire electrically connected to one of the two plugs, The second portion forms another metal wire that is electrically connected to the other of the two plugs. The method for fabricating an interconnect as described in claim 4, further comprising: filling the dielectric material between the first portion and the second portion after removing the third portion. The method of fabricating the interconnect according to claim 1, wherein before the forming a metal wire on each plug, the manufacturing method further comprises conformally forming a barrier layer on the substrate. The method for fabricating an interconnect according to claim 7, wherein the manufacturing method further comprises removing the barrier layer on the second dielectric layer and the between the two plugs Barrier layer. The method of fabricating an interconnect according to claim 1, wherein the second dielectric layer is a composite dielectric layer comprising two different dielectric materials. An interconnect structure includes: a first dielectric layer; a second dielectric layer disposed on the first dielectric layer; and a plug disposed in the first dielectric layer and extending to the second dielectric layer An electrical layer; and a wire disposed in the second dielectric layer and located on the plug, wherein the wire has opposite sides and between one side of the wire and the second dielectric layer A barrier layer is disposed with no barrier layer between the other side of the wire and the second dielectric layer.