JP3439447B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having multi-layered wiring, and more particularly to an improvement in a method for forming multi-layered wiring including formation of a plug for electrically connecting a lower layer wiring and an upper layer wiring. Regarding things

[0001]

2. Description of the Related Art In recent years, with the high integration and high performance of semiconductor devices, miniaturization and multi-layering of internal wiring have been advanced. However, miniaturization and multi-layering of wiring cause an increase in inter-wiring capacitance, and an increase in inter-wiring capacitance affects the operating speed of a semiconductor element. Therefore, it is necessary to reduce inter-wiring capacitance. . To reduce the capacitance between wirings, an insulating film material with a low relative dielectric constant may be used. To further reduce the capacitance, a hollow structure wiring in which a gap is provided in the insulating film between wirings You can do this.

An example of a conventional method of forming a hollow structure wiring of this type is disclosed in, for example, Japanese Patent No. 2948588 or Japanese Unexamined Patent Publication No. 2000-58649.

In the process of forming a multilayer wiring having a hollow structure disclosed in these publications, a plug for electrically connecting the upper wiring and the lower wiring is formed before the lower wiring, and the lower layer is formed after the plug is formed. Wiring is formed, and then an upper wiring is formed. As a result, in the step of forming the plug after forming the lower layer wiring having a gap between the adjacent wirings, when misalignment of the plug with respect to the lower layer wiring occurs, the conductive material forming the plug becomes It is possible to avoid the problem of inflow and short circuit between lower layer wirings.

However, the above forming method includes a polishing step of depositing an interlayer insulating film on the formed plug and flattening the interlayer insulating film until the upper surface of the plug is exposed. The polishing device for flattening has no choice but to polish the metal forming the plug. Therefore, the polishing apparatus for planarizing the insulating film may be contaminated with metal, or even if the polishing apparatus is cleaned after polishing, the metal particles generated from the plug may not be completely removed and may remain in the apparatus.

Further, in the step of etching the interlayer insulating film and the conductive film using the plug as a mask, a part of the adhesive layer formed around the plug is removed,
There are problems that the adhesion between the plug and the insulating film is deteriorated, the insulating property of the insulating film is deteriorated due to diffusion of the metal material forming the plug, and the reliability such as electromigration resistance of the wiring is deteriorated.

The process of forming a conventional multi-layer wiring having a hollow structure wiring disclosed in the above publication will be described below with reference to FIG.
Will be explained. FIG. 3 is a cross-sectional view for explaining the above-described conventional hollow structure wiring forming process. First, FIG. 3 (a)
As shown in, the semiconductor substrate 30 made of, for example, silicon
A first insulating film 302 made of a silicon oxide film, a conductor film 303 made of an aluminum alloy, and a second insulating film 304 made of a silicon oxide film are formed on the substrate 1 by CVD (chemical vapor deposition).
r deposition) method or the like. Next, a novolac-based resist film, for example, is applied on the second insulating film 304, and the mask pattern 3 is formed by using photolithography.
Form 05.

Next, as shown in FIG. 3B, the second insulating film 304 is dry-etched using a mask pattern 305 to form a connection hole 306 at a position where a plug is to be formed.

Next, as shown in FIG. 3C, an adhesion film made of, for example, titanium nitride is deposited on the entire surface of the second insulating film 304 by a sputtering method or the like, and then an evaporation method is performed. Etc., a conductor film made of, for example, tungsten is deposited, and the contact film and the conductor film are filled in the connection hole 306 in the second insulating film 304. Then, the adhesion film and the conductive film other than the inside of the connection hole 306 are CMP-treated.
The plug 307 is formed inside the connection hole 306 by polishing and removing by a (Chemical Mechanical Polishing) method. This plug 307 has an adhesion layer 307a on the side wall and bottom surface of the connection hole 306.

Next, as shown in FIG. 3D, the second insulating film 304 is partially etched back. As a result, the upper portion of the plug 307 is exposed, and it is possible to control the apex position of the void between the wirings to be formed later.

Next, as shown in FIG. 3E, a novolac-based resist, for example, is applied on the entire surface of the second insulating film 304 and patterned to form a first wiring pattern resist pattern 308. Form. The resist pattern 308 is formed according to the shape of the wiring pattern, but the resist pattern 3 that completely covers the plug 307 is formed.
08a is also formed.

Next, as shown in FIG. 3F, the second insulating film 304, the conductive film 303, and the first insulating film 302 are sequentially dry-etched using the resist patterns 308 and 308a as masks to form a lower layer. The wiring 303a is formed. At this time, the portion of the first insulating film 302 between the wirings is dug down by etching. This is because by forming the voids between the wirings with a high aspect ratio, it becomes easy to form the voids between the wirings in a later step, and the vertical position of the void portion is controlled.

Next, as shown in FIG. 3G, after removing the resist pattern 308, for example, silane gas,
A third insulating film 309 made of silicon oxide is deposited over the entire surface of the semiconductor substrate 301 by a plasma CVD method using a gas containing a dinitrogen monoxide (N ₂ O) gas. Since the third insulating film has a low coverage and a high directivity,
It is a film that does not easily adhere to the side wall. Then, a fourth insulating film 310 such as a silicon oxide film having a high filling property is formed by a high density plasma CVD method. As a result, the first wiring 3
A void 311 is formed between 03a. The formation of the gap 311 by forming the third insulating film 309 is limited to the case where the distance between the wirings is narrow, and the case where the distance between the wirings is wide only narrows the opening portion. By forming the fourth insulating film 310, the remaining portions also have their openings closed and voids are formed.

Next, as shown in FIG. 3 (h), the plug 3
The fourth insulating film 310 and the third insulating film 309 are polished by CMP until the upper surface of 07 is exposed. This CM
The P method is not the metal CMP method used in FIG. 3C but a CMP method for an insulating film.

Next, as shown in FIG. 3 (i), the plug 3
By forming the upper layer wiring 312 so as to be connected to 07, a two-layer wiring structure is formed. This two-layer wiring is
Since holes are formed in the insulating layer between the wirings in the second layer and the relative permittivity of the air contained in the holes is about 1/4, the capacitance between the adjacent wirings can be reduced and the relative permittivity can be reduced. It is possible to obtain a highly reliable semiconductor device at a lower cost than using a novel insulating film material having a small size (such as fluorine-doped SiOF).

[0015]

However, according to the conventional method of manufacturing a semiconductor device, as shown in FIG. 3H, the third insulating film 3 deposited on the formed plug 307 is used.
In the step of planarizing and polishing the 09 and the fourth insulating film 310 using the insulating film CMP method until the upper surface of the plug 307 is exposed, the plug 307 and the adhesion layer 307a are also polished to some extent. This causes the above-mentioned problem, that is, the polishing pad of the CMP apparatus, which originally has a polishing specification of only the insulating film, is contaminated by the metal forming the plug 307 and the adhesion layer 307a, or is cleaned after polishing. This also causes a problem that the metal particles generated from the plug 307 and the adhesion layer 307a cannot be completely removed and remain on the polishing pad.

The metal contamination of this CMP apparatus is difficult to remove, and the metal particles remaining on the polishing pad cause
The semiconductor device may be damaged during polishing, causing an increase in electric resistance of the wiring, disconnection, or the like.

Further, as shown in FIG. 3D, in the step of etching the second insulating film 304, the plug 3
07 and a part of the adhesion layer (barrier metal) 307a formed around the plug 307 are removed, the adhesion between the plug 307 and the third insulating film 309 is deteriorated, or the plug 307 is removed. There are problems that the insulation property of the insulating film is deteriorated due to the diffusion of the metal material constituting the wiring, and the reliability such as electromigration resistance of the wiring is deteriorated.

The present invention solves the above-mentioned conventional problems and can form the plug without exposing the plug and the adhesion layer in the polishing process of the upper surface of the insulating film, thereby preventing metal contamination and generation of metal particles in the insulating film polishing process. In addition, the adhesion layer and the plug are not etched by the insulating film etching process, the adhesion between the insulating film and the plug is deteriorated, the metal material forming the plug is diffused into the insulating film, and the reliability of the wiring is improved. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can prevent deterioration of the characteristics.

[0019]

In order to achieve the above object, in a method of manufacturing a semiconductor device according to the invention of claim 1 of the present application, a first wiring pattern forming layer made of a conductive film is formed.
And a first insulating layer on the first wiring pattern forming layer.
The first step of forming a film and the selection for the first insulating film
Selective etching is performed to form an opening, and the opening is
First wiring pattern formation by forming a conductive film
A second plug forming a first plug electrically connected to the layer
And a step of forming the first insulating film including on the first plug.
A mask pattern for forming a first wiring pattern on the upper surface
The third step of forming a mask and the mask pattern.
As the mask, the first insulating film and the first wiring pattern
The first wiring pattern is formed by etching the film forming layer.
A fourth step of forming a plug, the first plug and the front
While covering the first wiring pattern, the first wiring pattern
Forming a second insulating film to leave a gap between turns
And the upper surface of the second insulating film,
The flattening so that the upper surface of the first plug is not exposed
Step and selectively etch the second insulating film
To form an opening and at least a bottom surface of the opening.
Exposing a part of the upper surface of the first plug,
By forming a conductive film on the first plug,
Seventh step of forming a second plug that is electrically connected
And a second plug to be electrically connected to the second plug.
And an eighth step of forming the wiring pattern .

As a result, the plug and the adhesion layer are not exposed in the flattening polishing step of the insulating film, so that metal particles are generated in the insulating film polishing step.
Generation of metal contamination is prevented. Further, since the step of etching the insulating film is not required, the etching of the plug and the adhesion film is prevented, and the deterioration of the adhesion between the insulation film and the plug, the diffusion of the plug constituent material into the insulation film, and the deterioration of the reliability of the wiring are prevented. It

The method of manufacturing a semiconductor device according to the invention of claim 2 of the present application is the method of manufacturing a semiconductor device according to claim 1.
In the method, in the sixth step, the second isolation
The top surface of the first plug is not exposed to the top surface of the edge film.
Instead of planarizing as described above, a third layer is formed on the second insulating film.
An insulating film is formed on the upper surface of the third insulating film.
By flattening the top surface of the
If the voids are not exposed in the flattening process,
In both cases, the upper surface of the third insulating film is covered with the second insulating film.
The top surface should be flatter than that when flattened.
It is obtained as that.

As a result, the margin in the flattening process
Is ensured and the exposure of voids becomes more difficult to occur.
In addition, the step of the second insulating film has been eliminated beforehand.
Therefore, the upper surface of the second insulating film alone must be flattened and polished.
The flatness of the surface is excellent .

A method of manufacturing a semiconductor device according to a third aspect of the present invention is the method of manufacturing a semiconductor device according to the first aspect.
A method for forming the first wiring pattern
Of the first plug when forming the mask pattern of
The mask pattern of the portion formed on the upper portion is set to the first
By making it wider than the plug,
Etching step for the first wiring pattern forming layer
The side surface of the first plug is the first insulating film.
The first plug so that it is covered by a part of
The side surface of is not etched .

This etches the first wiring pattern.
Side surface or plug of the first plug when forming by plugging.
Since a part of the first insulating film remains on the side surface of the
During the etching process, the side surface of the first plug or the plug
The sides of the lug are protected and the first plug or plug is
Essentially, it is prevented from being etched .

A method of manufacturing a semiconductor device according to a fourth aspect of the present invention is the method of manufacturing a semiconductor device according to the first aspect , wherein the planarization of the second insulating film is performed by a chemical mechanical method.
This is performed by a polishing method .

As a result, it is flattened by the chemical mechanical polishing method.
Insulation film polishing specification is
Metal contamination of chemical mechanical polishing equipment, which is difficult to remove
A semiconductor device manufacturing method effective for prevention is realized.
It

The method of manufacturing a semiconductor device according to a fifth aspect of the present invention is the method of manufacturing a semiconductor device according to the second aspect , wherein the planarization of the third insulating film is performed by a chemical machine.
This is performed by a polishing method .

Thereby, flattening is performed by the chemical mechanical polishing method.
Insulation film polishing specification is
Metal contamination of chemical mechanical polishing equipment, which is difficult to remove
A semiconductor device manufacturing method effective for prevention is realized .

[0029]

[0030]

[0031]

[0032]

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION (Embodiment 1) In Embodiment 1, a plug for electrically connecting a lower layer wiring and an upper layer wiring is formed twice so that an insulating film specification is obtained. When the polishing is performed by the CMP apparatus, the only object to be polished is the insulating film, and metal contamination is prevented from occurring. Embodiment 1 of the present invention will be described below with reference to the drawings. 1A to 1D are process sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. First, Fig. 1
As shown in (a), a first insulating film 10 made of silicon oxide is formed on a semiconductor substrate 101 made of silicon, for example.
2 and an aluminum alloy conductor film (wiring pattern forming layer in the claims) 103 and a second insulating film (first insulating film in the claims) 104 made of a silicon oxide film are sequentially deposited. The materials for the first insulating film 102, the conductor film 103, and the second insulating film 104 are merely examples.

Next, a novolac-based resist film is applied on the second insulating film 104, and a mask pattern (not shown) is formed by photolithography. Then, using the mask pattern, the second insulating film 104 is etched with a fluorocarbon gas such as CF ₄ , CHF ₃ or the like, and the first connection hole 10 is formed at a position where a plug is to be formed.
5 is formed. The radius is about 0.1 to 0.4 μm.

Here, the film thickness of the second insulating film 104 is related to the position of the apex of the void 110 formed later from the upper surface of the first wiring 103a. If it is too thick, the apex position of the void 110 is the first wiring 1
There is a risk that the upper part of the void 110 may be exposed in the subsequent insulating film flattening polishing step, which is considerably above the upper surface of 03a. Therefore, the film thickness of the second insulating film 104 is an appropriate thickness such that the apex position of the void 110 is not much above the upper surface of the first wiring 103a, for example, 3
The thickness is set to about 00 to 600 nm. This thickness corresponds to the thickness in which the plug in FIG. 3D is embedded in the insulating film 304. The film thicknesses of the first insulating film 102 and the conductor film 103 are, for example, 1000 nm and 60 nm, respectively.
It is about 0 nm.

As described above, the second insulating film 104 that affects the position of the top of the void 110 between the wirings from the wiring upper surface.
The film thickness of the second insulating film 304 may be the same as the film thickness when the second insulating film 104 is deposited.
It is not necessary to etch back to adjust the film thickness (Fig. 3
(See (d)). Therefore, the adhesion layer around the plug is not etched by the insulating film etch-back process, the adhesion between the insulating film and the plug is deteriorated, the plug constituent material is diffused into the insulating film, and the reliability of the wiring is reduced. There is no problem such as doing.

Next, as shown in FIG. 1B, an adhesion film made of, for example, titanium nitride is formed on the upper surface of the second insulating film 104 including the first connection hole 105 by a sputtering method or the like to a thickness of 50 n.
It is deposited with a thickness of about m, and then using a vapor deposition method or the like,
For example, a conductor film made of tungsten is deposited to a thickness of about 100 nm, the adhesion film and the conductor film are filled in the first connection hole 105 in the second insulating film 104, and the inside of the first connection hole 105 is filled. Other than the adhesion film and the conductive film other than metal C
By polishing and removing by the MP method (stopping CMP on the surface of the insulating film 104 by time control),
A first plug 106 made of tungsten is formed in the first connection hole 105. This plug 106 has an adhesion layer 106a made of titanium nitride on its side wall and bottom surface.

Next, as shown in FIG. 1C, a resist pattern 107 for forming a first wiring pattern is formed on the upper surface of the second insulating film 104 in conformity with the shape of the wiring pattern. At that time, the resist pattern 107 is formed also on the upper part of the first plug 106 and the adhesion layer 106a. This pattern has a larger area including a region where the upper surface of the first plug 106 and the upper surface of the adhesion layer 106a are combined. Keep it as a pattern. As a result, in the next dry etching step, the insulating film is present and protected on the side surfaces of the first plug 106 and the adhesion layer 106a, so that the first plug 106 and the adhesion layer 106a are unnecessarily etched. There is no.

Next, as shown in FIG. 1D, the first wiring pattern resist pattern 107 is used as a mask.
The second insulating film 104, the conductive film 103, and the first insulating film 10
2 are sequentially dry-etched to form the first wiring pattern 1
03a is formed. At this time, the inter-wiring portion of the first insulating film 102 is dug down to, for example, about 300 nm by dry etching using a fluorocarbon gas such as CF ₄ or CHF ₃ . As a result, for example, a wiring having a width of 0.5 μm or less has a high aspect ratio (an aspect ratio of 3 or more), and in the subsequent insulating film forming step, the formation position of the void in the up-and-down direction is not biased upward between the wiring and between the wiring. It can be controlled so as to come to the central portion, and the gap can be formed so as to be the largest between the wirings.

Next, as shown in FIG. 1E, after removing the first wiring pattern resist pattern 107,
For example, the third insulating film 1 made of silicon oxide is formed over the entire surface of the semiconductor substrate 101 by a plasma CVD method using a gas containing a silane gas and a dinitrogen monoxide gas.
08 is deposited on the order of 200 to 500 nm, for example. The third insulating film has a low coverage and a high directivity. Next, the fourth insulating film 109 made of, for example, a silicon oxide film is formed by, for example, a high density plasma CVD method to have a thickness of 300 to 1000 nm.
To have a film thickness of By forming these third and fourth insulating films 108 and 109, a void 110 is formed between the first wiring patterns 103a.

Furthermore, for example, TEOS (tetraethyl orthos) is formed on the fourth insulating film 109 by a plasma CVD method.
The fifth insulating film 111 made of an ilicate) film is formed of, for example, 100
It is formed to have a film thickness of 0 to 2000 nm.

The formation of the fifth insulating film 111 is not essential, but in the case where the fifth insulating film 111 is formed, the thickness of the insulating film above the void 110 should be made thicker than in the case where it is not formed. You can By increasing the thickness of the insulating film on the upper side of the void 110, there is an advantage that the process margin in the step of polishing the upper insulating film of the void 110 can be increased so that the upper portion of the void 110 is not exposed.

When the fifth insulating film 111 is formed, the fifth insulating film 1 is formed when the fifth insulating film 111 is formed.
11 Since the step difference (for example, 0.2 μm or less) on the upper surface can be made smaller than the step difference (for example, about 0.5 μm) on the upper surface of the fourth insulating film 109 when the fourth insulating film 109 is formed,
The fifth insulating film 111 is formed so that the upper portion of the void 110 is not exposed.
Polishing the upper surface also has the advantage that it is possible to easily obtain the upper surface of the insulating film, which is superior in flatness, as compared with the case where the upper surface of the fourth insulating film 109 is polished.

Next, as shown in FIG. 1F, the upper surface of the fifth insulating film 111 is polished and planarized by the CMP method. At this time, the polishing time is controlled so that the upper surfaces of the first plug 106 and the adhesion layer 106a are not exposed. Therefore, the first plug 106 and the adhesion layer 106a are not polished and metal particles are not generated, so that metal contamination in the insulating film flattening polishing step can be prevented.

Next, as shown in FIG. 1G, a sixth insulating film 112 made of silicon oxide is deposited on the entire surface of the semiconductor substrate 101. Next, the sixth insulating film 11
A resist film is applied on the surface 2 and a mask pattern 112 is formed by photolithography so that the pattern matches the position of the first plug 106.

Next, as shown in FIG. 1H, for example, CF ₄ and C are applied to the fifth insulating film 111, the fourth insulating film 109 and the third insulating film 108 by using a mask pattern 112.
The second connection hole 113 is formed by dry etching with a fluorocarbon gas such as HF ₃ . At this time, at least the first plug 10 is provided on the bottom surface of the second connection hole 113.
6. Second connection hole 113 is formed so that a part of the upper surface is exposed.

Next, as shown in FIG. 1I, an adhesion film made of titanium nitride is deposited on the upper surface of the fifth insulating film 111 including the second connection hole 113 by using a sputtering method or the like. A conductive film made of tungsten is deposited by using a vapor deposition method or the like to fill the contact film and the conductor film in the second connection hole 113, and the contact film other than the inside of the second connection hole 113 and the contact film. The second plug 1 made of tungsten is obtained by polishing and removing the conductive film by the metal CMP method.
An adhesion layer 114a composed of titanium nitride and titanium nitride is formed.
At this time, the upper surface of the first plug 106 and the adhesion layer 114a
Bottoms of are in contact. Therefore, the second plug 11
4 is electrically connected to the first plug 106 via the adhesion layer 114a.

Next, as shown in FIG. 1J, a second wiring pattern 115 is formed on the fifth insulating film 111 so as to be electrically connected to the second plug 114.

As described above, according to the first embodiment, the multilayer wiring for electrically connecting the lower layer wiring and the upper layer wiring by the plug is provided, and the space between the wirings of the lower layer wiring is formed to reduce the inter-wiring capacitance. The fourth insulating film 109 and the third insulating film 108 that cover the space above when manufacturing the semiconductor device aiming at
In the planarization polishing process for the first plug 106
Since the contact layer 106a and the adhesion layer 106a are not exposed, the first plug 106 and the adhesion layer 106a are not polished and metal particles are not generated. Therefore, it is possible to prevent metal contamination in the insulating film flattening / polishing step. it can.

Further, the film thickness of the second insulating film 104, which influences the position of the apex of the void 110 between the wires from the upper surface of the wire, may be the same as the film thickness when the second insulating film 104 was deposited. Unlike the conventional method, it is not necessary to etch back the second insulating film 104 to adjust the film thickness. Therefore,
The insulating film etch-back process does not etch the plug or the adhesion layer around the plug, which deteriorates the adhesion between the insulation film and the plug, diffuses the constituent material of the plug into the insulation film, and improves the reliability of the wiring. Does not occur.

In the first embodiment, the two-layer wiring structure is shown, but by repeating this process, it can be applied to the formation of multilayer wiring having three or more layers.

(Embodiment 2) In Embodiment 2, the plug forming process is performed only once, and the upper layer wiring is a buried wiring, so that the total number of steps can be reduced.

The second embodiment of the present invention will be described below with reference to the drawings. 2A to 2E are process cross-sectional views showing the method of manufacturing a semiconductor device according to the second embodiment. First, FIG.
As shown in (a), a first insulating film 20 made of silicon oxide is formed on a semiconductor substrate 201 made of silicon, for example.
2 and an aluminum alloy conductor film (wiring pattern forming layer in the claims) 203 and a second insulating film (first insulating film in the claims) 204 made of a silicon oxide film are sequentially deposited. The materials for the first insulating film 202, the conductor film 203, and the second insulating film 204 are merely examples.

Next, a novolac-based resist film is applied on the second insulating film 204, and a mask pattern (not shown) is formed by photolithography. Then, the second insulating film 204 is etched using the mask pattern to form a connection hole 205 at a position where a plug is to be formed.

Here, the film thickness of the second insulating film 204 is related to the position of the apex of the void 210 formed later from the upper surface of the first wiring 203a. If it is too thick, the apex position of the void 210 is the first wiring 2
There is a possibility that the upper part of the void 210 may be exposed in the subsequent insulating film flattening polishing step because it is considerably above the upper surface of 03a. Therefore, the film thickness of the second insulating film 204 is appropriate, for example, 3 so that the apex position of the void 210 is not much above the upper surface of the first wiring 203a.
The thickness is set to about 00 to 600 nm. This thickness corresponds to the thickness in which the plug in FIG. 3D is embedded in the insulating film 304.

As described above, the second insulating film 204 that affects the position of the apex of the void 210 between the wirings from the wiring upper surface.
The film thickness of the second insulating film 304 may be the same as the film thickness when the second insulating film 204 is deposited.
It is not necessary to etch back to adjust the film thickness (Fig. 3
(See (d)). Therefore, the plug and the adhesion layer (barrier metal) around the plug are etched by the insulating film etch back process.
Is not etched, and there is no problem that the adhesion between the insulating film and the plug is deteriorated, the plug constituent material is diffused into the insulating film, or the reliability of the wiring is deteriorated.

Next, as shown in FIG. 2B, the second insulating film 204 including the connection hole 205 is formed by using the sputtering method or the like.
An adhesion film 206a made of, for example, titanium nitride is deposited on the upper surface, and then a conductor film 206 made of, for example, tungsten is deposited by using a vapor deposition method or the like so that the adhesion film and the conductor film are formed in the second insulating film 204. Then, the plug 206 made of tungsten is formed in the connection hole 205 by filling the connection hole 205 and removing the adhesive film and the conductive film other than the inside of the connection hole 205 by the metal CMP method. This plug 206 has an adhesion layer 206a made of titanium nitride on its side wall and bottom surface. In the second embodiment, since the plug forming step only needs to be performed once, the step can be simplified as compared with the first embodiment.

Next, as shown in FIG. 2C, the plug 2
A resist pattern 207 for forming a first wiring pattern is formed on the upper surface of the second insulating film 204 including 06 and the adhesion layer 206a in accordance with the shape of the wiring pattern. At this time, the resist pattern 207 is also formed on the plug 206 and the upper portion of the adhesion layer 206a, and this pattern has a larger area including a region in which the upper surface of the plug 206 and the upper surface of the adhesion layer 206a are combined. As a result, in the next dry etching process, the plug 206 and the adhesion layer 20 are
Since the insulating film exists and is protected on the side surface of 6a, the plug 206 and the adhesion layer 206a are not unnecessarily etched.

Next, as shown in FIG. 2D, the second insulating film 204, the conductive film 203, and the first insulating film 202 are sequentially dried using the first wiring pattern forming resist pattern 207 as a mask. Etching is performed to form the first wiring pattern 203a. At this time, the first insulating film 202
The portion between the wirings is dug down by dry etching. With this, it is possible to control the distance between the wirings to have a high aspect ratio, and the formation position of the void in the up-and-down direction in the subsequent insulating film forming process so as to come to the central portion between the wirings without being biased upward from between the wirings. It can be formed so that the space between wirings is the largest.

Next, as shown in FIG. 2E, after removing the first wiring pattern resist pattern 207,
For example, the third insulating film 2 made of silicon oxide is formed over the entire surface of the semiconductor substrate 201 by a plasma CVD method using a gas containing a silane gas and a dinitrogen monoxide gas.
08 is deposited. The third insulating film has a low coverage and a high directivity.

Next, a fourth insulating film 209 made of a silicon oxide film is formed by the high density plasma CVD method. As a result, the gap 21 is formed between the first wiring patterns 203a.
0 is formed. The steps up to this point are the same as in the first embodiment. However, the third insulating film 208 and the fourth insulating film 209 deposited on the plug 206 are necessary to form a buried wiring groove for forming a buried wiring after the flattening polishing of the upper surface thereof. The total film thickness is determined so that the film thickness remains. This total film thickness is, for example, 2.0 to 3.
It is about 0 μm.

Next, as shown in FIG. 2F, the insulating film C
At least the fourth insulating film 209 is polished and planarized by using the MP method. At this time, the fourth insulating film 209 has a sufficient thickness, and the upper surfaces of the plug 206 and the adhesion layer 206a are not exposed. Therefore, the plug 206 and the adhesion layer 206
Since a is not polished and metal particles are not generated, it is possible to prevent metal contamination in the insulating film flattening / polishing step.

Next, as shown in FIG. 2G, a resist film is applied on the polished fourth insulating film 209, and a mask pattern 212 is formed by photolithography.

Next, as shown in FIG. 2H, dry etching is performed on the fourth insulating film 209 and the third insulating film 208 using the mask pattern 212 to form the buried wiring forming groove 213. Form. At this time, for example, time control is performed so that at least a part of the upper surface of the plug 206 is exposed at the bottom surface of the embedded wiring forming groove 213.

Next, as shown in FIG. 2I, a fourth method including a buried wiring forming groove 213 is formed by a sputtering method or the like.
Of the tantalum nitride on the upper surface of the insulating film 209 of
4a is deposited, and then a conductor film 214 made of, for example, copper is deposited by using a plating method to fill the adhesion film 214a and the conductor film 214 in the embedded wiring forming groove 213.

Next, as shown in FIG. 2J, the conductive film 214 and the adhesion film 2 other than the inside of the embedded wiring forming groove 213 are formed.
By polishing and removing 14a by a metal CMP method, a second wiring pattern 215 which is an embedded wiring made of copper and an adhesion layer 215a made of tantalum nitride are formed. At this time, the second wiring pattern 215 and the plug 2
06 is electrically connected via the adhesion film 215a.

As described above, according to the second embodiment, the multilayer wiring for electrically connecting the lower layer wiring and the upper layer wiring with the plug is provided, and the space between the wirings of the lower layer wiring is formed to reduce the capacitance between wirings. When manufacturing a semiconductor device with reduced size, the plug 206 and the adhesion layer 206a are not exposed in the flattening polishing step for the fourth insulating film 209 that covers the upper portion of the void, so that the plug 206 and the adhesion layer 206a are not exposed. Is not polished and metal particles are not generated, so that metal contamination in the step of flattening and polishing the insulating film can be prevented.

Further, the film thickness of the second insulating film 204, which influences the position of the apex of the void 210 between the wires from the upper surface of the wire, may be the same as the film thickness when the second insulating film 204 was deposited. Unlike the conventional method, it is not necessary to etch back the second insulating film 204 to adjust the film thickness. Therefore,
The plug and the adhesion layer around the plug are not etched by the insulating film etch back process, the adhesion between the insulating film and the plug is deteriorated, the plug constituent material is diffused into the insulating film, and the reliability of the wiring is reduced. There is no problem such as doing. Furthermore, since the plug forming process is required only once, the process can be simplified as compared with the first embodiment.

Although the two-layer wiring structure is shown in the second embodiment, it is shown in FIG. 2 (b) on the insulating film 209 and the second wiring pattern 215 in the state of FIG. 2 (j). By forming such a plug and then repeating the process of FIG. 2A and subsequent steps, it can be similarly applied to the formation of a multilayer wiring having three or more layers.

[0070]

As described above, according to the method for manufacturing a semiconductor device of the invention of claim 1 of the present application, it is possible to remove the conductive film from the conductive film.
And forming a first wiring pattern forming layer
Forming a first insulating film on the first wiring pattern forming layer;
1 and selectively etch the first insulating film
Forming an opening and forming a conductive film in the opening.
To electrically connect with the first wiring pattern forming layer.
A second step of forming a first plug to be continued,
No. 1 plug on the upper surface of the first insulating film including the first plug.
Forming a mask pattern for forming a line pattern
The third step, using the mask pattern as a mask,
For the first insulating film and the first wiring pattern forming layer
Etching to form a first wiring pattern
4 step, the first plug and the first wiring pattern
While covering the turn, between the first wiring patterns
Fifth step of forming second insulating film so as to leave voids in
And the upper surface of the second insulating film on the first plug.
A sixth step of flattening the surface so that it is not exposed;
2 Insulating film is selectively etched to open
And forming at least the first plastic on the bottom surface of the opening.
Part of the top surface of the plug is exposed and a conductive film is formed in the opening.
Is electrically connected to the first plug by
A second step of forming a second plug, and the second plug
The second wiring pattern so that it is electrically connected to the lug
Since the eighth step of forming is included, in the step of forming a multi-layered wiring in which a gap is provided between the wirings, the plug and the adhesion layer should not be exposed during the step of flattening and polishing the upper surface of the insulating film. As a result, since the plug and the adhesion layer are not polished and metal particles are not generated, it is possible to prevent metal contamination in the flattening polishing process of the insulating film, and
Since the insulating film etch-back step for adjusting the position of the apex of the void formed between the wirings from the upper surface of the wiring is not necessary, the adhesion layer around the plug cannot be etched by this step. There is an effect that a method of manufacturing a semiconductor device can be obtained, which can prevent problems such as deterioration of adhesion, diffusion of plug constituent material into an insulating film, and deterioration of reliability of wiring.

According to the method of manufacturing a semiconductor device according to the invention of claim 2 of the present application, the semiconductor device according to claim 1
In the sixth step,
The upper surface of the first plug is exposed on the upper surface of the second insulating film.
Instead of flattening so that there is no
Forming a third insulating film on the upper surface of the third insulating film,
By flattening the top surface of the plug so that it is not exposed
To prevent the voids from being exposed during the flattening process.
And the upper surface of the third insulating film is covered with the second insulating film.
The flatness is superior to that when the top surface of the insulating film is flattened.
Since it is made to be a surface, the effect of the invention of claim 1 is added.
However, a margin is secured in the flattening process and the void is exposed.
Is less likely to occur, and the step of the second insulating film is
Has been eliminated in advance, the second insulating film alone
A top surface with better flatness than that obtained by flattening and polishing the top surface was obtained.
The method of manufacturing a semiconductor device has an effect obtained that.

According to the method of manufacturing a semiconductor device according to the invention of claim 3 of the present application, the semiconductor device according to claim 1
Forming the first wiring pattern,
When forming a mask pattern for
The mask pattern of the part formed on the top of the lug is
By making it wider than the first plug,
Etching for the edge film and the first wiring pattern forming layer
In the plugging step, the side surface of the first plug is
The first insulating film is covered with a part of the insulating film.
Since the sides of the plug are not etched,
In addition to the effect of the invention of claim 1, the first wiring pattern is etched.
The first plug is formed on the side surface of the first plug when forming by plugging.
Since a part of the insulating film remains, it can be used in the next dry etching process.
The side surface of the first plug is protected,
There is an effect that a method of manufacturing a semiconductor device can be obtained that can prevent unnecessary etching .

According to the method of manufacturing a semiconductor device according to the invention of claim 4 of the present application, in the method of manufacturing a semiconductor device according to claim 1 , the planarization of the second insulating film is performed.
Since the mechanical polishing method is used,
In addition to the effect of light, planarization was performed by the chemical mechanical polishing method.
In this case, the insulation film is polished and the metal particles
Prevents metal contamination of chemical mechanical polishing equipment, which is difficult to remove
In addition, there is an effect that a semiconductor device manufacturing method that is effective above can be realized .

According to the method of manufacturing a semiconductor device according to the invention of claim 5 of the present application, in the method of manufacturing a semiconductor device according to claim 2, the planarization of the third insulating film is performed.
Since the mechanical polishing method is used,
In addition to the effect of light, planarization was performed by the chemical mechanical polishing method.
In this case, the insulation film is polished and the metal particles
Prevents metal contamination of chemical mechanical polishing equipment, which is difficult to remove
In addition, there is an effect that a semiconductor device manufacturing method that is effective above can be realized .

[0075]

[0076]

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

3A to 3D are process cross-sectional views showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

101 semiconductor substrate 102 first insulating film 103 conductive film 103a First wiring pattern 104 second insulating film 105 First connection hole 106 First plug 106a adhesion layer 107 first wiring pattern resist pattern 108 Third insulating film 109 fourth insulating film 110 void 111 fifth insulating film 112 Second Connection Hole Forming Resist Pattern 113 Second connection hole 114 Second plug 114a adhesion layer 115 Second wiring pattern 201 semiconductor substrate 202 first insulating film 203 conductive film 203a First wiring pattern 204 second insulating film 205 connection hole 206 plug 206a Adhesion layer 207 First resist pattern for wiring pattern 208 Third insulating film 209 Fourth insulating film 210 void 212 Resist Pattern for Forming Groove for Embedded Wiring 213 Embedded wiring groove 214 conductive film 214a Adhesive film 215 Second wiring pattern 215a Adhesion layer 301 Semiconductor substrate 302 First insulating film 303 conductive film 303a First wiring pattern 304 Second insulating film 305 Resist pattern for connection hole formation 306 connection hole 307 plug 307a Adhesion layer 308 First wiring pattern forming resist pattern 309 Third insulating film 310 Fourth insulating film 311 void 312 Second wiring pattern

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP 2000-58649 (JP, A) JP 11-204635 (JP, A) JP 64-11346 (JP, A) JP 64-45141 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (5)

(57) [Claims] 1. Forming a first wiring pattern made of a conductive film
Forming a layer on the first wiring pattern forming layer
A first step of forming a first insulating film, and an opening by selectively etching the first insulating film.
By forming a mouth portion and forming a conductive film in the opening portion,
Is electrically connected to the first wiring pattern forming layer.
A second step of forming a first plug, and a first step on the upper surface of the first insulating film including on the first plug.
Shape the mask pattern to form the wiring pattern 1
And a third step of forming the first insulating film using the mask pattern as a mask.
And etching the first wiring pattern forming layer
And a fourth step of forming a first wiring pattern and covering the first plug and the first wiring pattern.
At the same time, a gap is left between the first wiring patterns.
Thus, the fifth step of forming the second insulating film and the upper surface of the second insulating film
A sixth step of flattening so as not to expose it and an opening by selectively etching the second insulating film.
Forming a mouth portion and at least the first portion on the bottom surface of the opening portion;
Part of the upper surface of the plug is exposed, and a conductive film is formed in the opening.
To form an electrical contact with the first plug.
A seventh step of forming a second plug to be continued, and a second step for electrically connecting to the second plug.
An eighth step of forming a line pattern, and a method of manufacturing a semiconductor device. 2. A method of manufacturing a semiconductor device according to claim 1.
In the sixth step, the upper surface of the second insulating film is
Flatten the top surface of the first plug so that it is not exposed
Instead of the above, a third insulating film is formed on the second insulating film, and the third insulating film is formed.
Make sure that the upper surface of the insulating film is not exposed on the upper surface of the plug.
By planarizing, the voids in the planarizing step
Is not exposed and the third insulating film
Compared to the case where the upper surface of the second insulating film is flattened,
A method of manufacturing a semiconductor device, which also has an upper surface excellent in flatness . 3. A method of manufacturing a semiconductor device according to claim 1.
In, a mask pattern for forming the first wiring pattern
Formed on top of the first plug when forming a plug
Make the mask pattern of the wider part wider than the first plug.
The first insulating film and the first wiring
In the etching process for the pattern forming layer,
The side surface of the first plug is formed by a part of the first insulating film.
The side surface of the first plug is etched so that it is covered.
A method of manufacturing a semiconductor device, which is characterized in that it is prevented from being damaged . 4. The method of manufacturing a semiconductor device according to claim 1 , wherein the planarizing of the second insulating film is performed by a chemical mechanical polishing method.
A method of manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 2 , wherein the planarizing of the third insulating film is performed by a chemical mechanical polishing method.
A method of manufacturing a semiconductor device, comprising: