JP3442064B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multi-layer wiring and a method of manufacturing the same, and more particularly, to a structure of a plug for connecting a lower layer wiring having an air gap in an inter-wiring space to an upper layer wiring and a method of forming the same. Regarding

[0002]

2. Description of the Related Art In recent years, with higher integration and higher performance of semiconductor devices, miniaturization and multi-layering of wiring inside semiconductor devices have been advanced. On the other hand, miniaturization and multi-layering of wirings increase the capacitance between wirings, which adversely affects the operating speed of semiconductor devices. Therefore, there is a demand for a method of miniaturizing or multilayering the wiring while reducing the capacitance between the wirings.

In order to reduce the inter-wiring capacitance, an insulating material having a small relative dielectric constant may be used as the inter-layer insulating film, but in order to further reduce the inter-wiring capacitance, an inter-wiring space (adjacent An air gap may be formed in the area between the pair of wirings.

Below, a paper by T. Ueda et al. ((1) A Novel Air
Gap Integration Scheme for Multi-level Interconnec
ts using Self-aligned Via Plugs: 1998 Symposium on
VLSI Technology Digest of Technical Papers, P.46, 1
998., (2) Integration of 3Level Air Gap Interconnec
t for Sub-quater Micron CMOS: 1999 Symposium on VLSI
Technology Digest of Technical Papers, P.111, 199
A conventional method for manufacturing a semiconductor device, specifically, a method for forming a multi-layer wiring having an air gap will be described with reference to the drawings.

8 (a) to 8 (c) and 9 (a) to 9 (c)
10A to 10C are cross-sectional views showing the steps of a conventional method for manufacturing a semiconductor device.

First, as shown in FIG. 8A, a base insulating film 11 made of silicon oxide and a film thickness 600n made of an aluminum alloy are formed on a semiconductor substrate 10 made of silicon.
m first conductive film 12 and a 1500 nm-thick first interlayer insulating film 13 made of silicon oxide are sequentially deposited.
After that, a mask pattern 14 having an opening in the plug formation region is formed on the first interlayer insulating film 13.

Then, the first interlayer insulating film 13 is etched by using the mask pattern 14 to form the structure shown in FIG.
As shown in (b), the aperture 4 reaching the first conductive film 12
After forming the connection hole 15 of about 00 nm, the mask pattern 14 is removed.

Next, by using a vapor deposition method or the like, the second conductive film made of tungsten is entirely filled on the first interlayer insulating film 13 including the connection hole 15 so that the connection hole 15 is completely filled. 8A and 8B, the second conductive film on the outside of the contact hole 15 is polished and removed by the CMP method.
As shown in (c), the plug 16 connected to the first conductive film 12 is formed.

Next, as shown in FIG. 9A, the first interlayer insulating film 13 is etched back so that the film thickness is about 300 to 600 nm, and the upper portion of the plug 16 is covered with the first film. Is projected from the upper surface of the interlayer insulating film 13. As a result, the air gap 20 (FIG.
The position of the top of (see (a)) can be controlled.

Next, as shown in FIG. 9B, a resist pattern 17 is formed on the first interlayer insulating film 13 to cover the lower layer wiring forming region.

Next, as shown in FIG. 9C, the first interlayer insulating film 13 and the first conductive film 12 are sequentially etched by using the resist pattern 17 and the plug 16 as a mask to form a first film. Of the conductive film 12 of
A lower layer wiring 12A connected to is formed.

Further, in the step shown in FIG. 9C, after forming the lower layer wiring 12A, the resist pattern 17 and the plug 1 are formed.
6 is used as a mask to etch the underlying insulating film 11 to form the lower wiring 1 on the surface of the underlying insulating film 11.
The lower side of the inter-wiring space of 2A is removed by about 300 nm.

Next, after removing the resist pattern 17, as shown in FIG. 10A, a plasma CVD method using silane gas and dinitrogen monoxide gas is performed over the entire surface of the semiconductor substrate 10. A second interlayer insulating film 18 having a thickness of about 200 to 500 nm made of silicon oxide having a high directivity and a low coverage is deposited, and subsequently, a film made of silicon oxide having a good filling performance by a high density plasma CVD method. A third interlayer insulating film 19 having a thickness of about 1000 nm is deposited. As a result, the air gap 20 is formed in the inter-wiring space of the lower layer wiring 12A.

Next, as shown in FIG.
Method is used to polish the second interlayer insulating film 18 and the third interlayer insulating film 19 until the plug 16 is exposed, so that the second interlayer insulating film 18 and the third interlayer insulating film 19 are exposed. The upper surfaces of the respective plugs are flattened so as to be flush with the upper surface of the plug 16.

Next, as shown in FIG. 10C, the second interlayer insulating film 18 and the third interlayer insulating film 19 which are flattened.
An upper layer wiring 21 is formed on the above so as to be connected to the plug 16, thereby completing the two-layer wiring structure.

As described above, in the conventional semiconductor device manufacturing method, the lower layer wiring 12A and the upper layer wiring 21 are formed.
After forming the plug 16 electrically connecting to the lower layer wiring 12A, the first conductive film 12 is patterned using the plug 16 as a mask to form the lower layer wiring 12A.
Therefore, it is possible to prevent the positional deviation between the plug 16 and the lower layer wiring 12A, thereby improving the reliability of the multilayer wiring.

[0017]

However, in the conventional method of manufacturing a semiconductor device, in order to lower the position of the top of the air gap 20 formed in the inter-wiring space of the lower wiring 12A, the position shown in FIG. As shown in FIG. 3, the first interlayer insulating film 13 is etched back to project the upper portion of the plug 16 from the upper surface of the first interlayer insulating film 13. Therefore, as shown in FIG. 9B, the resist pattern 17 is formed on the base having irregularities. As a result, the accuracy of the pattern exposure is lowered and the resist pattern 17 is deformed, or the formed resist pattern 17 is partially collapsed, which makes it difficult to miniaturize the resist pattern 17 and the lower layer. It becomes difficult to miniaturize the wiring 12A, that is, the multilayer wiring.

On the other hand, if the upper portion of the plug 16 is not projected from the upper surface of the first interlayer insulating film 13, the top of the air gap 20 may reach the same height as the upper surface of the plug 16. In that case, the second interlayer insulating film 1
8 and the third interlayer insulating film 19 (FIG. 10)
(B)), the air gap 2 is formed on the upper surface of the planarized second interlayer insulating film 18 or third interlayer insulating film 19.
An opening is formed at 0, and a conductive film to be the upper layer wiring 21 enters into the opening. As a result, a formation failure such as a step break occurs in the upper layer wiring 21, and the reliability of the multilayer wiring deteriorates.

By the way, with the miniaturization of semiconductor devices,
In many cases, the plugs that connect the lower layer wiring and the upper layer wiring are arranged close to each other.

FIG. 11 is a diagram for explaining a problem that occurs when a pair of plugs for connecting a lower layer wiring and an upper layer wiring is formed by using the conventional semiconductor device manufacturing method.

FIG. 11 is different from FIG. 10B showing one step of the conventional method for manufacturing a semiconductor device in that the lower layer wiring 12A and the upper layer wiring 21 (see FIG. 10C) are connected to each other. Since the adjacent plug 22 adjacent to the plug 16 is formed, and the air gap 20 is also formed in the space between the plug 16 and the adjacent plug 22 (hereinafter, referred to as inter-plug space). is there. At this time,
Since the aspect ratio of the space between the plugs increases as the distance between the plug 16 and the adjacent plug 22 decreases,
It becomes difficult to embed the second interlayer insulating film 18 or the third interlayer insulating film 19 in the inter-plug space, and the position of the top of the air gap 20 formed in the inter-plug space becomes high. Therefore, as shown in FIG. 11, in the polishing process for the second interlayer insulating film 18 and the third interlayer insulating film 19, the planarized second interlayer insulating film 18 or the third interlayer insulating film 19 is removed. An opening 20a is formed in the air gap 20 on the upper surface, and the upper layer wiring 2 is formed in the opening 20a.
There is a possibility that the conductive film of 1 will enter. In that case, formation failure such as step breakage may occur in the upper layer wiring 21 (see FIG. 10B), the lower layer wirings 12A may be short-circuited with each other, or the plug 16 and the adjacent plug 22 may be short-circuited. The reliability of the wiring will be reduced.

In the conventional semiconductor device manufacturing method, the first conductive film 12 and the like are etched using the plug 16 as a mask (see FIG. 9C), or the plug 16 is exposed. Up to the second interlayer insulating film 18
Alternatively, the third interlayer insulating film 19 is polished (see FIG. 1).
0 (b)), the height of the plug 16 decreases during the manufacturing process. Therefore, in order to make the final height of the plug 16 equal to a predetermined value, the time when the plug 16 is formed in the connection hole 15 provided in the first interlayer insulating film 13 (see FIG. It is necessary to give a margin to the height of the plug 16 in ()). That is, it is necessary to form a connection hole 15 having a high aspect ratio in the first interlayer insulating film 13 and fill the connection hole 15 with a conductive film to be the plug 16 (hereinafter, referred to as a plug-forming conductive film).

However, as the aspect ratio of the connection hole 15 becomes higher, it becomes difficult to embed the plug-forming conductive film in the connection hole 15, and as a result, as shown in FIG. 12 (corresponding to FIG. 8C). The plug 16 formed in the connection hole 15
There is a possibility that the void 16a remains inside the plug and the electrical resistance of the plug 16 increases, resulting in a defective plug formation. This defective plug formation tends to occur due to the reduction of the plug diameter accompanying the miniaturization of the multilayer wiring.

Further, an etchback process for the first interlayer insulating film 13 (see FIG. 9A), the first conductive film 12 is performed.
The upper part of the plug 16 is etched or polished by an etching process for the above (see FIG. 9C), a polishing process for the third interlayer insulating film 19 and the like (see FIG. 10B), and the like. Therefore, as shown in FIG.
(Corresponding to), the void 16a inside the plug 16
There may be an opening formed in the. When the opening is formed in the void 16a, there is a problem that the conductive film to be the upper layer wiring 21 enters the opening and a formation failure such as a step break occurs in the upper layer wiring 21. Alternatively, the polishing abrasive grains used in the polishing step for the third interlayer insulating film 19 and the like flow into the voids 16a, that is, the inside of the plugs 16 and remain there, thereby deteriorating the electromigration resistance and the like of the plugs 16. That is, there arises a problem that the reliability of the multilayer wiring is lowered.

In view of the above, according to the present invention, the top of the air gap is made lower than the upper surface of the plug, the multilayer wiring can be miniaturized, and the formation of voids inside the plug can be prevented. The purpose is to do.

[0026]

A method of manufacturing a semiconductor device according to the present invention comprises a step of depositing a first conductive film on a semiconductor substrate and a step of forming a lower interlayer insulating film on the first conductive film. After that, a step of selectively etching the lower interlayer insulating film to form a first opening reaching the first conductive film, and filling the second conductive film in the first opening Accordingly, a step of forming a lower plug connected to the first conductive film, a step of forming a mask pattern on the lower interlayer insulating film, and then using the mask pattern and the lower plug as a mask, the lower interlayer insulating film and the first conductive film are formed. The step of sequentially etching the film to form a lower layer wiring made of the first conductive film and connected to the lower plug, an upper interlayer insulating film on the semiconductor substrate, and an air gap between wirings of the lower layer wiring. A gap will be created And a step of selectively etching the upper interlayer insulating film to form a second opening reaching the lower plug, and embedding a third conductive film in the second opening. Thus, the method includes a step of forming an upper plug connected to the lower plug and a step of forming an upper layer wiring on the upper interlayer insulating film so as to be connected to the upper plug.

According to the method of manufacturing a semiconductor device of the present invention,
After the lower plug is embedded in the lower interlayer insulating film formed on the first conductive film on the semiconductor substrate, the first plug is formed using the mask pattern and the lower plug formed on the lower interlayer insulating film.
The conductive film is patterned to form a lower layer wiring. Then, after forming an upper interlayer insulating film so that an air gap is formed in the inter-wiring space of the lower layer wiring, an upper plug connected to the lower plug is formed in the upper interlayer insulating film. Therefore, the top of the air gap can be made lower than the upper surface of the upper interlayer insulating film, that is, the upper surface of the upper plug.
In order to control the position of the top of the air gap, it is not necessary to etch back the lower interlayer insulating film in which the lower plug is embedded to project the lower plug. Therefore, since the mask pattern for forming the lower layer wiring can be formed on the lower interlayer insulating film having no unevenness, the mask pattern can be miniaturized, and thereby the lower layer wiring, that is, the multilayer wiring can be miniaturized.

Further, according to the semiconductor device manufacturing method of the present invention, even when the plugs connecting the lower layer wiring and the upper layer wiring are arranged close to each other, the upper plugs constituting the respective plugs serve as the upper interlayer insulating film. Since the plugs are embedded, no air gap is formed even in the region between the upper plugs forming each plug. Therefore, the top of the air gap can be made lower than the upper surface of each upper plug,
Since no opening is formed in the air gap on the upper surface of the upper interlayer insulating film, it is possible to prevent formation failure of the upper layer wiring.

Further, according to the method of manufacturing a semiconductor device of the present invention, the plug connecting the lower layer wiring and the upper layer wiring is divided into a lower plug and an upper plug, and a conductive film is embedded in different openings, that is, connection holes. To be formed. Therefore, since the aspect ratio of each connection hole can be lowered, the conductive film can be sufficiently embedded in each connection hole, thereby forming a void inside each of the lower plug and the upper plug. It can be prevented. Therefore, it is possible to easily realize a plug having a sufficient height while preventing an increase in electric resistance in the plug composed of the lower plug and the upper plug. Further, even if the surface of the plug is etched or polished in the middle of the manufacturing process, no opening is formed in the void inside the plug, so that formation failure such as step breakage in the upper layer wiring does not occur. It is possible to prevent this from occurring or the polishing particles entering the inside of the plug from degrading the electromigration resistance of the plug.

In the method of manufacturing a semiconductor device of the present invention,
The step of forming the lower plug preferably includes a step of flattening the upper surface of the lower interlayer insulating film so as to be flush with the upper surface of the lower plug.

In this way, the lower interlayer insulating film, which is the base of the mask pattern for forming the lower layer wiring, is made more flat, so that the mask pattern can be made finer, thereby making the lower layer wiring, that is, the multilayer wiring finer. Can be converted.

In the method of manufacturing a semiconductor device of the present invention,
The area of the upper surface of the lower plug is preferably larger than the area of the lower surface of the upper plug.

By doing so, even if misalignment occurs during the formation of the mask pattern for forming the second opening, that is, the connection hole for the upper plug, the connection between the lower plug and the upper plug is made. Since the area is sufficiently secured, the electric resistance of the entire plug does not increase. In addition, even if over-etching is performed using the mask pattern when misalignment occurs during the formation of the mask pattern, the upper surface of the lower plug acts as an etching stopper, so that the connection hole for the upper plug is formed. Can be prevented from reaching the air gap.

In the method of manufacturing a semiconductor device of the present invention,
The upper interlayer insulating film preferably has a first insulating film deposited so as to form an air gap, and a second insulating film deposited on the first insulating film. .

In this case, an insulating film having a high directivity and a low coverage is used as the first insulating film and the second insulating film is used.
By using an insulating film having a good burying property as the insulating film, the air gap can be increased and the inter-wiring capacitance can be reduced in the narrow inter-wiring space. In addition, since a high air gap with a high top position is not formed in the space between the wide wirings, it is possible to avoid a situation in which an opening is formed in the air gap in a polishing process or the like for a later interlayer insulating film. It is possible to prevent a decrease in the reliability of the multilayer wiring.

Specifically, it is preferable that the first insulating film is formed by, for example, the plasma CVD method and the second insulating film is formed by, for example, the high density plasma CVD method.

If the upper interlayer insulating film further has a third insulating film deposited on the second insulating film and having a flattened surface, the upper wiring can be easily formed. Can be done. At this time, most of the upper plug may be covered with the third insulating film.

Further, after the second insulating film is formed, the second insulating film is polished until the lower plug or the first insulating film is exposed to flatten the surface of the second insulating film. Then, the subsequent step of depositing an insulating film or a conductive film can be easily performed.

A semiconductor device according to the present invention includes a lower layer wiring formed on a semiconductor substrate and having an air gap in an inter-wiring space, an upper layer wiring formed on the lower layer wiring via an interlayer insulating film, and a lower layer wiring. And a plug connecting the upper wiring to the upper wiring. The plug has a lower plug formed on the lower wiring and an upper plug formed on the lower plug so as to be connected to the upper wiring.

According to the semiconductor device of the present invention, since it is formed by the method of manufacturing a semiconductor device of the present invention, the top of the air gap formed in the inter-wiring space of the lower layer wiring is made lower than the upper surface of the upper plug, It is possible to miniaturize the multilayer wiring and prevent voids from being formed inside the lower plug and the upper plug.

In the semiconductor device of the present invention, the area of the upper surface of the lower plug is preferably larger than the area of the lower surface of the upper plug.

By doing so, even if misalignment occurs during formation of the mask pattern for forming the connection hole for the upper plug, the connection area between the lower plug and the upper plug is sufficiently secured. Therefore, the electrical resistance of the plug as a whole does not increase. In addition, even if over-etching is performed using the mask pattern when misalignment occurs during the formation of the mask pattern, the upper surface of the lower plug acts as an etching stopper, so that the connection hole for the upper plug is formed. Can be prevented from reaching the air gap.

The semiconductor device of the present invention further includes an adjacent plug that connects the lower layer wiring and the upper layer wiring and is adjacent to the plug. The adjacent plug is formed on the lower layer wiring so as to be adjacent to the lower plug. It is preferable to have a lower plug and an adjacent upper plug formed on the adjacent lower plug so as to be adjacent to the upper plug.

With this arrangement, even if the plug composed of the lower plug and the upper plug and the adjacent plug composed of the adjacent lower plug and the adjacent upper plug are arranged close to each other, the space between the upper plug and the adjacent upper plug is reduced. Since no air gap is formed in the region, the top of the air gap can be lower than the upper surface of the upper plug or the adjacent upper plug.

In the semiconductor device of the present invention, the interlayer insulating film includes a lower interlayer insulating film deposited so as to cover the upper surface of the lower wiring and an upper interlayer insulating film deposited on the lower interlayer insulating film. The upper interlayer insulating film may have a first insulating film deposited so as to form an air gap and a second insulating film deposited on the first insulating film. preferable.

In this case, an insulating film having a high directivity and a low coverage is used as the first insulating film and the second insulating film is used.
By using an insulating film having a good burying property as the insulating film, the air gap can be increased and the inter-wiring capacitance can be reduced in the narrow inter-wiring space. In addition, since a high air gap with a high top position is not formed in the space between the wide wirings, it is possible to avoid a situation in which an opening is formed in the air gap in a polishing process or the like for a later interlayer insulating film. It is possible to prevent a decrease in the reliability of the multilayer wiring.

If the upper interlayer insulating film further has a third insulating film deposited on the second insulating film and having a flattened surface, the formation of the upper layer wiring is facilitated. Can be done. At this time, most of the upper plug may be covered with the third insulating film.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention will be described below with reference to the drawings.

1A to 1D and 2A to 2C.
3A to 3C are cross-sectional views showing each step of the method for manufacturing the semiconductor device according to the first embodiment.

First, as shown in FIG. 1A, on a semiconductor substrate 100 made of, for example, silicon, a base insulating film 101 made of, for example, silicon oxide and a first conductive film made of, for example, an aluminum alloy and having a film thickness of about 600 nm. Membrane 10
2 are sequentially deposited. After that, a film thickness of 300 to 600 n made of, for example, silicon oxide is formed on the first conductive film 102.
The first interlayer insulating film 103 of about m ("Claims")
"Lower interlayer insulating film") is deposited, a mask pattern (not shown) having an opening in the lower plug formation region is formed on the first interlayer insulating film 103, and then the mask pattern is used. The aperture 4 which reaches the first conductive film 102 is obtained by performing etching on the first interlayer insulating film 103.
The first connection hole 104 having a thickness of about 00 nm is formed.

Next, a second conductive film made of, for example, tungsten is formed over the entire surface of the first interlayer insulating film 103 including the first connection hole 104 by using, for example, an evaporation method. After depositing so that the connection hole 104 is completely filled, C
By polishing and removing the second conductive film outside the first connection hole 104 by using the MP method, as shown in FIG. 1B, the lower plug 105 connected to the first conductive film 102.
To form. At this time, since the aspect ratio of the first connection hole 104 (for example, about 1 to 1.5) is relatively small, the first connection hole 104 can be completely filled with the second conductive film. No void is formed inside 105. At this time, the upper surface of the first interlayer insulating film 103 is flattened so as to be flush with the upper surface of the lower plug 105.

Next, as shown in FIG. 1C, a resist pattern 106 that covers the lower layer wiring formation region is formed on the first interlayer insulating film 103. At this time, the resist pattern 106 is formed as a base (first interlayer insulating film 10) having no unevenness.
3) Since it is formed on the resist pattern 106, the resist pattern 106 can be miniaturized.

Next, as shown in FIG. 1D, the first interlayer insulating film 103 and the first conductive film 102 are sequentially etched using the resist pattern 106 and the lower plug 105 as a mask, and the first interlayer insulating film 103 and the first conductive film 102 are sequentially etched. The lower layer wiring 102A made of the first conductive film 102 and connected to the lower plug 105 is formed.

In the step shown in FIG. 1D, after the lower layer wiring 102A is formed, the underlying insulating film 101 is etched by using the resist pattern 106 and the lower plug 105 as a mask, and the surface of the underlying insulating film 101 is etched. The lower side of the inter-wiring space of the lower layer wiring 102A in the portion is removed by about 300 nm, for example. As a result, the air gap 109 (see FIG. 2A) to be formed in a later step is formed to a lower position, whereby the air gap 109 can be formed so as to face the entire side surface of the lower layer wiring 102A. Further, the inter-wiring capacitance of the lower layer wiring 102A is further reduced.

Next, after removing the resist pattern 106, as shown in FIG. 2A, a plasma CVD method using, for example, silane gas and dinitrogen monoxide gas is performed over the entire surface of the semiconductor substrate 100. Then, a second interlayer insulating film 107 (“first insulating film” of “upper interlayer insulating film” in “Claims”) having a film thickness of about 200 to 500 nm made of, for example, silicon oxide is deposited. Subsequently, plasma CVD using higher density plasma than the plasma CVD method used for forming the second interlayer insulating film 107.
Method, for example, high density plasma CVD method, for example, the third interlayer insulating film 108 made of silicon oxide and having a film thickness of about 1000 nm (“upper interlayer insulating film” in “Claims”).
Of the "second insulating film"). This allows
An air gap 10 is formed in the space between the lower layer wirings 102A.
9 is formed.

Here, since the second interlayer insulating film 107 has a high directivity and a low coverage, the third interlayer insulating film 108 has a good burying property, so that the lower layer as shown in FIG. The inter-wiring capacitance can be reduced by increasing the air gap 109 formed in the narrow inter-wiring space of the wiring 102A. Further, in the inter-wiring space having a wide width among the inter-wiring spaces of the lower layer wiring 102A,
Since the air gap 109 having a high top position is not formed, the subsequent polishing step for the interlayer insulating film (see FIG. 2).
It is possible to avoid a situation in which an opening is formed in the air gap 109 due to (b) or the like, and thus it is possible to prevent the reliability of the multilayer wiring from being degraded.

Next, as shown in FIG. 2B, the second interlayer insulating film 107 and the third interlayer insulating film 108 are polished by the CMP method so that the second interlayer insulating film 107 is polished. The upper surfaces of the insulating film 107 and the third interlayer insulating film 108 are flattened. At this time, the third interlayer insulating film 108
By polishing until the second interlayer insulating film 107 is exposed, the upper surface of the third interlayer insulating film 108 is planarized so as to be flush with the upper surface of the second interlayer insulating film 107. Good. Further, the second interlayer insulating film 107 and the third interlayer insulating film 108 are polished until the lower plug 105 is exposed, so that the second interlayer insulating film 107 is formed.
The upper surfaces of the third and third interlayer insulating films 108 may be flattened so as to be flush with the upper surface of the lower plug 105.

Next, as shown in FIG. 2C, the planarized second interlayer insulating film 107 and third interlayer insulating film 10 are formed.
8 over the entire surface and a fourth interlayer insulating film 110 made of, for example, silicon oxide and having a film thickness of about 400 to 800 nm.
(“Third insulating film” of “upper interlayer insulating film” in “Claims”) is deposited. After that, the surface of the fourth interlayer insulating film 110 is flattened, and then a mask pattern 111 having an opening in an upper plug formation region is formed on the flattened fourth interlayer insulating film 110.

Next, at least the fourth interlayer insulating film 110 is etched using the mask pattern 111, and as shown in FIG. 3A, the second plug having a diameter of about 400 nm reaching the lower plug 105 is formed. The connection hole 112 is formed.

Next, a third conductive film made of, for example, tungsten is formed over the entire surface of the fourth interlayer insulating film 110 including the second connection hole 112 by using, for example, an evaporation method. After depositing so that the connection hole 112 is completely filled, C
By polishing and removing the third conductive film outside the second connection hole 112 by using the MP method, as shown in FIG. 3B, the upper plug 113 connected to the lower plug 105 is formed. . At this time, since the aspect ratio of the second connection hole 112 (for example, about 1 to 2) is relatively small, the second connection hole 112 can be completely filled with the third conductive film. No void is formed inside. At this time, the lower plug 105
And the upper plug 113 are directly connected,
Electrically connected to each other.

Next, as shown in FIG. 3C, an upper layer wiring 114 is formed on the fourth interlayer insulating film 110 so as to be connected to the upper plug 113, thereby completing a two-layer wiring structure. Let

As described above, according to the first embodiment, the lower plug 105 is formed on the first interlayer insulating film 103 formed on the first conductive film 102 on the semiconductor substrate 100.
After burying it, the first conductive film 102 is patterned by using the resist pattern 106 and the lower plug 105 formed on the first interlayer insulating film 103 to form the lower wiring 102.
Form A. After that, the second interlayer insulating film 107 and the third interlayer insulating film 108 are sequentially deposited so that the air gap 109 is formed in the inter-wiring space of the lower layer wiring 102A, and then the fourth interlayer insulating film 110 is further formed. After the deposition, the upper plug 113 connected to the lower plug 105 is formed on at least the fourth interlayer insulating film 110. Therefore, the top of the air gap 109 is covered with the fourth interlayer insulating film 11
Since it can be lower than the upper surface of 0, that is, the upper surface of the upper plug 113, the first plug in which the lower plug 105 is embedded in order to control the position of the top of the air gap 109.
It is not necessary to etch back the interlayer insulating film 103 to cause the lower plug 105 to project. Therefore, since the resist pattern 106 for forming the lower layer wiring can be formed on the first interlayer insulating film 103 having no unevenness (see FIG. 1C), the resist pattern 106 can be miniaturized, whereby the lower layer wiring 102A, that is, the multilayer structure. The wiring can be miniaturized.

Further, according to the first embodiment, the plug connecting the lower layer wiring 102A and the upper layer wiring 114 is divided into the lower plug 105 and the upper plug 113, and different connecting holes, specifically, It is formed by embedding a conductive film in the first connection hole 104 and the second connection hole 112. Therefore, since the aspect ratio of each connection hole can be lowered, the conductive film can be sufficiently embedded in each connection hole, thereby forming a void inside each of the lower plug 105 and the upper plug 113. Can be prevented. Therefore, the lower plug 105 and the upper plug 1
It is possible to easily realize a plug having a sufficient height while preventing an increase in electric resistance in the plug formed by 13. Also, if the surface of the plug is etched or polished during the manufacturing process,
Since no opening is formed in the void inside the plug, formation failure such as step breakage may occur in the upper wiring 114,
Alternatively, it is possible to prevent the abrasive particles for polishing from entering the inside of the plug to deteriorate the electromigration resistance of the plug.

Further, according to the first embodiment, when the lower plug 105 is embedded in the first connection hole 104 formed in the first interlayer insulating film 103, the first interlayer insulating film 10 is formed.
Since the upper surface of 3 is flattened so as to be flush with the upper surface of the lower plug 105, the first interlayer insulating film 103, which is the base of the resist pattern 106 for forming the lower layer wiring, is further flattened. The resist pattern 106 can be further miniaturized, and thereby the lower layer wiring 102A, that is, the multilayer wiring can be further miniaturized.

In the first embodiment, the lower layer wiring 1
Although a two-layer wiring structure composed of 02A and the upper layer wiring 114 is premised, the present invention is not limited to this, and even in a wiring structure of three or more layers, a plug for connecting vertically adjacent wirings is divided into a lower portion and an upper portion, The same effect as that of the first embodiment can be obtained by repeating the step of forming conductive films by embedding in different connection holes.

Further, in the first embodiment, the plug connecting the lower layer wiring 102A and the upper layer wiring 114 is divided into two stages of the lower plug 105 and the upper plug 113, and the conductive film is embedded in different connection holes. However, the present invention is not limited to this, and even if the plugs that connect vertically adjacent wirings are divided into three or more stages and the conductive films are embedded in the different connection holes, it is possible to form the first embodiment. The same effect can be obtained.

In addition, in the first embodiment, the first interlayer insulating film 103, the first conductive film 102, and the base insulating film 1
01 is sequentially etched (FIG. 1 (d))
Although the resist pattern 106 was used as a mask in the etching process for the first conductive film 102 or the base insulating film 101, instead of this, the first conductive film 10 was used instead.
2 or in the etching process for the base insulating film 101,
The patterned first interlayer insulating film 103 may be used as a mask. In this case, it is preferable to thickly deposit the first interlayer insulating film 103 in the step shown in FIG.

In the first embodiment, the second interlayer insulating film 107 and the third interlayer insulating film 108 are formed between the formation of the lower layer wiring 102A and the formation of the upper layer wiring 114.
And the fourth interlayer insulating film 110 is formed.
The number, type, and deposition method of the interlayer insulating film (upper interlayer insulating film) formed from the formation of 02A to the formation of the upper wiring 114 are not particularly limited.

(Modified Example of First Embodiment) A semiconductor device according to a modified example of the first embodiment and a method for manufacturing the same will be described below with reference to the drawings.

FIG. 4 shows a cross-sectional view of one step in the method of manufacturing a semiconductor device according to the modification of the first embodiment. Note that FIG. 4 corresponds to FIG. 3B showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

The modification of the first embodiment is different from that of the first embodiment as shown in FIG.
Adjacent lower plug 115 is formed on 2A adjacent to lower plug 105, and adjacent upper plug 116 is formed on adjacent lower plug 115 adjacent to upper plug 113. Is. At this time, the adjacent lower plug 115 is formed by the same forming method as that of the lower plug 105 (see FIGS. 1A and 1B), and the adjacent upper plug 116 is formed by the same forming method as that of the upper plug 113 (see FIG. 2). (C) and FIGS. 3 (a) and 3 (b)).

According to the modification of the first embodiment, the following effects can be obtained in addition to the effects of the first embodiment.

That is, one plug composed of the lower plug 105 and the upper plug 113 and the adjacent lower plug 115.
And the adjacent upper plug 116 and the other adjacent plug are arranged close to each other, the upper plug 113 and the adjacent upper plug 116 are at least the fourth interlayer insulating film 1 respectively.
Since it is embedded in 10, the air gap 109 is not formed even in the region between the upper plug 113 and the adjacent upper plug 116. Therefore, the top of the air gap 109 can be made lower than the upper surface of the upper plug 113 or the adjacent upper plug 116, so that no opening is formed in the air gap 109 on the upper surface of the fourth interlayer insulating film 110. Therefore, formation failure of the upper layer wiring 114 can be prevented.

(Second Embodiment) A semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described below.
A description will be given with reference to the drawings.

FIGS. 5A to 5D and FIGS. 6A to 6C.
7A to 7C are cross-sectional views showing the respective steps of the method for manufacturing the semiconductor device according to the second embodiment.

First, as shown in FIG. 5A, on a semiconductor substrate 200 made of, for example, silicon, a base insulating film 201 made of, for example, silicon oxide and a first conductive film made of, for example, an aluminum alloy and having a thickness of about 600 nm are formed. Membrane 20
2 are sequentially deposited. After that, a film thickness of 300 to 600 n made of, for example, silicon oxide is formed on the first conductive film 202.
m of the first interlayer insulating film 203 ("Claims")
"Lower interlayer insulating film") is deposited, a mask pattern (not shown) having an opening in the lower plug formation region is formed on the first interlayer insulating film 203, and then the mask pattern is used. The first interlayer insulating film 203 is etched to reach the first conductive film 202 with a diameter of 5
A first connection hole 204 of about 00 nm is formed.

Next, a second conductive film made of, for example, tungsten is formed over the entire surface of the first interlayer insulating film 203 including the first connection hole 204 by using, for example, a vapor deposition method. After depositing so that the connection hole 204 is completely filled, C
By polishing and removing the second conductive film outside the first connection hole 204 by using the MP method, as shown in FIG. 5B, the lower plug 205 connected to the first conductive film 202.
To form. At this time, since the aspect ratio (about 0.6 to 1.2) of the first connection hole 204 is relatively small,
Since the connection hole 204 of 1 is completely filled with the second conductive film, no void is formed inside the lower plug 205. At this time, the lower plug 2
The area of the upper surface of 05 is made larger than the area of the lower surface of the upper plug 213 (see FIG. 7B) formed in a later step. Further, at this time, the upper surface of the first interlayer insulating film 203 is planarized so as to be flush with the upper surface of the lower plug 205.

Next, as shown in FIG. 5C, a resist pattern 206 covering the lower layer wiring formation region is formed on the first interlayer insulating film 203. At this time, the resist pattern 206 is formed as a base (first interlayer insulating film 20) having no unevenness.
3) Since it is formed on the resist pattern 206, the resist pattern 206 can be miniaturized.

Next, as shown in FIG. 5D, the first interlayer insulating film 203 and the first conductive film 202 are sequentially etched using the resist pattern 206 and the lower plug 205 as a mask, and the first interlayer insulating film 203 and the first conductive film 202 are etched. The lower layer wiring 202A made of the first conductive film 202 and connected to the lower plug 205 is formed.

Further, in the step shown in FIG. 5D, after the lower layer wiring 202A is formed, the base insulating film 201 is etched using the resist pattern 206 and the plug lower portion 205 as a mask to form the surface of the base insulating film 201. The lower side of the inter-wiring space of the lower layer wiring 202A in the portion is removed by about 300 nm, for example. As a result, the air gap 209 (see FIG. 6A) formed in a later step is formed to a lower position, whereby the air gap 209 can be formed so as to face the entire side surface of the lower layer wiring 202A. The inter-wiring capacitance of the lower layer wiring 202A is further reduced.

Next, after removing the resist pattern 206, as shown in FIG. 6A, a plasma CVD method using, for example, silane gas and dinitrogen monoxide gas is performed over the entire surface of the semiconductor substrate 200. Then, a second interlayer insulating film 207 (for example, “first insulating film” of “upper interlayer insulating film” in “Claims”) having a film thickness of about 200 to 500 nm made of silicon oxide is deposited. Subsequently, plasma CVD using higher density plasma than the plasma CVD method used for forming the second interlayer insulating film 207.
Method, for example, high density plasma CVD method, for example, a third interlayer insulating film 208 made of silicon oxide and having a film thickness of about 1000 nm (“upper interlayer insulating film” in “Claims”).
Of the "second insulating film"). This allows
An air gap 20 is provided in the space between the lower layer wirings 202A.
9 is formed.

Here, the second interlayer insulating film 207 has a high directivity and a low coverage ratio, while the third interlayer insulating film 208 has a good burying performance, so that the lower layer as shown in FIG. The inter-wiring capacitance can be reduced by increasing the air gap 209 formed in the narrow inter-wiring space of the wiring 202A. Moreover, in the inter-wiring space having a wide width among the inter-wiring spaces of the lower layer wiring 202A,
Since the air gap 209 having a high top position is not formed, a polishing process for a later interlayer insulating film (see FIG. 6).
It is possible to avoid a situation in which an opening is formed in the air gap 209 due to (see (b)) or the like, and thus it is possible to prevent a decrease in reliability of the multilayer wiring.

Next, as shown in FIG. 6B, the second interlayer insulating film 207 and the third interlayer insulating film 208 are polished by the CMP method so that the second interlayer insulating film 207 is polished. The upper surfaces of the insulating film 207 and the third interlayer insulating film 208 are flattened. At this time, the third interlayer insulating film 208
By polishing until the second interlayer insulating film 207 is exposed, the upper surface of the third interlayer insulating film 208 is planarized so as to be flush with the upper surface of the second interlayer insulating film 207. Good. In addition, the second interlayer insulating film 207 and the third interlayer insulating film 208 are polished until the lower plug 205 is exposed, so that the second interlayer insulating film 207 is formed.
The upper surfaces of the third and third interlayer insulating films 208 may be flattened so as to be flush with the upper surface of the lower plug 205.

Next, as shown in FIG. 6C, the second interlayer insulating film 207 and the third interlayer insulating film 20 which are flattened.
8 over the entire surface and a fourth interlayer insulating film 210 made of, for example, silicon oxide and having a film thickness of about 400 to 800 nm.
(“Third insulating film” of “upper interlayer insulating film” in “Claims”) is deposited. After that, the surface of the fourth interlayer insulating film 210 is flattened, and then a mask pattern 211 having an opening in an upper plug formation region is formed on the flattened fourth interlayer insulating film 210.

Next, at least the fourth interlayer insulating film 210 is etched using the mask pattern 211, and as shown in FIG. 7A, a second plug having a diameter of about 350 nm reaching the lower plug 205 is formed. The connection hole 212 is formed.

Next, a third conductive film made of, for example, tungsten is formed over the entire surface of the fourth interlayer insulating film 210 including the second connection hole 212 by using, for example, a vapor deposition method or the like. After depositing so that the connection hole 212 is completely filled, C
By polishing and removing the third conductive film outside the second connection hole 212 using the MP method, the upper plug 213 connected to the lower plug 205 is formed as shown in FIG. 7B. . At this time, since the aspect ratio of the second connection hole 212 (about 1.0 to 2.5) is relatively small, the second connection hole 212 can be completely filled with the third conductive film. No void is formed inside the plug 213. At this time, the lower plug 20
5 and the upper plug 213 are directly connected to each other so that they are electrically connected to each other. Further, at this time, the area of the lower surface of the upper plug 213 is smaller than the area of the upper surface of the lower plug 205.

Next, as shown in FIG. 7C, an upper wiring 214 is formed on the fourth interlayer insulating film 210 so as to be connected to the upper plug 213, thereby completing a two-layer wiring structure. Let

As described above, according to the second embodiment, the lower plug 205 is formed on the first interlayer insulating film 203 formed on the first conductive film 202 on the semiconductor substrate 200.
And then the first conductive film 202 is patterned by using the resist pattern 206 and the lower plug 205 formed on the first interlayer insulating film 203 to form the lower wiring 202A.
To form. After that, a second interlayer insulating film 207 and a third interlayer insulating film 208 are sequentially deposited so that an air gap 209 is formed in the inter-wiring space of the lower layer wiring 202A, and then a fourth interlayer insulating film 210 is further formed. Then, the lower plug 2 is deposited on at least the fourth interlayer insulating film 210.
The upper plug 213 connected to 05 is formed. Therefore, the top portion of the air gap 209 is covered with the fourth interlayer insulating film 21.
Since it can be lower than the upper surface of 0, that is, the upper surface of the upper plug 213, the lower plug 205 is embedded in order to control the position of the top of the air gap 209.
It is not necessary to etch back the interlayer insulating film 203 to expose the lower plug 205. Therefore, since the resist pattern 206 for forming the lower layer wiring can be formed on the first interlayer insulating film 203 having no unevenness (see FIG. 5C), the resist pattern 206 can be miniaturized, whereby the lower layer wiring 202A, that is, the multilayer wiring. The wiring can be miniaturized.

Further, according to the second embodiment, the plug connecting the lower layer wiring 202A and the upper layer wiring 214 is divided into the lower plug 205 and the upper plug 213, and different connecting holes, specifically, It is formed by embedding a conductive film in the first connection hole 204 and the second connection hole 212. Therefore, since the aspect ratio of each connection hole can be lowered, the conductive film can be sufficiently embedded in each connection hole, thereby forming a void inside each of the lower plug 205 and the upper plug 213. Can be prevented. Therefore, the lower plug 205 and the upper plug 2
It is possible to easily realize a plug having a sufficient height while preventing an increase in electric resistance in the plug formed by 13. Also, if the surface of the plug is etched or polished during the manufacturing process,
Since no opening is formed in the void inside the plug, formation failure such as step breakage may occur in the upper wiring 214,
Alternatively, it is possible to prevent the abrasive particles for polishing from entering the inside of the plug to deteriorate the electromigration resistance of the plug.

Further, according to the second embodiment, when the lower plug 205 is embedded in the first connection hole 204 formed in the first interlayer insulating film 203, the first interlayer insulating film 20 is formed.
3 is planarized so as to be flush with the upper surface of the lower plug 205, the first interlayer insulating film 203, which is the base of the resist pattern 206 for forming the lower layer wiring, is further planarized. The resist pattern 206 can be further miniaturized, whereby the lower layer wiring 202A, that is, the multilayer wiring can be further miniaturized.

Further, according to the second embodiment, since the area of the upper surface of the lower plug 205 is made larger than the area of the lower surface of the upper plug 213, the second plug for the upper plug 213 is formed.
Pattern 211 for forming the connection hole 212 of
Even if misalignment occurs during the formation of the plug, the connection area between the lower plug 205 and the upper plug 213 is sufficiently secured, so that the electrical resistance of the entire plug does not increase. In addition, when misalignment occurs during formation of the mask pattern 211, even if overetching is performed using the mask pattern 211, the upper surface of the lower plug 205 acts as an etching stopper, so the second connection hole 212 is formed. Can be prevented from reaching the air gap 209.

In the second embodiment, the lower layer wiring 2
Although a two-layer wiring structure composed of 02A and the upper layer wiring 214 is premised, the present invention is not limited to this, and even in a wiring structure of three or more layers, the plug connecting the vertically adjacent wirings is divided into the lower portion and the upper portion, The same effect as in the second embodiment can be obtained by repeating the step of forming conductive films in different connection holes.

In the second embodiment, the plug connecting the lower layer wiring 202A and the upper layer wiring 214 is divided into two stages, the lower plug 205 and the upper plug 213, and the conductive films are embedded in different connection holes. However, the present invention is not limited to this, and even if the plugs that connect the vertically adjacent wirings are divided into three or more stages and the conductive films are embedded in the different connection holes, it is possible to form the second embodiment. The same effect can be obtained.

In addition, in the second embodiment, the first interlayer insulating film 203, the first conductive film 202, and the base insulating film 2
01 is sequentially etched (FIG. 5D)
Although the resist pattern 206 was used as a mask in the etching process for the first conductive film 202 or the base insulating film 201, instead of this, the first conductive film 20 was used instead.
2 or in the etching process for the base insulating film 201,
The patterned first interlayer insulating film 203 may be used as a mask. In this case, it is preferable that the first interlayer insulating film 203 be deposited thickly in the step shown in FIG.

In the second embodiment, the second interlayer insulating film 207 and the third interlayer insulating film 208 are formed between the formation of the lower layer wiring 202A and the formation of the upper layer wiring 214.
And the fourth interlayer insulating film 210 is formed.
The number, type, and deposition method of the interlayer insulating film (upper interlayer insulating film) formed from the formation of 02A to the formation of the upper wiring 214 are not particularly limited.

Further, in the second embodiment, the area of the upper surface of the lower plug 205 is made larger than the area of the lower surface of the upper plug 213, but instead of this, the upper plug 213 is used.
The area of the lower surface of the lower plug 205 may be larger than the area of the upper surface of the lower plug 205. In this case, even if misalignment occurs during formation of the mask pattern 211, the lower plug 205
Since the connection area between the upper plug and the upper plug 213 is sufficiently secured, the electric resistance of the entire plug does not increase.

Further, in the second embodiment, the same forming method as the lower plug 205 (see FIGS. 5A and 5B).
Is used to form an adjacent lower plug so as to be adjacent to the lower plug 205 on the lower layer wiring 202A, and a forming method similar to that of the upper plug 213 (FIGS. 6C and 7).
The adjacent upper plug may be formed on the adjacent lower plug so as to be adjacent to the upper plug 213 by using (a) and (b). With this configuration, even if one plug including the lower plug 205 and the upper plug 213 and another plug including the adjacent lower plug and the adjacent upper plug are arranged close to each other, the upper plug 213 and the adjacent upper plug are Since each is buried in at least the fourth interlayer insulating film 210, the air gap 209 is not formed even in the region between the upper plug 213 and the adjacent upper plug. Therefore, since the top of the air gap 209 can be made lower than the upper surface of the upper plug 213 or the adjacent upper plug, an opening is not formed in the air gap 209 on the upper surface of the fourth interlayer insulating film 210. It is possible to prevent the formation failure of the upper layer wiring 214. When forming the adjacent lower plug and the adjacent upper plug, the area of the upper surface of the adjacent lower plug is made larger than the area of the lower surface of the adjacent upper plug, or the area of the lower surface of the adjacent upper plug is set to the upper surface of the adjacent lower plug. The area is preferably larger than the area.

[0098]

According to the present invention, the top of the air gap can be made lower than the top surface of the upper plug. Therefore, in order to control the position of the top of the air gap, the lower interlayer insulating film having the lower plug buried therein is controlled. There is no need to etch back to project the lower plug. Therefore,
Since the mask pattern for forming the lower layer wiring can be formed on the lower interlayer insulating film having no unevenness, the mask pattern can be miniaturized, and thereby the multilayer wiring can be miniaturized.

Further, according to the present invention, even when the plugs connecting the lower layer wiring and the upper layer wiring are arranged close to each other, the top of the air gap is made lower than the upper surface of the upper plug constituting each plug. be able to. Therefore, no opening is formed in the air gap on the upper surface of the upper interlayer insulating film, so that formation failure of the upper layer wiring can be prevented.

Further, according to the present invention, it is possible to prevent voids from being formed inside the lower plug and the upper plug, and thus to prevent an increase in electric resistance in the plug formed by the lower plug and the upper plug. In addition, since openings are not formed in the voids inside the plugs by polishing or the like, it is possible to prevent defective formation of the upper layer wiring or deterioration of electromigration resistance of the plugs.

[Brief description of drawings]

1A to 1D are cross-sectional views showing each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

2A to 2C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

3A to 3C are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device according to the modification of the first embodiment of the present invention.

5A to 5D are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

6A to 6C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

7A to 7C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

8A to 8C are cross-sectional views showing respective steps of a conventional method for manufacturing a semiconductor device.

9A to 9C are cross-sectional views showing respective steps of a conventional method for manufacturing a semiconductor device.

10A to 10C are cross-sectional views showing respective steps of a conventional method for manufacturing a semiconductor device.

FIG. 11 is a diagram illustrating a problem that occurs when a pair of plugs that connect a lower layer wiring and an upper layer wiring is formed by using a conventional method for manufacturing a semiconductor device.

FIG. 12 is a diagram illustrating a problem that occurs when a conventional semiconductor device manufacturing method is used.

FIG. 13 is a diagram illustrating a problem that occurs when a conventional method of manufacturing a semiconductor device is used.

[Explanation of symbols]

100, 200 Semiconductor substrate 101, 201 Base insulating film 102, 202 First conductive film 102A, 202A lower layer wiring 103, 203 First interlayer insulating film 104, 204 First connection hole 105, 205 Lower plug 106, 206 resist pattern 107, 207 Second interlayer insulating film 108, 208 Third interlayer insulating film 109,209 Air gap 110, 210 Fourth interlayer insulating film 111, 211 mask pattern 112, 212 Second connection hole 113,213 Upper plug 114, 214 Upper layer wiring 115 Adjacent lower plug 116 Adjacent upper plug

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 2000-58651 (JP, A) JP 10-233449 (JP, A) JP 9-213697 (JP, A) JP 63-175443 (JP, A) JP 2002-124516 (JP, A) JP 2002-110793 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (5)

(57) [Claims] 1. A first conductive film is deposited on a semiconductor substrate.
And a step of forming a lower interlayer insulating film on the first conductive film,
Selectively etching the lower interlayer insulating film
Forming a first opening reaching the first conductive film.
And a step of embedding a second conductive film in the first opening.
Form a lower plug connected to the first conductive film.
And a mask pattern was formed on the lower interlayer insulating film.
After that, the mask pattern and the lower plug are used as a mask.
Then, with respect to the lower interlayer insulating film and the first conductive film,
The first conductive film is formed by sequentially etching.
The step of forming a lower layer wiring connected to the lower plug
And an upper interlayer insulating film on the semiconductor substrate, the lower wiring
So that an air gap is formed in the space between
And the selective etching of the upper interlayer insulating film.
To form a second opening reaching the lower plug.
And a step of embedding a third conductive film in the second opening.
To form the upper plug that connects with the lower plug.
The upper plug is connected to the upper interlayer insulating film.
And forming a sea urchin upper wiring, the step of forming the lower plug, and characterized in that it comprises a step of planarizing so that the upper surface of the lower interlayer insulating layer on the upper surface flush with the lower plug Of manufacturing a semiconductor device . 2. A first conductive film is deposited on a semiconductor substrate.
And a step of forming a lower interlayer insulating film on the first conductive film,
Selectively etching the lower interlayer insulating film
Forming a first opening reaching the first conductive film.
And a step of embedding a second conductive film in the first opening.
Form a lower plug connected to the first conductive film.
And a mask pattern was formed on the lower interlayer insulating film.
After that, the mask pattern and the lower plug are used as a mask.
Then, with respect to the lower interlayer insulating film and the first conductive film,
The first conductive film is formed by sequentially etching.
The step of forming a lower layer wiring connected to the lower plug
And an upper interlayer insulating film on the semiconductor substrate, the lower wiring
So that an air gap is formed in the space between
And the selective etching of the upper interlayer insulating film.
To form a second opening reaching the lower plug.
And a step of embedding a third conductive film in the second opening.
To form the upper plug that connects with the lower plug.
The upper plug is connected to the upper interlayer insulating film.
And forming a sea urchin upper wiring, the area of the upper surface of the lower plug, a method of manufacturing a semiconductor device, characterized in that greater than the area of the lower surface of said upper plug. 3. The upper interlayer insulating film is the air gap.
A first insulating film deposited to form a
A second insulating film deposited on the first insulating film , wherein the first insulating film is formed by a plasma CVD method, and the second insulating film is different from the plasma CVD method. 3. The method of manufacturing a semiconductor device according to claim 1 , wherein the semiconductor device is formed by a high-density plasma CVD method using high-density plasma. 4. The air gap is formed on the upper interlayer insulating film.
A first insulating film deposited to form a
A second insulating film deposited on the first insulating film, wherein the upper interlayer insulating film is deposited on the second insulating film and has a flattened surface. 3. The method for manufacturing a semiconductor device according to claim 1 , further comprising: Wherein said upper plug claims, characterized in that the majority of which is covered with the third insulating film
Item 5. A method of manufacturing a semiconductor device according to item 4 .