KR100244713B1 - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device Download PDF

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KR100244713B1
KR100244713B1 KR1019970028816A KR19970028816A KR100244713B1 KR 100244713 B1 KR100244713 B1 KR 100244713B1 KR 1019970028816 A KR1019970028816 A KR 1019970028816A KR 19970028816 A KR19970028816 A KR 19970028816A KR 100244713 B1 KR100244713 B1 KR 100244713B1
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South Korea
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film
interlayer insulating
oxide film
dielectric constant
low dielectric
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KR1019970028816A
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Korean (ko)
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KR19990004680A (en
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이성준
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Abstract

본 발명은 반도체 소자의 제조 방법을 개시한다. 개시된 본 발명의 반도체소자의 제조 방법은 콘택홀들을 갖는 제 1 층간 절연막이 형성된 반도체 기판을 제공하는 단계; 상기 콘택홀들 내에 각각 텅스텐 플러그를 형성하는 단계; 상기 텅스텐 플러그 및 제 1 층간 절연막 상에 알루미늄 합금막 및 소정 두께의 제 1 산화막을 적층하는 단계; 상기 텅스텐 플러그 및 그에 인접된 제 1 층간 절연막 상에만 제 1 산화막 및 알루미늄 합금막이 남도록 상기 제 1 산화막 및 알루미늄 합금막을 패터닝하는 단계; 상기 잔류된 제 1 산화막 및 알루미늄 합금막의 측부와 상기 제 1 층간 절연막 상에 소정 두께의 제 2 산화막을 형성하는 단계; 상기 제 2 산화막 상에 제 2 층간 절연막으로서 저유전상수 물질을 증착하는 단계; 상기 제 2 산화막을 식각 정지층으로 하여 상시 저유전상수 물질을 식각하는 단계; 및 상기 잔류된 제 2 산화막 및 저유전상수 물질 상에 제 3 층간 절연막을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a method for manufacturing a semiconductor device. The disclosed method of manufacturing a semiconductor device includes the steps of: providing a semiconductor substrate having a first interlayer insulating film having contact holes; Forming a tungsten plug in each of the contact holes; Stacking an aluminum alloy film and a first oxide film having a predetermined thickness on the tungsten plug and the first interlayer insulating film; Patterning the first oxide film and the aluminum alloy film such that a first oxide film and an aluminum alloy film remain only on the tungsten plug and the first interlayer insulating film adjacent thereto; Forming a second oxide film having a predetermined thickness on the side portions of the remaining first oxide film and the aluminum alloy film and the first interlayer insulating film; Depositing a low dielectric constant material on the second oxide film as a second interlayer insulating film; Etching the low dielectric constant material at all times using the second oxide layer as an etch stop layer; And forming a third interlayer insulating film on the remaining second oxide film and the low dielectric constant material.

Description

반도체 소자의 제조 방법.Method of manufacturing a semiconductor device.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는, 상·하부 금속들간을 절연시키기 위한 층간 절연막으로서 저유전상수 물질을 이용함으로써 소자의 RC 지연 및 크로스토크(Crosstalk)를 감소시킨 반도체 소자의 제조방법에 관한 것이다BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device having a low RC constant and crosstalk reduced by using a low dielectric constant material as an interlayer insulating film for insulating between upper and lower metals. Relates to a method for producing

일반적으로, 반도체 소자의 제조 방법에서 상·하부 금속 배선들간을 절연시키기 위한 재료로는 주로 산화막이 이용되며, 소자를 평탄화시키기 위한 막들로는 흐름성이 우수한 SOG(Spin On Glass) 및 BPSG(Boro-phosphorus Silicate Glass)막들이 주로 이용되고 있다.In general, an oxide film is mainly used as a material for insulating the upper and lower metal interconnections in a method of manufacturing a semiconductor device, and as a film for planarizing the device, an on-flow flow on glass (SOG) and a BPSG (Boro-) are excellent. Phosphorus Silicate Glass) films are mainly used.

도 1a 내지 도 1c는 상기와 같은 막들을 이용한 종래 기술에 따른 반도체 소자의 제조 방법을 설명하기 위한 도면으로서, 도 1a를 참조하면, 게이트 전극(도시않됨) 및 접합 영역들(도시않됨)이 구비된 반도체 기판(1) 상에 제 1 층간 절연막(2)을 형성하고, 상기 제 1 층간 절연막(2)을 식각하여 접합 영역들을 노출시키는 콘택홀들(3)을 형성한다.1A to 1C are diagrams for describing a method of manufacturing a semiconductor device according to the related art using the above films. Referring to FIG. 1A, a gate electrode (not shown) and junction regions (not shown) are provided. The first interlayer insulating film 2 is formed on the semiconductor substrate 1, and the first interlayer insulating film 2 is etched to form contact holes 3 exposing the junction regions.

도 1b를 참조하면, 전체 상부에 알루미늄 금속막 또는 알루미늄 합금막을 증착하고, 이를 패터닝하여 콘택홀 및 그에 인접된 제 1 층간 절연막(2)상에 하부 금속 배선(4)을 형성한다. 그런 다음, 하부 금속 배선을 포함한 제 1 층간 절연막(2)상에 소정 두께의 제 2 층간 절연막(5)을 형성한 상태에서, 그 상부에 소자를 평탄화시키기 위한 SOG막 또는 BPSG막과 같은 평탄화 절연막(6)을 증착한다.Referring to FIG. 1B, an aluminum metal film or an aluminum alloy film is deposited on the entire upper portion and patterned to form a lower metal wire 4 on the contact hole and the first interlayer insulating film 2 adjacent thereto. Then, in the state where the second interlayer insulating film 5 having a predetermined thickness is formed on the first interlayer insulating film 2 including the lower metal wiring, a planarizing insulating film such as an SOG film or a BPSG film for planarizing the device thereon. (6) is deposited.

도 1c를 참조하면, 하부 금속 배선(4)상부의 평탄화 절연막(6) 및 제 2 층간 절연막(5)부분을 식각하여 상기 하부 금속 배선(4)을 노출시키는 비아홀(도시않됨)을 형성한 후, 비아홀 및 그에 인접된 평탄화 절연막(6)상에 상부 금속 배선(7)을 형성한다.Referring to FIG. 1C, after the planarization insulating layer 6 and the second interlayer insulating layer 5 are etched on the lower metal wiring 4 to form a via hole (not shown) exposing the lower metal wiring 4. The upper metal wiring 7 is formed on the via hole and the planarization insulating film 6 adjacent thereto.

그러나, 상기와 같은 종래 기술은 층간 절연막으로 이용되는 산화막의 유전상수 값이 4이상을 나타내기 때문에 소자가 미세화짐에 따라 야기될 수 있는 RC 지연 및 크로스토크 등에 의한 소자의 열화 현상으로 인하여 소자의 속도를 향상시키는데 한계가 있는 문제점이 있으며, 또한, 평탄화 절연막의 유전상수 값도 매우 높기 때문에 앞으로의 미세 크기를 갖는 소자에 상기와 같은 평탄화 저연막을 적용하기에는 어려운 문제점이 있었다.However, since the above-described conventional technology exhibits a dielectric constant value of 4 or more for the oxide film used as the interlayer insulating film, the device is deteriorated due to the deterioration of the device due to RC delay and crosstalk, which may be caused by the miniaturization of the device. There is a problem that there is a limit to improve the speed, and also because the dielectric constant value of the planarization insulating film is very high, it is difficult to apply the planarization low smoke film to the device having a fine size in the future.

따라서, 본 발명은 상·하부 금속 배선들 사이를 절연시키기 위한 층간 절연막을 형성하되, 동일면 상의 금속 배선들 사이에는 저유전상수 물질인 SOG막 또는 폴리머 계통의 막을 형성하고, 상·하 금속 배선들 사이에는 FSG막을 형성함으로써, 소자의 미세화에 따라 발생되는 RC 지연 및 크로스토크 등의 결함을 방지할 수 있는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention forms an interlayer insulating film for insulating between upper and lower metal wires, but forms an SOG film or a polymer-based film, which is a low dielectric constant material, between the metal wires on the same surface, and between the upper and lower metal wires. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing defects such as RC delay and crosstalk caused by miniaturization of the device by forming an FSG film.

제1a도 내지 제1c도는 종래 기술에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정 단면도.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

제2a도 내지 제2e도는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정 단면도.2A to 2E are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

11 : 반도체 기판 12 : 제 1 층간 절연막11 semiconductor substrate 12 first interlayer insulating film

13 : 텅스텐 플러그 14 : 알루미늄 합금막13: tungsten plug 14: aluminum alloy film

15 : 제 1 산화막 16 : 제 2 산화막15: first oxide film 16: second oxide film

17 : 저유전상수 물질 18 : FSG막17 low dielectric constant material 18 FSG film

상기와 같은 목적은, 콘택홀들을 갖는 제 1 층간 절연막이 형성된 반도체 기판을 제공하는 단계; 상기 콘택홀들 내에 각각 텅스텐 플러그를 형성하는 단계; 상기 텅스텐 플러그 및 제 1 층간 절연막 상에 알루미늄 합금막 및 소정 두께의 제 1 산화막을 적층하는 단계; 상기 텅스텐 플러그 및 그에 인접된 제 1 층간 절연막 상에만 제 1 산화막 및 알루미늄 합금막이 남도록 상기 제 1 산화막 및 알루미늄 합금막을 패터닝하는 단계; 상기 잔류된 제 1 산화막 및 알루미늄 합금막의 측부와 상기 제 1 층간 절연막 상에 소정 두께의 제 2 산화막을 형성하는 단계; 상기 제 2 산화막 상에 제 2 층간 절연막으로서 저유전상수 물질을 증착하는 단계; 상기 제 2 산화막을 식각 정지층으로 하여 상기 저유전상수 물질을 식각하는 단계; 및 상기 잔류된 제 2 산화막 및 저유전상수 물질 상에 제 3 층간 절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 본 발명에 따른 반도체 소자의 제조방법에 의하여 달성된다.The above object is to provide a semiconductor substrate having a first interlayer insulating film having contact holes; Forming a tungsten plug in each of the contact holes; Stacking an aluminum alloy film and a first oxide film having a predetermined thickness on the tungsten plug and the first interlayer insulating film; Patterning the first oxide film and the aluminum alloy film such that a first oxide film and an aluminum alloy film remain only on the tungsten plug and the first interlayer insulating film adjacent thereto; Forming a second oxide film having a predetermined thickness on the side portions of the remaining first oxide film and the aluminum alloy film and the first interlayer insulating film; Depositing a low dielectric constant material on the second oxide film as a second interlayer insulating film; Etching the low dielectric constant material by using the second oxide layer as an etch stop layer; And forming a third interlayer insulating film on the remaining second oxide film and the low dielectric constant material.

본 발명에 따르면, 상·하부 금속 배선 사이를 절연시키기 위한 층간 절연막을 형성하되, 저유전상수 값을 갖는 물질로 형성하여 RC 지연 등을 방지함으로써, 소자의 속도가 저하되는 것을 막을 수 있다.According to the present invention, an interlayer insulating film is formed to insulate between upper and lower metal wirings, but is formed of a material having a low dielectric constant value to prevent RC delay or the like, thereby preventing the device's speed from being lowered.

[실시예]EXAMPLE

이하, 도 2a 내지 도 2e를 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to FIGS. 2A to 2E.

도 2a를 참조하면, 접합 영역(도시않됨)이 구비된 반도체 기판(11)상에 제 1 층간 절연막(12)으로서 BPSG막 또는 PMD(Poly to Metal Dielectric)막을 증착한 상태에서 포토리소그라피 공정으로 제 1 층간 절연막(12)내에 접합 영역을 노출시키는 콘택홀들(도시않됨)을 형성한다. 그런 다음, 콘택홀이 매립되도록 전체 상부에 텅스텐 금속막을 증착한 후, 텅스텐 금속막을 에치백(Etch-Back)또는 CMP(Chemical Mechenical Polishing)공정을 통해 각각의 콘택홀 내에 텅스텐 플러그(13)를 형성한다.Referring to FIG. 2A, a BPSG film or a poly to metal dielectric (PMD) film is deposited as a first interlayer insulating film 12 on a semiconductor substrate 11 having a junction region (not shown). Contact holes (not shown) are formed in the interlayer insulating film 12 to expose the junction region. Then, a tungsten metal film is deposited on the entire upper portion so that the contact holes are filled, and then the tungsten metal film is formed in each contact hole through an etch-back or chemical mechanical polishing (CMP) process. do.

도 2b를 참조하면, 전체 상부에 5,000 내지 6,000Å두께로 구리 및 실리콘이 함유된 알루미늄 합금막(14)을 증착하고, 그 상부에 플라즈마 방식으로 800 내지 1,200Å두께의 제 1 산화막(15)을 증착한다.Referring to FIG. 2B, an aluminum alloy film 14 containing copper and silicon is deposited on the entire upper portion of 5,000 to 6,000 kPa, and the first oxide film 15 having a thickness of 800 to 1,200 kPa is deposited on the upper portion thereof in a plasma manner. Deposit.

도 2c를 참조하면, 제 1 산화막(15) 및 알루미늄 합금막(14)을 금속 배선의 형태로 패터닝한 후, 전체 상부에 플라즈마 방식으로 약 500 내지 700Å 정도의 두께를 갖는 제 2 산화막(16)을 옥시나이트라이드(oxynitride)막으로 증착하고, 그 상부에 제 2 층간 절연막으로서 8,000 내지 9,000Å 두께로 저유전상수 물질(17)을 코팅한 후, 열처리 공정으로 안정화시킨다. 여기서, 저유전상수 물질(17)로는 SOG 또는 폴리머 계통의 물질이 이용되며, 폴리머 계통의 물질로는 HSQ(Hydrogen Silses Quioxane)또는 MSQ(Methyl Silses Quioxane)가 사용된다. 한편, 알루미늄 합금막(14)의 상부 및 측부에는 제 1 및 제 2 산화막(15, 16)이 형성되어 있기 때문에 저유전상수 물질(17)에 의하여 상기 알루미늄 합금막(14)이 손상되는 것을 방지할 수 있다.Referring to FIG. 2C, after the first oxide film 15 and the aluminum alloy film 14 are patterned in the form of metal wirings, the second oxide film 16 having a thickness of about 500 to 700 kPa in a plasma manner over the entire upper portion is patterned. Is deposited with an oxynitride film, and a low dielectric constant material 17 is coated thereon as a second interlayer insulating film at a thickness of 8,000 to 9,000 kPa, and then stabilized by a heat treatment process. Here, the SOG or a polymer-based material is used as the low dielectric constant material 17, and the HSQ (Hydrogen Silses Quioxane) or MSQ (Methyl Silses Quioxane) is used as the material of the polymer-based material. Meanwhile, since the first and second oxide films 15 and 16 are formed on the upper and side portions of the aluminum alloy film 14, the aluminum alloy film 14 may be prevented from being damaged by the low dielectric constant material 17. Can be.

도 2d를 참조하면, CeO2슬러리를 이용한 CMP 공정으로 저유전상수 물질(17)을 식각한다. 이때, 제 1 및 2산화막(15, 16)과 저유전상수 물질(17)의 식각 선택비는 5 : 1 이상으로 한다. 이 결과, 알루미늄 합금막(14)상의 제 2 산화막(16) 및 제 1 산화막(15)은 거의 다 제거되며, 금속 배선들 사이에만 저유전상수 물질(17)이 남게된다.Referring to FIG. 2D, the low dielectric constant material 17 is etched by a CMP process using a CeO 2 slurry. In this case, the etching selectivity of the first and second oxide films 15 and 16 and the low dielectric constant material 17 may be 5: 1 or more. As a result, almost all of the second oxide film 16 and the first oxide film 15 on the aluminum alloy film 14 are removed, and the low dielectric constant material 17 remains only between the metal wires.

도 2e를 참조하면, 전체 상부에 제 3 층간 절연막으로서 FSG(F-doped Silicate Glass)막을 증착한다.Referring to FIG. 2E, an FSG (F-doped Silicate Glass) film is deposited as a third interlayer insulating film over the entire surface.

이후 도시되지는 않았지만, FSG막 내에 알루미늄 합금막을 노출시키는 비아홀을 형성한 상태에서, 상기와 마찬가지의 공정으로 진행하여 다층 금속 배선을 형성한다.Although not shown hereafter, in the state where the via hole exposing the aluminum alloy film is formed in the FSG film, the process is performed in the same manner as described above to form the multilayer metal wiring.

이상에서와 같이, 본 발명의 반도체 소자의 제조 방법은 상·하부 금속 배선들 사이를 절연시키기 위한 층간 절연막을 형성하되, 동일면 상의 금속 배선들 상이에는 저유전상수 물질인 SOG막 또는 폴리머 계통의 막을 형성하고, 상·하 금속 배선들 사이에는 FSG막을 형성함으로써, 소자의 미세화에 따라 발생되는 RC 지연 및 크로스토크 등의 결함을 방지할 수 있으며, 이에따라, 반도체 소자의 속도를 향상시킬 수 있다.As described above, the method of manufacturing a semiconductor device of the present invention forms an interlayer insulating film for insulating between upper and lower metal wirings, but forms an SOG film or a polymer-based film, which is a low dielectric constant material, between the metal wirings on the same surface. In addition, by forming the FSG film between the upper and lower metal lines, defects such as RC delay and crosstalk generated due to the miniaturization of the device can be prevented, thereby improving the speed of the semiconductor device.

한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것을 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, it will be understood that the following claims include all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (11)

콘택홀들을 갖는 제 1 층간 절연막이 형성된 반도체 기판을 제공하는 단계;Providing a semiconductor substrate having a first interlayer insulating film having contact holes; 상기 콘택홀들 내에 각각 텅스텐 플러그를 형성하는 단계;Forming a tungsten plug in each of the contact holes; 상기 텅스텐 플러그 및 제 1 층간 절연막 상에 알루미늄 합금막 및 소정 두께의 제 1 산화막을 적층하는 단계;Stacking an aluminum alloy film and a first oxide film having a predetermined thickness on the tungsten plug and the first interlayer insulating film; 상기 텅스텐 플러그 및 그에 인접된 제 1 층간 절연막 상에만 제 1 산화막 및 알루미늄 합금막이 남도록 상기 제 1 산화막 및 알루미늄 합금막을 패터닝하는 단계; 상기 잔류된 제 1 산화막 및 알루미늄 합금막의 측부와 상기 제 1 층간 절연막 상에 소정 두께의 제 2 산화막을 형성하는 단계; 상기 제 2 산화막 상에 제 2 층간 절연막으로서 저유전상수 물질을 증착하는 단계; 상기 제 2 산화막을 식각 정지층으로 하여 상기 저유전상수 물질을 식각하는 단계; 및 상기 잔류된 제 2 산화막 및 저유전상수 물질 상에 제 3 층간 절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Patterning the first oxide film and the aluminum alloy film such that a first oxide film and an aluminum alloy film remain only on the tungsten plug and the first interlayer insulating film adjacent thereto; Forming a second oxide film having a predetermined thickness on the side portions of the remaining first oxide film and the aluminum alloy film and the first interlayer insulating film; Depositing a low dielectric constant material on the second oxide film as a second interlayer insulating film; Etching the low dielectric constant material by using the second oxide layer as an etch stop layer; And forming a third interlayer insulating film on the remaining second oxide film and the low dielectric constant material. 제1항에 있어서, 상기 알루미늄 합금막은 5,000 내지 6000Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the aluminum alloy film is formed to have a thickness of 5,000 to 6000 kPa. 제1항에 있어서, 상기 제 1 및 제 2 산화막 플라즈마 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the first and second oxide film plasma are formed. 제1항 또는 제3항에 있어서, 상기 제 1 산화막은 800 내지 1,200Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the first oxide film is formed to a thickness of 800 to 1,200 Å. 제1항 또는 제3항에 있어서, 상기 제 2 산화막은 500 내지 700Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1 or 3, wherein the second oxide film is formed to a thickness of 500 to 700 GPa. 제1항에 있어서, 상기 저유전상수 물질은 SOG 또는 폴리머 계통의 물질인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the low dielectric constant material is an SOG or polymer-based material. 제6항에 있어서, 상기 폴리머 계통의 물질은 HSQ(Hydrogen Silses Quioxane)또는 MSQ(Methyl Silses Quioxane)인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 6, wherein the polymer-based material is HSQ (Hydrogen Silses Quioxane) or MSQ (Methyl Silses Quioxane). 제1항 또는 제6항에 있어서, 상기 저유전상수 물질은 8,000 내지 9,000Å 두께로 증착하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the low dielectric constant material is deposited to a thickness of 8,000 to 9,000 kPa. 제1항에 있어서, 상기 저유전상수 물질과 제 2 산화막의 식각 공정은 CeO2슬러리를 이용한 CMP 공정으로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the etching of the low dielectric constant material and the second oxide layer is performed by a CMP process using a CeO 2 slurry. 제9항에 있어서, 상기 CMP 공정시에 제 2 산화막과 저유전상수 물질은 5 : 1이상의 식각 선택비로 식각하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 9, wherein the second oxide layer and the low dielectric constant material are etched at an etching selectivity of 5: 1 or more during the CMP process. 제1항에 있어서, 상기 제 3 층간 절연막은 FSG(F-doped Silicate Glass) 인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the third interlayer insulating layer is FSG (F-doped Silicate Glass).
KR1019970028816A 1997-06-28 1997-06-28 Method of fabricating semiconductor device KR100244713B1 (en)

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