KR0165379B1 - Layer wiring method of semiconductor device - Google Patents

Abstract

An interlayer connection method of a semiconductor device for forming a contact for electrical contact between a metal layer and a substrate, or a via contact for electrical contact between a metal layer and another metal layer is described.

A first step of forming an interlayer insulating layer on the lower conductive layer, a second step of forming an opening exposing a part surface of the lower conductive layer by partially etching the interlayer insulating layer, and fusing the opening with tungsten And a fourth step of flowing aluminum or an aluminum alloy on the third step and the resultant entire surface.

Therefore, a flat metal layer can be formed without the step of paying attention to contact holes or via holes, and voids can be prevented by filling the holes completely.

Description

Indirect Method of Layer in Semiconductor Device

1 is a cross-sectional view illustrating a method for connecting an interlayer of a semiconductor device according to a conventional method.

2A and 2B are cross-sectional views for explaining the interlayer connection method of a semiconductor device by another conventional method.

3 is a cross-sectional view for explaining a method of connecting a semiconductor device according to another conventional method.

4A to 4D are cross-sectional views illustrating an interlayer connection method of a semiconductor device in accordance with a first embodiment of the present invention.

5 is a cross-sectional view for explaining the interlayer connection method of the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining the interlayer connection method of the semiconductor device according to the third embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an interlayer connection method of a semiconductor device for electrical contact between a metal layer and a substrate, or between a metal layer and another metal layer.

An integrated circuit has a conductive layer electrically separated by insulating layers formed on a semiconductor substrate. The upper metal layer must be in electrical contact with the substrate, or with one or more conductive layers, and the integrated circuit will fail unless proper electrical contact is made.

A common method of making electrical contact to a substrate or conductive layer is to make holes in the insulating layer or films formed on the substrate to expose the substrate region and then fill the holes by depositing a metal conductive material.

However, this technique can easily provide electrical contact to the substrate if the diameter of the hole is large enough, but if the width of the hole is too small, the conductive material will not reach the substrate, and electrical contact between the conductive layer and the substrate will not be established. Not done.

With the integration of semiconductor devices, the width of the metal wirings and the spacing between the wirings are also narrowed, and thus the sizes of the contact holes and the via holes are also reduced. Since the line width of 1 탆 or less is required in the manufacturing process of the integrated circuit, the size of the contact hole is extremely small, so that the connection between the semiconductor substrate and the conductive layer and the connection between the upper metal layer and the lower metal layer are very difficult.

While the width and spacing of the metal wirings and the size of the contacts or vias are reduced, the inter-layer dielectric (hereinafter referred to as PMD) between the gate and the metal layer and the intermetal dielectric (hereinafter referred to as PMD) The thickness of the IMD) is not lowered, but rather thickened to reduce the parasitic capacity. Therefore, the aspect ratio (the thickness of the interlayer insulating film / the size of the contact hole represents the degree of difficulty of contact filling, and the larger the value becomes, the more difficult the contact filling is).

Overcoming such a large aspect ratio, a method for forming an interlayer connection has been proposed, which is a method of filling a hole with a flow metal and using a mixture of a plug and a metal sputter. .

1 is a cross-sectional view for explaining a conventional interlayer connection method using an aluminum flow.

Referring to FIG. 1, a semiconductor substrate having an interlayer insulating film 20 and a contact hole formed therein, the temperature in the chamber is about 560 ° C, and the chuck temperature is about 490 ° C. By depositing the aluminum 40 as a whole, aluminum is deposited on the surface of the interlayer insulating film 20 and inside the contact hole to form an electrical connection with the substrate.

However, since the size of the contact hole is sub-micron, aluminum does not completely close the contact hole. As a result, some of the conductive layers become thinner on the sidewalls of the contact holes, causing the blocking of electrical passages, or conversely, transient concentrations.

2A and 2B are cross-sectional views illustrating a conventional interlayer connection method using a mixture of a floc and a sputter.

Referring to FIG. 2A, tungsten is deposited on the entire surface of the semiconductor substrate on which the insulating layer 20 and the contact hole are formed, followed by etching back on the entire surface of the resultant to form a floc 30 in the contact hole.

At this time, as the inside of the contact hole is filled with tungsten, some of the tungsten remains on the sidewall of the contact hole. Therefore, during the tungsten etchback process, overetch is performed to remove residual tungsten on the sidewall of the contact hole, in which the remaining tungsten remaining on the contacthole sidewall is removed and the tungsten filled with the floc in the contacthole is removed. A portion of is also removed, leaving the contact hole completely unfilled.

When sputtering a metal, such as aluminum (Al), on the entire surface of the resultant tungsten floc, the unfilled contact hole makes the aluminum 40 coating profile equal to that of FIG.

Referring to FIG. 2B, when the interlayer insulating film 50 is deposited on the entire surface of the aluminum 40 sputtered, voids are generated due to the incidence generated in FIG. 2A, causing leakage current, and the reliability of the semiconductor device. Greatly decreases.

3 is a cross sectional view of a stacked via contact, in which reference numerals 20a and 20b denote interlayer insulating films in a multilayer wiring structure, 30a and 30b denote flocks, and 40a and 40b denote aluminum interconnect layers, respectively. Indicates.

Referring to FIG. 3, it can be seen that voids are caused more severely in the case of a multilayer wiring structure. In Figs. 1 to 3, reference numeral 10 denotes a semiconductor substrate, and 12 denotes a field oxide film.

Accordingly, it is an object of the present invention to provide an interlayer connection method of a semiconductor device in which an ear is not generated around a contact hole or a via hole.

Another object of the present invention is to provide an interlayer connection method of a semiconductor device which can prevent voids by completely filling contact holes.

The interlayer connection method of a semiconductor device according to the present invention for achieving the above object,

A first step of forming an interlayer insulating layer covering a lower conductive layer: A second step of forming a contact hole exposing a part surface of the lower conductive layer by partially etching the interlayer insulating layer: Flushing the opening with tungsten And a fourth step of forming an upper doser layer connected to the lower conductive layer by flowing aluminum or an aluminum alloy over the entire surface of the resultant.

The lower conductive layer represents a conductive substrate made of a semiconductor substrate or a metal material doped with impurities.

Here, when the lower conductive layer is a semiconductor substrate doped with an impurity, the first step includes depositing an oxide film on the lower conductive layer and depositing BPSG (Boron-Phosphorus Silicate Glass) on the oxide film. And the process for flattening the resultant.

In addition, when the lower conductive layer is a metal, the first process may include depositing plasma enhanced tetraethyl orthosilicate (PE-TEOS) on the lower conductive layer, and coating spin-on glass (SOG) on the PE-TEOS. Process to re-deposit PE-TEOS on the OSG and to planarize the resultant.

After the second process, the method may further include forming a barrier layer of titanium (Ti) or titanium nitride (Tin) in the opening.

In addition, the third process includes a process of depositing tungsten on the entire surface of the resultant in which the opening is formed, and the process of etching the tungsten by RF sputter etching.

The method may further include forming a capping layer using titanium nitride on the aluminum or the aluminum alloy after the fourth process.

The present invention uses a tungsten to form a floc in the contact hole, and then flows aluminum or aluminum alloy to prevent the occurrence of incidence around the contact hole or via hole, and completely fills the contact hole or via hole, thereby improving the characteristics of the device. Can be improved.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4A to 6 are cross-sectional views for explaining the interlayer connection method according to the present invention. FIGS. 4A to 4D are a first embodiment of the interlayer connection method according to the present invention, and FIG. 5 is a second embodiment. For example, FIG. 6 is a cross-sectional view respectively shown to describe the third embodiment. In the drawings to which reference is made, the same reference numerals as those in FIGS. 1 to 3 denote the same parts.

First embodiment

The first embodiment of the present invention proceeds to (a) contact hole forming step, (b) tungsten floc forming step, and (c) aluminum flow step.

FIG. 4A shows a process of forming a unit element, which is a first step of forming a field oxide film 12 which defines a semiconductor substrate 10 into an active region and an inactive region, and a source region in the active region of the semiconductor substrate. 14), and proceeds to the second process of forming a transistor consisting of the drain region 16 and the gate electrode 18.

4B illustrates a process of forming the interlayer insulating layer 20 and the contact hole 22, which forms the interlayer insulating layer 20 on the resultant product on which the unit devices are formed. The first step of forming the interlayer insulating layer 20 on the resultant, the second step of forming a photoresist pattern (not shown) for forming the contact hole, and the third step of forming the contact hole 22. do.

Specifically, in the first process, in order to electrically separate a gate electrode, a source region / drain region, or another lower conductive layer from a metal layer to be formed later, a high temperature oxide film (HTO) ) And depositing a silicon oxide film such as a low temperature oxide film (LTO) to a thickness of about 2,500 kPa, depositing a BPSG to a thickness of about 14,000 kPa on the silicon oxide film, and chemically-physically polishing the BPSG ( Chemical Mechanical Polishing (hereinafter referred to as CMP) method is used to planarize to form an interlayer insulating layer 20 made of a silicon oxide film and BPSG.

In the second process of forming a photoresist pattern (not shown) for contact hole form, a photoresist such as, for example, a photoresist is applied on the interlayer insulating layer 20, and then a photolithography process is performed to form a contact hole form. And forming a contact hole 22 by anisotropically etching the interlayer insulating layer 20 by using the photoresist pattern as an etch mask. Proceed.

FIG. 4C illustrates a co-deposition for forming the fruc 30, wherein the first step of depositing tungsten on the resultant formed contact hole, the deposited tungsten is etched back to the contact hole (refer to reference numeral 22 of FIG. 4B). By allowing tungsten to remain inside only, a second process of forming the tungsten floc 30 and a third process of etching the tungsten by an RF sputter etching method are performed.

The tungsten is deposited to a thickness of about 10,000 mm 3, and the tungsten is sufficiently etched back to remove residual tungsten so that the tungsten on the top of the contact hole is overetched.

The RF sputter is performed to improve adhesion between tungsten and aluminum to be laminated in a later step.

4d illustrates a process of depositing aluminum or an aluminum alloy to form the flow metal layer 40. According to a preferred embodiment of the present invention, the flow metal is 0.5% copper (Cu) and 0.25% silicon ( Si) is formed from aluminum. The temperature in the chamber is about 560 ° C, and the temperature of the chuck, that is, the temperature of the substrate, is about 490 ° C.

The interlayer connection method according to the first embodiment of the present invention described above can form a flat metal layer because the contact hole is completely filled with a conductive material and thus does not form a step around the contact hole.

Second embodiment

FIG. 5 is a cross-sectional view illustrating a method for connecting an interlayer of a semiconductor device in accordance with a second embodiment of the present invention, and relates to an interlayer connecting method when a multilayer metal layer is formed, that is, when the lower conductive layer is a metal layer. .

Referring to FIG. 5, a first process of forming the interlayer insulating layer 20a on the lower metal layer, a second process of forming the via hole, a third process of removing the tungsten floc and a fourth process of forming the flow metal layer Proceeds to.

Specifically, in the first process, the processes from FIGS. 4A to 4D are sequentially performed to form the flat metal layer 40, and then 4,000 PE-TEOS is formed on the entire surface of the resultant metal layer 40. Process to deposit SOG on top of it, process to deposit SOG on top of about 2,000 ,, coating process on SOG twice on thickness of about 2,000Å, PE-TEOS on top of about 5,000Å The process of depositing the CVD process, the process of flattening by performing the CMP process, and again the process of depositing PE-TEOS with a thickness of about 6,000Å.

At this time, the thickness of the oxide film remaining on the metal layer 40 is adjusted to be about 3,000 Pa, which is a thickness at which SOG on the metal layer is removed. In this way, the total circumference of the interlayer insulating layer is about 9,000 mW.

The second process includes forming a photoresist pattern for forming a via hole on the interlayer insulating layer 20a, and forming a via hole by anisotropically etching the interlayer dielectric with the photoresist pattern as an etch mask.

Subsequently, the RF sputtering process, the process of forming the second tungsten floc, and the process of forming the flow metal layer are performed in the same manner as in the first embodiment of the present invention.

According to the second embodiment of the present invention, even in the connection of the double metal layer, the floc is formed first, and then the metal flows so that the contact hole can be completely filled without having an indentation around the contact hole.

Although the interlayer connection method of the double metal layer according to the present invention has been described, it is well known that the present invention can be applied to contact formation of triple or more multilayer metal layers.

Third embodiment

FIG. 6 is a cross-sectional view for explaining the interlayer connection method of the semiconductor device according to the third embodiment of the present invention, in which a barrier layer is formed inside the contact hole and a capping layer is formed on the flow metal layer. To a method of forming an interlayer connection.

Referring to FIG. 6, barrier layers 60 and 70 may be formed on the resulting contact hole after forming a contact hole exposing a part of the lower conductive layer in the same manner as in the first and second embodiments of the present invention. Forming a floc, forming a floc 30 on the barrier layers 60 and 70, forming a flow metal layer 40 on the resultant floc and capping layer 80 on the flow metal layer. ) To the process of forming.

Specifically, the process of forming the barrier layer (60, 70), to improve the adhesion of the metal layer to be subsequently laminated on the resultant, the contact hole is formed, the impurity region (source or drain) of the metal layer and the lower, or In order to improve the nick connection of the gate electrode, for example, titanium (Ti) is deposited to a thickness of about 600 Å to form the first material layer 60, and the diffusion of impurities on the first material layer 60 or In order to prevent diffusion of silicon, for example, titanium nitride is deposited to a thickness of about 600 mm 3 to form the second material layer 70.

The process of forming the capping layer 80 is performed by depositing, for example, a titanium nitride film on the flow metal layer 40 to a thickness of about 250 GPa. The other steps proceed in the same manner as in the first or second embodiment of the present invention.

According to the third embodiment of the present invention, by forming a barrier layer in the contact hole before forming the floc, the adhesion of tungsten for forming the floc is improved, and the diffusion of impurities when flowing aluminum or aluminum alloy is prevented. Can be.

According to the interlayer connection method of a semiconductor device according to the present invention described above, a step is not made after forming a metal layer so as not to generate an abrasion around the contact hole or the via hole, and the void is formed by completely filling the contact hole or the via hole with a conductive material. Can be prevented.

The present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art.

Claims (10)

A first step of forming an interlayer insulating layer covering a lower conductive layer: A second step of forming a contact hole exposing a part surface of the lower conductive layer by partially etching the interlayer insulating layer: Flush the opening with tungsten And a fourth step of forming an upper conductive layer connected to the lower conductive layer by flowing aluminum or an aluminum alloy on the entire surface of the resultant. The method of claim 1, wherein the lower conductive layer is a semiconductor substrate doped with impurities. 2. The interlayer of a semiconductor device according to claim 1, wherein said first step includes a step of depositing an oxide film covering a lower conductive layer, a step of depositing BPSG on said oxide film, and a step of leveling off the hot water. How to connect. The method of claim 1, wherein the lower conductive layer is a conductive layer made of a metal material. The method of claim 1, wherein the first process comprises depositing PE-TEOS on a lower conductive layer, coating SOG on the PE-TEOS, re-depositing PE-TEOS on the SOG, and The interlayer connection method of a semiconductor device, characterized in that the process proceeds to the planarization of the result. The method of claim 1, further comprising: forming a barrier layer in the opening after the second step. 7. The method of claim 6, wherein the barrier layer is formed of titanium or titanium nitride. The method of claim 1, wherein the third process comprises depositing tungsten on the entire surface of the resultant product in which the opening is formed, and etching the tungsten by RF sputter etching. The method of claim 1, further comprising depositing a capping metal on the aluminum or the aluminum alloy after the fourth process. 10. The method of claim 9, wherein titanium nitride is used as the capping metal.