KR100427539B1 - Method of forming multilayer metal of semiconductor device using improved intermetal dielectric - Google Patents

Method of forming multilayer metal of semiconductor device using improved intermetal dielectric Download PDF

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KR100427539B1
KR100427539B1 KR1019960011720A KR19960011720A KR100427539B1 KR 100427539 B1 KR100427539 B1 KR 100427539B1 KR 1019960011720 A KR1019960011720 A KR 1019960011720A KR 19960011720 A KR19960011720 A KR 19960011720A KR 100427539 B1 KR100427539 B1 KR 100427539B1
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lower metal
metal layer
forming
layer
semiconductor device
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KR1019960011720A
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KR970072085A (en
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김영우
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method of forming a multilayer metal of a semiconductor device is provided to improve the insulation and flatness of an intermetal dielectric by performing repeatedly an oxide depositing process and an etching process until a space between metal films is completely filled with oxide. CONSTITUTION: A plurality of metal lines(13) are formed on a silicon substrate(11) via an insulating layer(12). An oxide layer(14) is deposited along the upper surface of the resultant structure. A dry-etching process is mainly performed for the oxide layer on each metal line. A space between the metal lines is completely filled with oxide by performing repeatedly the oxide depositing process and the dry-etching process.

Description

반도체 소자의 다중 금속층 형성 방법Method of forming multiple metal layers in semiconductor devices

본 발명은 반도체 소자의 다중 금속층 형성 방법에 관한 것으로, 특히 금속층간 절연막의 절연 및 평탄도를 향상시킬 수 있도록 한 반도체 소자의 다중 금속층 형성 방법에 관한 것이다.The present invention relates to a method for forming a multi-metal layer of a semiconductor device, and more particularly, to a method for forming a multi-metal layer of a semiconductor device to improve the insulation and flatness of the inter-metal insulating film.

일반적으로 반도체 소자의 제조 공정에서 금속층은 이중 또는 다중 구조로 형성되며, 금속층간에는 절연 및 평탄화를 위하여 금속층간 절연막을 형성한다. 그런데 반도체 소자가 고집적화됨에 따라 금속배선의 폭이 미세화되고 금속배선간의 거리가 감소되기 때문에 금속배선과 금속배선 그리고 금속층간의 절연은 더욱 중요해진다. 그러면 종래 반도체 소자의 다중 금속층 형성 방법을 제 1A 및 제 1B 도를 통해 설명하면 다음과 같다.In general, in the process of manufacturing a semiconductor device, the metal layer is formed in a double or multiple structure, and an intermetallic insulating film is formed between the metal layers for insulation and planarization. However, as semiconductor devices are highly integrated, insulation between metal interconnections, metal interconnections, and metal layers becomes more important because the width of metal interconnections becomes smaller and the distance between metal interconnections decreases. A method of forming a multi-metal layer of a conventional semiconductor device will now be described with reference to FIGS. 1A and 1B.

제 1A 및 제 1B 도는 종래 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도로서,1A and 1B are cross-sectional views of a device for explaining a method of forming a multi-metal layer of a conventional semiconductor device.

제 1A 도는 절연층(2)이 형성된 실리콘 기판(1)상에 하부 금속층을 5000 내지 10,000 Å 두께로 형성한 후 상기 하부 금속층을 패터닝하여 하부 금속배선(3)을 형성하고, 전체 상부면에 제 1 금속층간 절연막(4), SOG(Spin-On-Glass)막(5) 및 제 2 금속층간 절연막(6)을 순차적으로 형성한 상태의 단면도이다. 그런데 상기 하부 금속배선(3)의 단차로 인하여 표면의 평탄도가 저하되며, 상기 하부 금속배선(3)간의 거리가 매우 미세하기 때문에 상기 SOG막(5)의 매립 상태가 불량하여 상기 하부 금속배선(3)간의 공간에 보이드(7)가 발생된다.The lower metal layer is formed on the silicon substrate 1 having the insulating layer 2 formed thereon in a thickness of 5000 to 10,000 Å, and then the lower metal layer is patterned to form the lower metal wiring 3, 1 is a cross-sectional view of a state in which a first interlayer insulating film 4, a spin-on-glass film 5, and a second interlayer insulating film 6 are sequentially formed. However, the flatness of the surface is lowered due to the step difference of the lower metal wiring 3, and the distance between the lower metal wiring 3 is very small, so that the embedded state of the SOG film 5 is poor and the lower metal wiring is poor. The void 7 is generated in the space between (3).

제 1B 도는 상기 하부 금속배선(3)의 표면이 노출되도록 상기 제 2 금속층간 절연막(6), SOG막(5) 및 제 1 금속층간 절연막(4)을 순차적으로 패터닝하여 콘택 홀(Contact hole)을 형성한 후 상기 콘택 홀이 매립되도록 전체 상부면에 금속을 증착하여 상부 금속층(9)을 형성한 상태의 단면도인데, 상기 상부 금속층(9) 형성시 상기 SOG막(5)으로부터 방출되는 수분(H2O)으로 인하여 상기 SOG막(5)과 제 2 금속층간 절연막(6)의 사이에는 거품 효과(Bubble effect)로 인한 결함(8)이 발생되고, 상기 콘택 홀내에서는 상기 SOG막(5)의 노출된 부분이 손실되는 보윙(Bowing) 현상이 발생된다. 그리고 상기 결함(8) 및 보윙 현상은 상기 하부 금속배선(3)간의 절연도 및 상기 하부 금속 배선(3) 및 상부 금속층(9)간의 절연도를 저하시켜 소자의 전기적 특성이 저하되는 원인으로 작용한다.In FIG. 1B, the second interlayer insulating film 6, the SOG film 5, and the first interlayer insulating film 4 are sequentially patterned so that the surface of the lower metal wiring 3 is exposed to a contact hole. Is a cross-sectional view of a state in which the upper metal layer 9 is formed by depositing metal on the entire upper surface so that the contact hole is buried, and water discharged from the SOG film 5 when the upper metal layer 9 is formed ( H 2 O) causes a defect 8 due to a bubble effect between the SOG film 5 and the second intermetallic insulating film 6, and in the contact hole, the SOG film 5. The bowing phenomenon occurs in which the exposed part of the body is lost. In addition, the defects 8 and the bowing phenomenon lower the insulation between the lower metal interconnection 3 and the insulation between the lower metal interconnection 3 and the upper metal layer 9, thereby acting as a cause of deterioration of the electrical characteristics of the device. do.

따라서 본 발명은 하부 금속배선을 형성한 후 상기 하부 금속배선간의 공간이 완전히 매립되는 시점까지 산화막 증착 및 식각 공정을 반복 실시하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 다중 금속층 형성 방법을 제공하는 데 그 목적이 있다.Accordingly, the present invention provides a method for forming a multi-metal layer of a semiconductor device that can solve the above-mentioned disadvantages by repeatedly performing the oxide film deposition and etching process after forming the lower metal wiring until the space between the lower metal wiring is completely filled. Its purpose is to.

상기한 목적을 달성하기 위한 본 발명은 절연층이 형성된 실리콘 기판상에 하부 금속층을 형성한 후 상기 하부 금속층을 패터닝하여 하부 금속배선을 형성하는 제 1 단계와, 상기 제 1 단계로부터 전체 상부면에 산화막을 증착하는 제 2 단계와, 상기 제 2 단계로부터 상기 하부 금속배선상에 증착된 산화막의 식각비가 상기 하부 금속배선의 측벽에 증착된 산화막의 식각비보다 높은 식각 방법을 이용하여 상기 산화막을 소정 두께 식각하는 제 3 단계와, 상기 제 3 단계로부터 상기 하부 금속배선간의 사이에 상기 산화막이 완전히 매립되는 동시에 표면이 평탄화되도록 상기 제 2 및 제 3 단계의 공정을 순차적으로 반복 실시하는 제 4 단계와, 상기 제 4 단계로부터 상기 하부 금속배선의 표면이 노출되도록 상기 산화막을 패터닝하여 콘택 홀을 형성한 후 상기 콘택 홀이 매립되도록 전체 상부면에 금속을 증착하여 상부 금속층을 형성하는 제 5 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is a first step of forming a lower metal layer on the silicon substrate on which the insulating layer is formed and then patterning the lower metal layer, and from the first step to the entire upper surface The oxide film may be formed using an etching method in which an etch ratio of an oxide film deposited on the lower metal wiring from the second step is higher than an etching ratio of an oxide film deposited on the sidewall of the lower metal wiring. A fourth step of sequentially repeating the processes of the second and third steps so that the oxide film is completely filled between the third step of thickness etching and the lower metal wiring from the third step, and the surface is planarized. And forming a contact hole by patterning the oxide layer so that the surface of the lower metal wiring is exposed from the fourth step. Depositing a metal on the entire upper surface to the buried contact hole to the group characterized by comprising a fifth step of forming the top metal layer.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제 2A 내지 제 2E 도는 본 발명에 따른 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도로서,2A through 2E are cross-sectional views of devices for explaining a method of forming a multi-metal layer of a semiconductor device according to the present invention.

제 2A 도는 절연층(12)이 형성된 실리콘 기판(11)상에 하부 금속층을 5000 내지 10,000Å 두께로 형성한 후 상기 하부 금속층을 패터닝하여 하부 금속배선(13)을 형성한 상태의 단면도이고, 제 2B 도는 전체 상부면에 산화막(14)을 증착한 상태의 단면도로서, 이때 상기 하부 금속배선(13)상에 증착되는 산화막(14)의 두께(A)와 상기 하부 금속배선(13)의 측벽에 증착되는 산화막(14)의 두께(B) 비율(A : B)은 1 : 0.6 내지 0.8 정도가 되도록 한다.2A is a cross-sectional view of a lower metal layer 13 formed by forming a lower metal layer to a thickness of 5000 to 10,000 Å on a silicon substrate 11 on which the insulating layer 12 is formed, and then patterning the lower metal layer. 2B is a cross-sectional view of the oxide film 14 deposited on the entire upper surface, wherein the thickness A of the oxide film 14 deposited on the lower metal wiring 13 and the sidewalls of the lower metal wiring 13 are shown. The thickness B ratio (A: B) of the oxide film 14 to be deposited is about 1: 0.6 to about 0.8.

제 2C 도는 상기 하부 금속배선(13)상에 잔류되는 산화막(14)의 두께(A') 및 상기 하부 금속배선(13)의 측벽에 잔류되는 산화막(14)의 두께(B') 비율(A' : B')이 1 : 0.8 내지 0.95가 되는 시점까지 상기 산화막(14)을 식각한 상태의 단면도로써, 상기 식각 공정은 CF4가스를 이용한 산소(O2) 플라즈마(Plasma) 식각 방법으로 실시한다.2C shows a thickness A 'of the oxide film 14 remaining on the lower metal wiring 13 and a thickness B' ratio of the oxide film 14 remaining on the sidewall of the lower metal wiring 13. ': B') is a cross-sectional view of the oxide film 14 being etched until 1: 0.8 to 0.95, wherein the etching process is performed by an oxygen (O 2 ) plasma etching method using CF 4 gas. do.

제 2D 도는 상기 제 2B 및 제 2C 도의 설명에서 실시한 산화막(14) 증착 및 식각 공정을 순차적으로 반복 실시하므로써 상기 하부 금속배선(13)간의 공간에 상기 산화막(14)이 완전히 매립되는 동시에 표면이 평탄화된 상태의 단면도이다.In FIG. 2D, the oxide film 14 is completely embedded in the space between the lower metal wirings 13 by sequentially repeating the oxide film 14 deposition and etching processes performed in the description of FIGS. 2B and 2C. It is a cross-sectional view of the state.

제 2E 도는 상기 하부 금속배선(13)의 표면이 노출되도록 상기 산화막(14)을 패터닝하여 콘택 홀을 형성한 후 상기 콘택 홀이 매립되도록 전체 상부면에 금속을 증착하여 상부 금속층(15)을 형성한 상태의 단면도이다.In FIG. 2E, the oxide layer 14 is patterned to expose the surface of the lower metal wiring 13 to form contact holes, and then metal is deposited on the entire upper surface to fill the contact holes to form the upper metal layer 15. It is sectional view of one state.

상술한 바와 같이 본 발명에 의하면 하부 금속배선을 형성한 후 상기 하부 금속배선간의 공간이 완전히 매립되는 시점까지 산화막 증착 및 식각 공정을 반복 실시하므로써 금속배선과 금속배선 그리고 금속층간의 절연 및 표면의 평탄도가 향상되어 소자의 전기적 특성이 향상된다. 또한 수분의 방출로 인한 불량이 야기되는 SOG막을 사용하지 않으므로 소자의 수율이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, after the lower metal wiring is formed, the oxide film deposition and etching process are repeatedly performed until the space between the lower metal wiring is completely filled, thereby insulating the surface of the metal wiring and the metal wiring and the metal layer, and flattening the surface The degree is improved to improve the electrical characteristics of the device. In addition, there is an excellent effect that the yield of the device can be improved because the SOG film does not use a defect caused by the release of moisture.

제 1A 및 제 1B 도는 종래 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a method of forming a multi-metal layer of a conventional semiconductor device.

제 2A 내지 제 2E 도는 본 발명에 따른 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도.2A to 2E are cross-sectional views of a device for explaining a method of forming a multi-metal layer of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 및 11: 실리콘 기판 2 및 12: 절연층1 and 11: silicon substrate 2 and 12: insulating layer

3 및 13: 하부 금속배선 4: 제 1 금속층간 절연막3 and 13: lower metallization 4: first interlayer insulating film

5: SOG막 6: 제 2 금속층간 절연막5: SOG film 6: second interlayer insulating film

7: 보이드 8: 결함7: void 8: defect

9 및 15: 제 2 금속층 14: 산화막9 and 15: second metal layer 14: oxide film

Claims (6)

(a) 절연층이 형성된 실리콘 기판 상에 하부 금속층을 형성한 후 상기 하부 금속층을 패터닝하여 하부 금속배선을 형성하는 단계;(a) forming a lower metal layer on the silicon substrate on which the insulating layer is formed, and then patterning the lower metal layer to form a lower metal wiring; (b) 전체 구조 상부의 단차를 따라 산화막을 증착하되, 상기 산화막이 상기 하부 금속 배선의 측벽보다 상부에서 보다 더 두껍게 증착되는 단계;(b) depositing an oxide film along a step above the entire structure, wherein the oxide film is deposited thicker at the top than the sidewall of the lower metal interconnection; (c) 상기 하부 금속 배선 상부의 산화막이 보다 더 식각되도록 건식 식각 방식으로 상기 산화막을 식각하여, 상기 하부 금속 배선 측벽의 산화막을 보다 더 두껍게 잔류시키는 단계;(c) etching the oxide layer by a dry etching method so that the oxide layer on the lower metal interconnection is more etched, and leaving the oxide layer on the sidewall of the lower metal interconnection thicker; (d) 상기 산화막이 수평방향으로 증착되도록 상기 (b) 단계 및 상기 (c) 단계를 반복 실시하여 상기 하부 금속배선 사이를 상기 산화막으로 완전히 매립하는 단계; 및(d) repeating the steps (b) and (c) so that the oxide film is deposited in a horizontal direction to completely fill the oxide film between the lower metal wires; And (e) 상기 하부 금속배선의 표면이 노출되도록 상기 산화막을 패터닝하여 콘택 홀을 형성한 후, 상기 콘택홀이 매립되도록 전체 상부면에 금속을 증착하여 상부 금속층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성방법.(e) forming a contact hole by patterning the oxide layer so that the surface of the lower metal wiring is exposed, and then depositing a metal on the entire upper surface to fill the contact hole, thereby forming an upper metal layer. A method of forming a multi-metal layer of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 하부 금속층은 5000 내지 10,000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성방법.The lower metal layer is a method of forming a multiple metal layer of a semiconductor device, characterized in that formed in a thickness of 5000 to 10,000Å. 제 1 항에 있어서,The method of claim 1, 사익 (b) 단계에서 상기 산화막 증착공정 시, 상기 하부금속배선상에 증착되는 두께와 상기 하부 금속배선의 측벽에 증착되는 두께 비율은 1:0.6 내지 0.8이 되도록 하는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성방법.In the step (b), the ratio of the thickness deposited on the lower metal interconnection and the thickness deposited on the sidewall of the lower metal interconnection is 1: 0.6 to 0.8 in the oxide film deposition process. Metal layer formation method. 제 1 항에 있어서,The method of claim 1, 상기 (c) 단계에서 상기 산화막 식각공정시, 상기 하부 금속배선상에 잔류되는 두께 및 상기 하부 금속배선의 측벽에 잔류되는 두께 비율은 1:0.8 내지 0.95가 되도록 하는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성방법.In the step (c), the ratio of the thickness remaining on the lower metal interconnection and the thickness remaining on the sidewall of the lower metal interconnection may be 1: 0.8 to 0.95 during the oxide film etching process. Metal layer formation method. 제 1 항에 있어서,The method of claim 1, 상기 (c) 단계에서 상기 건식 식각공정은 산소 플라즈마 식각방법으로 실시되는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성방법.In the step (c), the dry etching process is a method of forming a multiple metal layer of a semiconductor device, characterized in that carried out by an oxygen plasma etching method. 제 5 항에 있어서,The method of claim 5, wherein 상기 산소 플라즈마 식각방법은 CF4가스를 이용하는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성방법.The oxygen plasma etching method is a method of forming a multi-metal layer of the semiconductor device, characterized in that using the CF 4 gas.
KR1019960011720A 1996-04-18 1996-04-18 Method of forming multilayer metal of semiconductor device using improved intermetal dielectric KR100427539B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920010892A (en) * 1990-11-30 1992-06-27 김광호 Surface flattening method of semiconductor device
KR950009930A (en) * 1993-09-25 1995-04-26 김주용 Metal wiring formation method of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920010892A (en) * 1990-11-30 1992-06-27 김광호 Surface flattening method of semiconductor device
KR950009930A (en) * 1993-09-25 1995-04-26 김주용 Metal wiring formation method of semiconductor device

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