KR970072085A - Method for forming multiple metal layers of semiconductor devices - Google Patents

Method for forming multiple metal layers of semiconductor devices Download PDF

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Publication number
KR970072085A
KR970072085A KR1019960011720A KR19960011720A KR970072085A KR 970072085 A KR970072085 A KR 970072085A KR 1019960011720 A KR1019960011720 A KR 1019960011720A KR 19960011720 A KR19960011720 A KR 19960011720A KR 970072085 A KR970072085 A KR 970072085A
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South Korea
Prior art keywords
lower metal
oxide film
metal layer
forming
deposited
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KR1019960011720A
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Korean (ko)
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KR100427539B1 (en
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김영우
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김주용
현대전자산업 주식회사
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Priority to KR1019960011720A priority Critical patent/KR100427539B1/en
Publication of KR970072085A publication Critical patent/KR970072085A/en
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Publication of KR100427539B1 publication Critical patent/KR100427539B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 다중 금속층 형성 방법에 관한 것으로, 금속층간 절연막의 절연 및 평탄도를 향상시키기 위하여 하부 금속배선을 형성한 후 상기 하부 금속배선간의 공간이 완전히 매립되는 시점까지 산화막증착 및 식각 공정을 반복 실시하므로써 금속배선과 금속배선 그리고 금속층간의 절연 및 표면의 평탄도가 향상되어 소자의 전기적 특성이 향상될 수 있도록 한 반도체 소자의 다중 금속층 형성 방법에 관한 것이다.The present invention relates to a method of forming a multiple metal layer of a semiconductor device, in which a lower metal interconnection is formed to improve insulation and flatness of a metal interlayer insulating film, and then an oxide film deposition and etching process is performed until a space between the lower metal interconnection is completely buried The present invention relates to a method for forming a multiple metal layer of a semiconductor device in which insulation between metal wires, metal wires, and flatness of the surface is improved to improve the electrical characteristics of the device.

Description

반도체 소자의 다중 금속층 형성 방법Method for forming multiple metal layers of semiconductor devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2A도 내지 제2E도는 본 발명에 따른 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도.2A to 2E are sectional views of a device for explaining a method of forming a multiple metal layer of a semiconductor device according to the present invention.

Claims (6)

반도체 소자의 다중 금속층 형성방법에 있어서, 절연층이 형성된 실리콘 기판상에 하부 금속층을 형성한 후 상기 하부 금속층을 패터닝하여 하부 금속배선을 형성하는 제1단계와 상기 제1단계로부터 전체 상부면에 산화막을 증착하는 제2단계와, 상기 제2단계로부터 상기 하부 금속배선상에 증착된 산화막의 식각비가 상기 하부 금속배선의 측벽에 증착된 산화막의 식각비보다 높은 식각 방법을 이용하여 상기 산화막을 소정 두께 식각하는 제3단계와, 상기 제3단계로부터 상기 하부 금속배선간의 사이에 상기 산화막이 완전히 매립되는 동시에 표면이 평탄화되도록 상기 제2 및 제3단계의 공정을 순차적으로 반복 실행하는 제4단계와, 상기 제4단계로 부터 상기 하부 금속배선의 표면이 노출되도록 상기 산화막을 패터닝하여 콘택 홀을 형성한 후 상기 콘택 홀이 매립되도록 전체 상부면에 금속을 증착하여 상부 금속층을 형성하는 제5단계로 이루어지는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성 방법.A method for forming a multiple metal layer of a semiconductor device, comprising: a first step of forming a lower metal layer on a silicon substrate on which an insulating layer is formed and then patterning the lower metal layer to form a lower metal wiring; And a second step of depositing the oxide film on the lower metal wirings by using an etching method in which an etching rate of an oxide film deposited on the lower metal wirings is higher than an etching rate of an oxide film deposited on a sidewall of the lower metal wirings, A fourth step of sequentially performing the second and third steps so that the oxide film is completely buried and the surface is planarized between the third step and the lower metal wiring; The oxide film is patterned to expose a surface of the lower metal interconnection from the fourth step to form a contact hole, And a fifth step of depositing a metal on the entire upper surface to form the upper metal layer so as to fill the trench hole. 제1항에 있어서, 상기 하부 금속층은 5000 내지 10,000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성 방법.The method of claim 1, wherein the lower metal layer is formed to a thickness of 5000 to 10,000 ANGSTROM. 제1항에 있어서, 상기 제2단계의 상기 산화막 증착시 상기 하부 금속배선상에 증착되는 두께와 상기 하부 금속배선의 측벽에 증착되는 두께 비율은 1 : 0.6 내지 0.8이 되도록 하는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성 방법.2. The semiconductor device according to claim 1, wherein a ratio of a thickness deposited on the lower metal wirings and a thickness ratio of deposited on the sidewalls of the lower metal wirings is 1: 0.6-0.8 when the oxide film is deposited in the second step. A method of forming a multiple metal layer in a device. 제1항에 있어서, 상기 제3단계의 상기 산화막 식각공정시 상기 하부 금속배선상에 잔류되는 두께 및 상기 하부 금속배선의 측벽에 잔류되는 두께 비율은 1 : 0.8 내지 0.95이 되도록 하는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성 방법.2. The method of claim 1, wherein the ratio of the thickness remaining on the lower metal wirings and the thickness remaining on the sidewalls of the lower metal wirings in the oxide film etching process in the third step is 1: 0.8 to 0.95 A method of forming a multiple metal layer of a semiconductor device. 제1항에 있어서, 상기 식각 공정은 건식으로 실시되는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성 방법.The method of claim 1, wherein the etching process is performed in a dry manner. 제5항에 있어서, 상기 건식 식각은 CF4가스를 이용한 산소(O2) 플라즈마 식각 방법으로 실시되는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성 방법.The method of claim 5, wherein the dry etching is a method of forming a multi-metal layer of the semiconductor element characterized in that which is performed in an oxygen (O 2) plasma etching method using CF 4 gas. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960011720A 1996-04-18 1996-04-18 Method of forming multilayer metal of semiconductor device using improved intermetal dielectric KR100427539B1 (en)

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KR100427539B1 KR100427539B1 (en) 2004-07-01

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Publication number Priority date Publication date Assignee Title
KR920010892A (en) * 1990-11-30 1992-06-27 김광호 Surface flattening method of semiconductor device
KR950009930A (en) * 1993-09-25 1995-04-26 김주용 Metal wiring formation method of semiconductor device

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