KR20000000882A - Method for forming a tungsten plug of semiconductor devices - Google Patents
Method for forming a tungsten plug of semiconductor devices Download PDFInfo
- Publication number
- KR20000000882A KR20000000882A KR1019980020801A KR19980020801A KR20000000882A KR 20000000882 A KR20000000882 A KR 20000000882A KR 1019980020801 A KR1019980020801 A KR 1019980020801A KR 19980020801 A KR19980020801 A KR 19980020801A KR 20000000882 A KR20000000882 A KR 20000000882A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- tungsten
- contact holes
- forming
- adhesive layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 보다 상세하게는, 서로 다른 크기를 갖는 콘택홀들의 내부를 충진시키기 위한 텅스텐 플러그의 형성방법에 관한 것이다. 본 발명의 반도체 소자의 텅스텐 플러그 형성방법은, 서로 다른 크기의 콘택홀들이 구비된 절연막이 형성되어 있는 반도체 기판을 제공하는 단계; 상기 절연막 상부 및 콘택홀들의 내벽에 제1접착층 및 배리어 금속막을 적층시키는 단계; 상기 콘택홀들이 완전히 매립되도록 전체 상부에 텅스텐막을 형성하는 단계; 상기 텅스텐막 상에 제2접착층을 형성하는 단계; 상기 제2접착층 상에 알루미늄 금속막을 증착하는 단계; 및 상기 배리어 금속막이 노출될 때까지 상기 알루미늄 금속막과 제2접착층 및 텅스텐막을 동일한 식각 선택비로 에치백하여 상기 콘택홀의 내부를 충진시키는 텅스텐 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a tungsten plug for filling the inside of contact holes having different sizes. A method of forming a tungsten plug of a semiconductor device of the present invention may include providing a semiconductor substrate having an insulating film having contact holes of different sizes formed thereon; Stacking a first adhesive layer and a barrier metal film on the insulating film and on inner walls of the contact holes; Forming a tungsten film on the whole of the contact holes so that the contact holes are completely filled; Forming a second adhesive layer on the tungsten film; Depositing an aluminum metal film on the second adhesive layer; And forming a tungsten plug to fill the inside of the contact hole by etching back the aluminum metal layer, the second adhesive layer, and the tungsten layer at the same etching selectivity until the barrier metal layer is exposed.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 보다 상세하게는, 서로 다른 크기를 갖는 콘택홀들의 내부를 충진시키기 위한 텅스텐 플러그의 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a tungsten plug for filling the inside of contact holes having different sizes.
최근, 반도체 소자의 고집적화가 진행됨에 따라 배선 설계가 자유롭고 용이하며 배선저항 및 전류용량등의 설정을 여유있게 할 수 있는 다층 금속 배선 기술에 관한 연구가 활발히 진행되고 있다.Recently, as the integration of semiconductor devices is advanced, research has been actively conducted on multilayer metal wiring technology that enables free and easy wiring design and allows setting of wiring resistance and current capacity.
한편, 다층 금속 배선에서는 반도체 기판과 배선 사이 또는 상·하층 배선 사이를 전기적으로 연결하기 위한 접속 통로로서 콘택홀을 형성하고 있으며, 이러한 콘택홀을 매립하기 위한 금속 배선의 재료로는 전도도가 높고 경제성이 있는 알루미늄 및 그의 합금이 주로 이용되고 있다.On the other hand, in the multi-layered metal wiring, contact holes are formed as connection passages for electrically connecting the semiconductor substrate and the wiring or between the upper and lower wirings, and the conductivity of the metal wiring for filling the contact holes is high and economical. Aluminum and alloys thereof are mainly used.
그러나, 콘택홀의 크기가 감소함에 따라, 일반적인 스퍼터링 방법으로는 콘택홀을 완전히 매립시키지 못하는 현상이 발생되기 때문에 최근에는 층덮힘 특성이 우수한 텅스텐등과 같은 금속을 사용하여 콘택홀에 매립시키고, 그 상부에 금속 배선을 형성시키는 방법이 제안되었다.However, as the size of the contact hole decreases, a phenomenon in which the contact hole is not completely filled by the general sputtering method occurs. In recent years, the contact hole is buried in a contact hole by using a metal such as tungsten having excellent layer covering properties. A method of forming a metal wiring in a wire was proposed.
도 1a 내지 도 1c는 종래 기술에 따른 텅스텐 플러그의 형성방법을 설명하기 위한 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a tungsten plug according to the prior art.
우선, 도 1a에 도시된 바와 같이, 하부 패턴들(도시안됨)이 형성된 반도체 기판(1) 상에 절연막(2)을 형성하고, 이어서, 공지된 포토리소그라피 공정을 실시하여 절연막(2)내에 서로 다른 폭을 갖는 콘택홀들(3a, 3b)을 형성한다.First, as shown in FIG. 1A, an insulating film 2 is formed on a semiconductor substrate 1 on which lower patterns (not shown) are formed, and then, a known photolithography process is performed to perform a mutual process in the insulating film 2. Contact holes 3a and 3b having different widths are formed.
그런 다음, 도 1b에 도시된 바와 같이, 절연막(2) 상부 및 콘택홀들(3a, 3b)의 내벽에 스퍼터링 방식으로 Ti 금속으로된 박막의 접착층(4)을 형성하고, 이어서, 상기 접착층(4) 상에 TiN 금속으로된 배리어 금속막(5)을 형성한 상태에서, 상기 콘택홀들(3a, 3b)이 완전히 매립될 수 있도록 전체 상부에 화학기상증착 방식으로 텅스텐막(6)을 형성한다.Then, as shown in FIG. 1B, an adhesive layer 4 of a thin Ti metal is formed on the upper surface of the insulating film 2 and the inner walls of the contact holes 3a and 3b by sputtering, and then the adhesive layer ( 4) With the barrier metal film 5 made of TiN metal formed thereon, the tungsten film 6 is formed on the whole by chemical vapor deposition so that the contact holes 3a and 3b can be completely buried. do.
다음으로, 도 1c에 도시된 바와 같이, 절연막(2)의 상부 표면이 노출될 때까지 상기 텅스텐막(6)을 에치백하여 콘택홀들을 충진시키는 텅스텐 플러그들(6a, 6b)를 형성한다,Next, as shown in FIG. 1C, the tungsten film 6 is etched back until the upper surface of the insulating film 2 is exposed to form tungsten plugs 6a and 6b for filling the contact holes.
이후, 전체 상부에 소정의 금속막을 전면 증착하고, 이를 패터닝하여 금속배선을 형성한다.Subsequently, a predetermined metal film is entirely deposited on the entire upper surface, and patterned to form a metal wiring.
그러나, 콘택홀들의 크기가 동일할 경우에는 별 문제가 없지만, 도 1c에 도시된 바와 같이, 콘택홀들의 크기가 서로 상이한 경우에는 균일한 형상의 텅스텐 플러그들을 형성할 수 없음은 물론 금속배선의 불량을 유발시키게 되는 문제점이 있었다.However, there is no problem when the sizes of the contact holes are the same, but as shown in FIG. 1C, when the sizes of the contact holes are different from each other, it is not possible to form tungsten plugs having a uniform shape, as well as a poor metal wiring. There was a problem that caused.
자세하게, 크기가 상이한 콘택홀들이 구비되어 있는 절연막 상에 화학기상증착 방법으로 텅스텐막을 형성하게 되면, 크기가 큰 콘택홀 부분에 증착되는 텅스텐막 부분이 다른 부분에 비해 상대적으로 낮은 높이를 갖게 되고, 이러한 상태에서 에치백 공정을 실시하게 되면, 크기가 큰 콘택홀의 상부에 위치된 텅스텐막 부분이 다른 부분에 비해 더 많이 식각됨으로써 상대적으로 크기가 큰 콘택홀 내에 충진된 텅스텐 플러그의 표면에는 홈이 형성되기 때문에 텅스텐 플러그들의 형상이 균일하지 못하게 되고, 이러한 홈에 기인하여 표면 평탄성이 불량하게 되기 때문에 후속 공정에서 금속배선의 불량이 발생하게 된다.In detail, when the tungsten film is formed by chemical vapor deposition on an insulating film having different sized contact holes, the tungsten film portion deposited on the large contact hole portion has a relatively lower height than other portions. When the etchback process is performed in such a state, grooves are formed on the surface of the tungsten plug filled in the relatively large contact hole by etching more of the tungsten film portion positioned on the larger contact hole than other portions. As a result, the tungsten plugs are not uniform in shape, and due to such grooves, the surface flatness is poor, resulting in a poor metal wiring in a subsequent process.
한편, 텅스텐막의 두께를 증가시켜 상기 텅스텐막의 표면 평탄화를 달성한 후에 에치백을 실시하게 되면 상기한 문제를 어느 정도는 해결할 수는 있지만, 이 경우에는 텅스텐막의 결정립 크기 증가로 인하여 표면 거칠기가 증가하게 되기 때문에 상기 텅스텐막의 에치백시에 배리어 금속막의 표면이 거칠어지게 되는 문제를 초래하게 되고, 아울러, 텅스텐막의 증착 시간 및 비용이 증가되는 또 다른 문제점을 초래하게 된다.On the other hand, if the etch-back is performed after increasing the thickness of the tungsten film to achieve the surface planarization of the tungsten film, the above problem can be solved to some extent, but in this case, the surface roughness is increased due to the increase in the grain size of the tungsten film. This results in a problem that the surface of the barrier metal film becomes rough when the tungsten film is etched back, and another problem that the deposition time and cost of the tungsten film is increased.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 텅스텐 플러그의 평탄성을 향상시킬 수 있는 반도체 소자의 텅스텐 플러그 형성방법을 제공하는데, 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a tungsten plug of a semiconductor device capable of improving the flatness of a tungsten plug.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 텅스텐 플러그 형성방법을 설명하기 위한 공정 단면도.1A to 1C are cross-sectional views illustrating a method of forming a tungsten plug of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 텅스텐 플러그 형성방법을 설명하기 위한 일련의 공정 단면도.2A to 2D are cross-sectional views of a series of steps for explaining a method of forming a tungsten plug in a semiconductor device according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 반도체 기판 12 : 절연막11 semiconductor substrate 12 insulating film
13a,13b : 콘택홀 14 : 제1접착층13a, 13b: contact hole 14: first adhesive layer
15 : 배리어 금속막 16 : 텅스텐막15 barrier metal film 16 tungsten film
16a,16b : 텅스텐 플러그 17 : 제2접착층16a, 16b: tungsten plug 17: second adhesive layer
18 : 알루미늄 금속막18: aluminum metal film
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 텅스텐 플러그 형성방법은, 서로 다른 크기의 콘택홀들이 구비된 절연막이 형성되어 있는 반도체 기판을 제공하는 단계; 상기 절연막 상부 및 콘택홀들의 내벽에 제1접착층 및 배리어 금속막을 적층시키는 단계; 상기 콘택홀들이 완전히 매립되도록 전체 상부에 텅스텐막을 형성하는 단계; 상기 텅스텐막 상에 제2접착층을 형성하는 단계; 상기 제2접착층 상에 알루미늄 금속막을 증착하는 단계; 및 상기 배리어 금속막이 노출될 때까지 상기 알루미늄 금속막과 제2접착층 및 텅스텐막을 동일한 식각 선택비로 에치백하여 상기 콘택홀의 내부를 충진시키는 텅스텐 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a tungsten plug of a semiconductor device, the method including: providing a semiconductor substrate having an insulating film having contact holes of different sizes formed thereon; Stacking a first adhesive layer and a barrier metal film on the insulating film and on inner walls of the contact holes; Forming a tungsten film on the whole of the contact holes so that the contact holes are completely filled; Forming a second adhesive layer on the tungsten film; Depositing an aluminum metal film on the second adhesive layer; And forming a tungsten plug to fill the inside of the contact hole by etching back the aluminum metal layer, the second adhesive layer, and the tungsten layer at the same etching selectivity until the barrier metal layer is exposed.
본 발명에 따르면, 2단계에 걸친 알루미늄 금속막의 증착 공정을 통해 표면 평탄성을 확보함으로써, 서로 다른 콘택홀들 내부에 평탄한 표면을 갖는 텅스텐 플러그들을 형성할 수 있다.According to the present invention, by securing the surface flatness through the deposition process of the aluminum metal film in two steps, it is possible to form tungsten plugs having a flat surface in the different contact holes.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 텅스텐 플러그 형성방법을 설명하기 위한 일련의 공정 단면도이다.2A through 2D are cross-sectional views illustrating a process of forming a tungsten plug in a semiconductor device according to an embodiment of the present invention.
우선, 도 2a에 도시된 바와 같이, 트랜지스터와 같은 하부 패턴들(도시안됨)이 형성된 반도체 기판(11) 상에 SiO2와 같은 절연막(12)을 형성하고, 이어서, 공지된 방법으로 상기 절연막(12)의 소정 부분에 서로 다른 크기를 갖는 제1 및 제2콘택홀들(13a, 13b)을 형성한 후, 상기 콘택홀들(13a, 13b)에 대한 클리닝 공정을 실시한다. 여기서, 제2콘택홀(13b)은 제1콘택홀(13a)에 비해 상대적으로 큰 크기로 형성한다.First, as shown in FIG. 2A, an insulating film 12 such as SiO 2 is formed on a semiconductor substrate 11 on which lower patterns (not shown) such as a transistor are formed, and then the insulating film ( After forming the first and second contact holes 13a and 13b having different sizes in a predetermined portion of 12), the cleaning process is performed on the contact holes 13a and 13b. Here, the second contact hole 13b is formed to have a relatively larger size than the first contact hole 13a.
그런 다음, 도 2b에 도시된 바와 같이, 절연막(12) 상부 및 콘택홀들(13a, 13b)의 내벽에 300 내지 500Å 두께로 Ti 금속으로된 제1접착층(14)을 형성하고, 이러한 제1접착층(14) 상에 600 내지 800Å 두께로 TiN 금속으로된 배리어 금속막(15)을 형성한다.Then, as illustrated in FIG. 2B, a first adhesive layer 14 made of Ti metal having a thickness of 300 to 500 μm is formed on the insulating film 12 and the inner walls of the contact holes 13a and 13b. On the adhesive layer 14, a barrier metal film 15 made of TiN metal is formed to a thickness of 600 to 800 Å.
다음으로, 도 2c에 도시된 바와 같이, 콘택홀들이 완전히 매립될 수 있도록 전체 상부에 화학기상증착 방식으로 텅스텐막(16)을 증착하고, 이 텅스텐막(16) 상에 200 내지 400Å 두께로 Ti 금속으로된 제2접착층(17)을 형성한다. 그런 다음, 제2접착층(17) 상에 스퍼터링 방식으로 알루미늄 금속막(18)을 형성한다.Next, as shown in FIG. 2C, a tungsten film 16 is deposited by chemical vapor deposition on the entire upper part so that the contact holes can be completely buried, and Ti on the tungsten film 16 with a thickness of 200 to 400 Å. A second adhesive layer 17 made of metal is formed. Then, the aluminum metal film 18 is formed on the second adhesive layer 17 by sputtering.
상기에서, 제2접착층(17)은 텅스텐막(16)과 알루미늄 금속막(18)간의 접착력을 높이기 위하여 형성하는 것이다. 또한, 알루미늄 금속막(18)은 2단계 증착공정을 통해 표면 평탄화가 확보되도록 형성하며, 1단계 증착공정은 100 내지 350℃의 저온에서 실시하고, 2단계 증착공정은 400 내지 500℃의 고온에서 실시한다.In the above, the second adhesive layer 17 is formed to increase the adhesive force between the tungsten film 16 and the aluminum metal film 18. In addition, the aluminum metal film 18 is formed to ensure the surface planarization through a two-step deposition process, the first step deposition process is carried out at a low temperature of 100 to 350 ℃, the two-step deposition process at a high temperature of 400 to 500 ℃ Conduct.
계속해서, 도 2d에 도시된 바와 같이, 배리어 금속막(15)이 노출될 때까지 알루미늄 금속막(18)과 제2접착층(17) 및 텅스텐막(16)을 연속적으로 에치백하여 서로 다른 크기의 콘택홀들을 충진시키는 텅스텐 플러그들(16a, 16b)을 형성한다. 이때, 에치백 공정은 Cl2또는 SF6가스를 사용하며, 아울러, 알루미늄 금속막(18)과 제2접착층(17) 및 텅스텐막(16)의 식각 선택비가 동일하게 되는 조건으로 실시한다.Subsequently, as shown in FIG. 2D, the aluminum metal film 18, the second adhesive layer 17, and the tungsten film 16 are successively etched back until the barrier metal film 15 is exposed to each other. Tungsten plugs 16a and 16b are formed to fill the contact holes of each other. In this case, the etch back process uses Cl 2 or SF 6 gas, and is performed under the condition that the etching selectivity of the aluminum metal film 18, the second adhesive layer 17, and the tungsten film 16 are the same.
이후, 도시되지는 않았지만, 콘택홀들을 충진시키는 텅스텐 플러그들을 형성한 상태에서, 전체 상부에 스퍼터링 방식으로 금속막을 증착하고, 상기 금속막을 패터닝하여 텅스텐 플러그와 콘택되는 금속배선을 형성한다. 이때, 상기 금속막은 3층 구조로 형성하되, 텅스텐 플러그와 접촉되는 제1층은 접착층의 역할을 하도록 Ti막 또는 TiN막으로 형성하고, 2층은 알루미늄 금속막으로 형성하며, 3층은 비반사막의 역할을 하도록 Ti 및 TiN의 적층막으로 형성한다. 또한, 알루미늄 금속막의 증착시에는 2단계 증착법을 채택하여 알루미늄막의 평탄화를 더욱 향상시킨다.Subsequently, although not shown, in the state in which tungsten plugs filling the contact holes are formed, a metal film is deposited on the whole by sputtering, and the metal film is patterned to form a metal wiring contacting the tungsten plug. In this case, the metal film is formed in a three-layer structure, wherein the first layer in contact with the tungsten plug is formed of a Ti film or a TiN film to serve as an adhesive layer, two layers are formed of an aluminum metal film, and three layers are antireflective films. It is formed of a laminated film of Ti and TiN to play a role. In addition, when the aluminum metal film is deposited, a two-step deposition method is adopted to further improve the planarization of the aluminum film.
일반적으로, 서로 다른 크기의 콘택홀들이 형성되어 있는 절연막 상에 텅스텐막을 전면 증착시키게 되면, 상대적으로 크기가 큰 제2콘택홀을 매립하는 텅스텐막 부분의 표면은 다른 부분에 비해 상대적으로 낮은 높이를 갖게 되고, 이러한 상태에서 후속의 에치백 공정을 실시하게 되면, 제2콘택홀을 충진시키는 텅스텐 플러그의 표면에 홈이 발생된다.In general, when the tungsten film is entirely deposited on the insulating film on which contact holes of different sizes are formed, the surface of the tungsten film portion filling the second contact hole having a relatively large size has a relatively low height compared to other portions. In this state, when a subsequent etch back process is performed, grooves are formed on the surface of the tungsten plug filling the second contact hole.
그러나, 본 발명의 실시예에서 처럼 텅스텐막 상에 알루미늄 금속막을 증착하여 표면 평탄화를 확보하기 때문에, 이러한 상태에서 에치백 공정을 실시할 경우에는 제2콘택홀을 충진시키는 텅스텐 플러그의 표면에 홈이 발생되지 않는다.However, as in the embodiment of the present invention, the aluminum metal film is deposited on the tungsten film to secure the planarization. Therefore, when the etchback process is performed in this state, grooves are formed on the surface of the tungsten plug filling the second contact hole. It does not occur.
그러므로, 후속 공정인 금속배선의 형성시에 하층부의 평탄성 불량에 기인된 결함을 방지할 수 있게 되며, 결과적으로는 금속배선의 신뢰성을 향상시킬 수 있게 된다.Therefore, it is possible to prevent defects caused by poor flatness of the lower layer portion in the formation of the metal wiring, which is a subsequent process, and as a result, it is possible to improve the reliability of the metal wiring.
이상에서와 같이, 본 발명은 서로 다른 크기를 갖는 콘택홀들이 매립되도록 텅스텐막을 전면 증착한 후에, 상기 텅스텐막의 표면 평탄화가 이루어지도록 알루미늄 금속막을 더 형성하고, 이후, 동일한 식각 선택비를 갖는 식각 조건으로 상기 알루미늄 금속막 및 텅스텐막을 연속적으로 에치백함으로써, 콘택홀의 크기에 관계없이 표면 평탄화가 이루어진 텅스텐 플러그들을 형성할 수 있다.As described above, according to the present invention, after the entire surface deposition of the tungsten film to fill the contact holes having different sizes, the aluminum metal film is further formed to planarize the tungsten film, and then etching conditions having the same etching selectivity are performed. By continuously etching back the aluminum metal film and the tungsten film, it is possible to form tungsten plugs having surface planarization regardless of the size of the contact hole.
따라서, 하층부의 평탄화가 확보되는 것에 기인하여 금속배선의 신뢰성을 향상시킬 수 있다.Therefore, it is possible to improve the reliability of the metal wiring due to the flattening of the lower layer portion.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980020801A KR20000000882A (en) | 1998-06-05 | 1998-06-05 | Method for forming a tungsten plug of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980020801A KR20000000882A (en) | 1998-06-05 | 1998-06-05 | Method for forming a tungsten plug of semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000000882A true KR20000000882A (en) | 2000-01-15 |
Family
ID=19538417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980020801A KR20000000882A (en) | 1998-06-05 | 1998-06-05 | Method for forming a tungsten plug of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000000882A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10269629B2 (en) | 2016-09-05 | 2019-04-23 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
| KR20220128584A (en) | 2021-03-11 | 2022-09-21 | 한국전자기술연구원 | Hydrofluoric acid detection sensor and hydrofluoric acid detection method using the same |
-
1998
- 1998-06-05 KR KR1019980020801A patent/KR20000000882A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10269629B2 (en) | 2016-09-05 | 2019-04-23 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
| KR20220128584A (en) | 2021-03-11 | 2022-09-21 | 한국전자기술연구원 | Hydrofluoric acid detection sensor and hydrofluoric acid detection method using the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100585115B1 (en) | Semiconductor device having metal-insulator-metal capacitor and method for fabricating same | |
| JP2001185614A (en) | Semiconductor device and its manufacturing method | |
| JP2004079924A (en) | Semiconductor device | |
| KR20000000882A (en) | Method for forming a tungsten plug of semiconductor devices | |
| KR20000019877A (en) | Semiconductor device having multi-layered metallic wire and method for fabriacting the same | |
| KR20000000881A (en) | Method for forming a tungsten plug of semiconductor devices | |
| KR100450244B1 (en) | Semiconductor device and fabrication method of thereof | |
| KR19990062003A (en) | Method of forming multilayer metal wiring in semiconductor device | |
| KR20020034468A (en) | Method of manufacturing a semiconductor device | |
| KR20080061168A (en) | Method of manufacturing a metal line in semiconductor device | |
| KR100661220B1 (en) | Method for forming metal interconnect with dual dielectric layer | |
| KR0168164B1 (en) | Method of fabricating semiconductor device | |
| KR100557612B1 (en) | A method for forming a metal line of a semiconductor device | |
| KR100269662B1 (en) | Method for manufacturing conductor plug of semiconductor device | |
| KR100265972B1 (en) | Method for forming mutilayer og semiconductor device | |
| KR100427539B1 (en) | Method of forming multilayer metal of semiconductor device using improved intermetal dielectric | |
| KR100559560B1 (en) | Method for forming multi-layered metal line of the semiconductor device | |
| KR20040050515A (en) | Method for forming multi level metal interconnection using self aligned via plug and air gap | |
| KR100383084B1 (en) | Plug forming method of semiconductor devices | |
| KR100277867B1 (en) | Method for forming metal line of semiconductor device | |
| KR20040025110A (en) | Method for forming a tungsten plug of semiconductor device | |
| JPH04209571A (en) | Manufacture of semiconductor device | |
| KR19990061060A (en) | Contact formation method of semiconductor device | |
| KR19990057891A (en) | Stack contact formation method of semiconductor device | |
| KR20020086098A (en) | a contact structure for interconnecting multi-level wires and a method for forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |