KR100269662B1 - Method for manufacturing conductor plug of semiconductor device - Google Patents

Method for manufacturing conductor plug of semiconductor device Download PDF

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Publication number
KR100269662B1
KR100269662B1 KR1019970082305A KR19970082305A KR100269662B1 KR 100269662 B1 KR100269662 B1 KR 100269662B1 KR 1019970082305 A KR1019970082305 A KR 1019970082305A KR 19970082305 A KR19970082305 A KR 19970082305A KR 100269662 B1 KR100269662 B1 KR 100269662B1
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South Korea
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conductor plug
metal layer
interlayer insulating
conductor
insulating film
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KR1019970082305A
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Korean (ko)
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KR19990062000A (en
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김종일
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

PURPOSE: A method for forming a conductor plug of a semiconductor device is provided to improve a step coverage of an upper interconnection line formed on an upper surface of the conductor plug by reducing a step between an interlayer insulation film and the conductor plug. CONSTITUTION: A lower interconnection line(102) and an interlayer insulation film(104) are formed on an interlayer insulation film(100) to insulate a metal interconnection line and a semiconductor device. And, an open aperture is formed by opening a surface of the lower interconnection line by selectively etching the interlayer insulation film using a photo lithography and etching process. Then, a glue layer(109) is formed on the interlayer insulation film by stacking a Ti film(108) and a TiN film(110) in sequence. A tungsten conductor is deposited to fill the open aperture completely on the glue layer. Then, the tungsten is planarized by a blanket etching process to remain only on the open aperture. Thus, a conductor plug(112') connected with the lower interconnection line is formed. Then, the glue layer remained on the upper surface of the interlayer insulation film is removed by a blanket etching process.

Description

반도체 장치의 도전체 플러그 형성 방법Method for forming conductor plug in semiconductor device

본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 하부 배선과 상부 배선의 층간 접속을 위해 콘택홀(Contact hole)이나 비아(Via)와 같은 개구부에 도전체 플러그를 형성하는 반도체 장치의 도전체 플러그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a conductor plug of a semiconductor device for forming a conductor plug in an opening such as a contact hole or via for interlayer connection between a lower wiring and an upper wiring. It relates to a forming method.

반도체 장치의 집적도가 증가함에 따라, 반도체 장치의 콘택홀은 크기가 작아지고 어스펙트비(Aspect ratio)가 증가하게 되어 하부 배선과 상부 배선의 전기적 연결을 위해 형성되는 도전체 플러그가 우수한 단차 도포성(Step coverage)을 가지면서 낮은 콘택저항을 갖도록 하는 제조 기술이 중요시 되고 있다.As the degree of integration of the semiconductor device increases, the contact hole of the semiconductor device decreases in size and the aspect ratio increases, so that the conductor plug formed for the electrical connection between the lower wiring and the upper wiring has excellent step coverage. (Step coverage) and manufacturing technology to have a low contact resistance is becoming important.

도 1은 종래 기술에 의한 반도체 장치의 도전체 플러그 구조를 나타낸 단면도로서, 종래 기술에 의한 도전체 플러그 구조는 하부 반도체 소자와 상부 배선간의 층간 절연을 위한 층간 절연막(10) 위에 형성된 하부 배선(12)과, 하부 배선(12)이 형성된 층간 절연막(14)의 콘택홀을 통해서 접착 금속층(Glue layer,19)을 내재하여 도전체가 매립된 도전체 플러그(22)로 구성된다.1 is a cross-sectional view showing a conductor plug structure of a semiconductor device according to the prior art, wherein the conductor plug structure according to the prior art has a lower wiring 12 formed on the interlayer insulating film 10 for interlayer insulation between the lower semiconductor element and the upper wiring. ) And a conductor plug 22 in which a conductor is embedded by embedding an adhesive metal layer 19 through a contact hole of the interlayer insulating layer 14 on which the lower wiring 12 is formed.

이러한 구조를 가지는 반도체 장치의 형성 방법은 하부 배선(12) 위의 층간 절연막(14) 내에 콘택홀을 형성한 후에 도전체와 절연체의 접착력을 향상시키기 위하여 접착 금속층(19)으로서 Ti막(18)과 TiN(20)을 콘택홀을 포함한 층간 절연막(14) 전면에 순차적으로 형성하였다. 이어서 접착 금속층(19) 전면에 도전체로서 텅스텐을 증착한 후에 SF6를 기본 가스로 사용하여 텅스텐을 전면 식각해서 콘택홀 내에 도전체 플러그(22)를 형성하였다. 이때, 도전체 플러그(22)는 텅스텐으로 이루어질 경우 증착 특성상 웨이퍼 전면에 증착된 텅스텐의 막질에 비해 구조가 치밀하지 못하기 때문에 식각 가스에 의해 노출될 때 급속히 식각되는 현상을 보이게 된다. 따라서 도전체 플러그(22)는 전면 식각(etch back) 공정이 완료되면 상단부가 접착 금속층(19)에 비해서 하부로 함몰된 부분(S1)이 발생하게 된다.In the method of forming a semiconductor device having such a structure, after forming a contact hole in the interlayer insulating film 14 on the lower wiring 12, the Ti film 18 is used as the adhesive metal layer 19 to improve the adhesion between the conductor and the insulator. And TiN 20 were sequentially formed on the entire surface of the interlayer insulating film 14 including the contact holes. Subsequently, after tungsten was deposited as a conductor on the entire surface of the adhesive metal layer 19, tungsten was completely etched using SF 6 as a base gas to form a conductor plug 22 in the contact hole. In this case, when the conductor plug 22 is made of tungsten, the structure of the conductor plug 22 is not as compact as that of the tungsten deposited on the entire surface of the wafer, so that the conductor plug 22 is rapidly etched when exposed by the etching gas. Accordingly, the conductive plug 22 may have a portion S1 having an upper end recessed below the adhesive metal layer 19 when the etch back process is completed.

이 때문에 도전체 플러그(22)를 형성하기 위한 전면 식각 공정은 기본적으로 이러한 도전체 플러그(22)와 접착 금속층(19)의 단차를 줄이기 위해서 텅스텐과 TiN의 식각 선택비를 높게 하는데, 이는 TiN의 식각율이 높으면 TiN 내의 질소 원자 분리가 증대되어 SF6가스의 분해를 촉진시켜 결국 텅스텐을 식각하는 F 원자를 다량 생성시키는 결과를 가져오게 된다. 그러나, 이와 같이 식각 선택비를 높게 유지한다고 해도 도전체 플러그(22) 영역의 함몰을 완전히 방지할 수 없기 때문에 텅스텐 플러그와 층간 절연막의 단차가 여전히 발생하게 된다.For this reason, the front etching process for forming the conductor plug 22 basically increases the etching selectivity of tungsten and TiN in order to reduce the step difference between the conductor plug 22 and the adhesive metal layer 19. Higher etch rates increase the separation of nitrogen atoms in TiN, which promotes decomposition of SF 6 gas, resulting in the production of large amounts of F atoms that etch tungsten. However, even if the etching selectivity is kept high, the depression of the conductor plug 22 region cannot be completely prevented, so that the step between the tungsten plug and the interlayer insulating film still occurs.

이후 이러한 단차를 가지는 텅스텐 플러그는 후속 금속 배선 공정시 배선 불량을 발생하게 된다. 즉, 텅스텐 플러그를 포함한 층간 절연막 전면에 장벽 금속층으로서 Ti,TiN 또는 Ti/TiN을 500∼1000Å의 두께로 증착하고, 그 위에 상부 배선으로서 알루미늄을 스퍼터링 방법으로 증착한 후에 사진 및 식각 공정으로 알루미늄, 장벽 금속층 및 접착 금속층(19)까지를 식각하여 텅스텐 플러그와 연결되는 상부 배선을 형성하였다. 이러한 공정에 의한 반도체 장치는 접착 금속층와 텅스텐 함몰 부위의 단차가 전체적으로 합쳐져 더욱 취약한 배선 구조를 형성하기 때문에 알루미늄 증착이 단차 도포성(step coverage)의 열악함으로 인해 하부 구조의 단차대로 상부 배선의 패턴이 따라서 형성된다.Since the tungsten plug having such a step will cause a wiring defect in the subsequent metal wiring process. That is, Ti, TiN or Ti / TiN as a barrier metal layer is deposited on the entire surface of the interlayer insulating film including the tungsten plug with a thickness of 500 to 1000 GPa, and aluminum is deposited on the upper wiring by the sputtering method. The barrier metal layer and the adhesive metal layer 19 were etched to form an upper wiring connected to the tungsten plug. In this semiconductor device, the step of the adhesive metal layer and the tungsten recessed portion is generally combined to form a more fragile wiring structure, so that the deposition of the upper wiring pattern according to the step structure of the lower structure due to the poor step coverage of aluminum deposition. Is formed.

도 2는 종래 기술에 의한 반도체 장치의 스택(stackted) 비아에 형성된 도전체 플러그 구조를 나타낸 단면도로서, 도 1에 도시된 하부 반도체 소자와 상부 배선간의 층간 절연을 위한 층간 절연막(10) 위에 형성된 하부 배선(12)과, 하부 배선(12)이 형성된 층간 절연막(14)의 콘택홀을 통해서 Ti막(18)과 TiN(20)이 순차적으로 적층된 제 1 접착 금속층(19)을 내재하여 도전체가 매립된 제 1 도전체 플러그(22)와, 제 1 도전체 플러그(22)와 제 1 접착 금속층(19) 상부면에 형성된 제 1 장벽 금속층(24)과, 상기 층간 절연막(14) 내의 상기 제 1 장벽 금속층(24)에 대응하는 콘택홀을 통해서 Ti막(26)과 TiN(28)이 순차적으로 적층된 제 2 접착 금속층(27)을 내재하여 도전체가 매립된 제 2 도전체 플러그(30)와, 상기 제 2 도전체 플러그(30)와 제 2 접착 금속층(27) 상부면에 형성된 제 2 장벽 금속층(32)과, 상기 층간 절연막(14) 내의 상기 제 2 장벽 금속층(24)에 대응하는 콘택홀을 통해서 Ti막(34)과 TiN(36)이 순차적으로 적층된 제 2 접착 금속층(37)을 내재하여 도전체가 매립된 제 3 도전체 플러그(38)으로 구성된다.FIG. 2 is a cross-sectional view illustrating a conductor plug structure formed in a stacked via of a semiconductor device according to the related art, and includes a lower portion formed on an interlayer insulating layer 10 for interlayer insulation between a lower semiconductor element and an upper interconnection illustrated in FIG. 1. Through the contact holes of the wiring 12 and the interlayer insulating film 14 on which the lower wiring 12 is formed, the conductor is embedded in the first adhesive metal layer 19 in which the Ti film 18 and the TiN 20 are sequentially stacked. A buried first conductor plug 22, a first barrier metal layer 24 formed on an upper surface of the first conductor plug 22 and the first adhesive metal layer 19, and the first inside of the interlayer insulating layer 14. The second conductor plug 30 in which the conductor is embedded by embedding the second adhesive metal layer 27 in which the Ti film 26 and the TiN 28 are sequentially stacked through the contact hole corresponding to the first barrier metal layer 24. And a second barrier formed on an upper surface of the second conductor plug 30 and the second adhesive metal layer 27. The second adhesive metal layer 37 in which the Ti film 34 and the TiN 36 are sequentially stacked through the metal layer 32 and the contact hole corresponding to the second barrier metal layer 24 in the interlayer insulating layer 14. And a third conductor plug 38 in which a conductor is embedded.

이와 같이 구성된 스택 비아는 로직 소자에서 자주 사용되고 있으며, 제 1 도전체 플러그(22)와 제 3 도전체 플러그(38)를 연결하고자 할 때 1회에 의해서 비아를 형성하는 것이 어렵기 때문에 수직으로 여러 차례 걸쳐서 다층의 플러그 공정을 실시한다. 이 경우 상부로 갈수록 하부의 단차를 반영하기 때문에 제 3 도전체 플러그(38)와 제 2 접착 금속층(37)의 단차는 S2와 같이 그 단차가 크게 형성된다. 그러므로, 이러한 도전체 플러그와 접착 금속층의 단차는 상부 배선 공정시 단차 도포성의 문제를 야기시키기 때문에 그 취약성이 극대화되어 심각한 평탄화 문제와 비아 불량의 원인으로 작용하게 된다.Stack vias configured as described above are frequently used in logic devices, and when the first conductor plug 22 and the third conductor plug 38 are connected to each other, it is difficult to form a via at a time. A multilayer plug process is performed in turn. In this case, the step difference between the third conductor plug 38 and the second adhesive metal layer 37 is larger as S2 because the step difference of the lower part is reflected toward the upper part. Therefore, since the step difference between the conductor plug and the adhesive metal layer causes a problem of step coverage in the upper wiring process, the vulnerability is maximized, which causes serious planarization problems and via defects.

본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 도전체 플러그에 평탄화를 위한 전면 식각 공정을 실시한 후에 텅스텐 플러그와 층간 절연막 사이에 형성되는 접착 금속층의 평탄화 공정을 실시하므로써 도전체 플러그를 가지는 층간 절연막과 도전체 플러그의 단차를 감소시켜 도전체 플러그 상부면에 형성되는 상부 배선의 단차 도포성을 크게 향상시킬 수 있는 반도체 장치의 도전체 플러그 형성 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a conductor plug by planarizing an adhesive metal layer formed between a tungsten plug and an interlayer insulating film after performing a front surface etching process for planarization on the conductor plug to solve the problems of the prior art. The present invention provides a method for forming a conductor plug of a semiconductor device capable of greatly improving the step coverage of the upper wiring formed on the upper surface of the conductor plug by reducing the step between the interlayer insulating film and the conductor plug.

도 1은 종래 기술에 의한 반도체 장치의 도전체 플러그 구조를 나타낸 단면도이다.1 is a cross-sectional view showing a conductor plug structure of a semiconductor device according to the prior art.

도 2는 종래 기술에 의한 반도체 장치의 스택(stacked) 비아에 형성된 도전체 플러그 구조를 나타낸 단면도이다.2 is a cross-sectional view illustrating a conductor plug structure formed in a stacked via of a semiconductor device according to the prior art.

도 3 내지 도 7은 본 발명에 따른 도전체 플러그 형성 공정을 나타낸 공정 순서도이다.3 to 7 are process flowcharts showing a conductor plug forming process according to the present invention.

도 8은 본 발명에 따른 도전체 플러그 형성 공정시 접착 금속층을 제거하고자 감광막을 사용한 제조 공정을 나타낸 단면도이다.8 is a cross-sectional view showing a manufacturing process using a photosensitive film to remove the adhesive metal layer during the conductor plug forming process according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

100,104: 층간 절연막 102: 하부 배선100, 104 interlayer insulating film 102: lower wiring

106: 개구부 109: 접착 금속층106: opening 109: adhesive metal layer

112': 도전체 플러그 114: 감광막112 ': conductor plug 114: photosensitive film

상기 목적을 달성하기 위하여 본 발명의 제조 방법은 반도체 장치의 하부 배선과 상부 배선을 절연하기 위한 층간 절연막 내의 콘택홀을 통해서 하부 배선과 상부 배선이 전기적으로 연결되는 도전체 플러그를 형성함에 있어서, 상기 하부 배선 위의 층간 절연막을 선택 식각하여 하부 배선 표면을 개방하는 개구부를 형성하는 단계; 상기 개구부가 형성된 층간 절연막 전면에 접착 금속층을 형성하는 단계; 상기 접착 금속층 전면에 도전체를 개구부에 매립하도록 형성하는 단계; 상기 도전체를 평탄화하여 층간 절연막의 개구부에 도전체 플러그를 형성하는 단계; 및 상기 층간 절연막의 상부면에 잔여된 접착 금속층을 제거하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, in the manufacturing method of the present invention, in forming a conductor plug in which the lower wiring and the upper wiring are electrically connected through a contact hole in an interlayer insulating film for insulating the lower wiring and the upper wiring of the semiconductor device, Selectively etching the interlayer insulating film over the lower wiring to form an opening for opening the lower wiring surface; Forming an adhesive metal layer on an entire surface of the interlayer insulating layer on which the opening is formed; Forming a conductor in an opening in an entire surface of the adhesive metal layer; Planarizing the conductor to form a conductor plug in an opening of the interlayer insulating film; And removing the adhesive metal layer remaining on the upper surface of the interlayer insulating film.

본 발명의 제조 방법에 있어서, 상기 접착 금속층 제거 공정은 전면 식각 공정을 이용하며, 이때 공정 조건은 BCl3를 55∼60sccm, Cl2를 25∼30sccm로 한다.In the manufacturing method of the present invention, the adhesive metal layer removal process is a front etching process, wherein the process conditions are BCl 3 55 to 60 sccm, Cl 2 25 to 30 sccm.

또한, 본 발명의 제조 방법에 있어서, 상기 접착 금속층 제거 공정은 도전체 플러그를 포함한 층간 절연막 전면에 감광막을 900∼1100Å 두께로 도포하는 단계; 및 상기 감광막과 층간 절연막 위에 형성된 접착 금속층을 동시에 제거하는 단계를 더 포함하는 것을 특징으로 한다.In addition, in the manufacturing method of the present invention, the adhesive metal layer removing step comprises the steps of applying a photosensitive film to the entire surface of the interlayer insulating film including a conductor plug to a thickness of 900 ~ 1100Å; And simultaneously removing the adhesive metal layer formed on the photosensitive film and the interlayer insulating film.

본 발명에 따른 반도체 장치의 제조 방법에 의하면, 층간 절연막의 개구부에서 도전체 플러그를 형성하기 위한 전면 식각 공정을 형성한 후에 개구부 내의 접착력을 증가시키기 위해 형성된 접착 금속층을 제거하기 위한 전면 식각 공정을 실시한다. 이로 인해 본 발명은 도전체 플러그 평탄화 공정시 플러그 중앙 부위의 함몰 현상과 접착 금속층의 높이에 의해 발생되는 배선 간 단차를 감소시키므로서, 평탄화 공정과 동일한 향상 효과를 얻을 수 있다. 또한, 본 발명은 후속 금속 증착시 균일한 층간 절연막 및 도전체 플러그에 의해 단차 도포성을 향상시킬 수 있기 때문에 금속 배선의 피복성을 높일 수 있다.According to the method of manufacturing a semiconductor device according to the present invention, after forming the front surface etching process for forming the conductor plug in the opening of the interlayer insulating film, the front surface etching process for removing the adhesive metal layer formed to increase the adhesive force in the opening is performed. do. Therefore, the present invention can reduce the step difference between the wiring caused by the depression of the central portion of the plug and the height of the adhesive metal layer during the conductor plug flattening process, thereby achieving the same improvement effect as the flattening process. In addition, the present invention can improve the coverage of the metal wiring because the step coverage property can be improved by the uniform interlayer insulating film and the conductor plug during the subsequent metal deposition.

이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3 내지 도 7은 본 발명에 따른 도전체 플러그 형성 공정을 나타낸 공정 순서도이다.3 to 7 are process flowcharts showing a conductor plug forming process according to the present invention.

실리콘 기판(도시하지 않음)의 반도체 소자와 이후 형성될 금속 배선을 절연하기 위한 층간 절연막(100)위에 도 3에 나타난 바와 같이 하부 배선(102) 및 층간 절연막(104)을 순차적으로 형성한다.The lower wiring 102 and the interlayer insulating film 104 are sequentially formed on the interlayer insulating film 100 for insulating the semiconductor element of the silicon substrate (not shown) and the metal wiring to be formed subsequently.

그 다음 도 4에 나타난 바와 같이 콘택 마스크를 이용한 사진 및 식각 공정을 이용하여 층간 절연막(104)을 선택 식각하여 하부 배선(102) 표면이 개방하도록 개구부(106)를 형성한다.Next, as shown in FIG. 4, the interlayer insulating film 104 is selectively etched using a photolithography and an etching process using a contact mask to form the opening 106 to open the lower wiring 102 surface.

이어서 도 5에 나타난 바와 같이 개구부(106)가 형성된 층간 절연막(104) 전면에 접착 금속층(109)을 형성한다. 이때, 접착 금속층(109)은 Ti막(108)과 TiN막(110)을 순차적으로 적층시킨 구조로서, 1000 Å이하의 두께를 가진다. 그리고, 접착 금속층(109) 전면에 도전체(112), 예컨대 텅스텐을 이용하여 개구부(106)를 완전히 매립하면서 층간 절연막(104) 위에 증착한다.Subsequently, as shown in FIG. 5, the adhesive metal layer 109 is formed on the entire surface of the interlayer insulating layer 104 having the opening 106 formed therein. At this time, the adhesive metal layer 109 is a structure in which the Ti film 108 and the TiN film 110 are sequentially stacked, and has a thickness of 1000 GPa or less. The conductive layer 112, for example, tungsten, is used to deposit the opening 106 completely on the entire interlayer insulating film 104.

이어서 도 6에 나타난 바와 같이 전면 식각 공정을 실시하여 플라즈마로 텅스텐(112)을 평탄화하여 개구부(106)에만 텅스텐이 남도록 식각한다. 이로 인해 층간 절연막(104) 내의 개구부(106)에는 텅스텐이 완전히 채워지고, 층간 절연막(104)의 상부면에는 텅스텐이 제거되어 접착 금속층(109)을 내재하여 하부 배선(102)과 연결되는 도전체 플러그(112')가 형성된다.Subsequently, as shown in FIG. 6, the entire surface etching process is performed to planarize the tungsten 112 by plasma to etch the tungsten only in the opening 106. As a result, the opening 106 in the interlayer insulating film 104 is completely filled with tungsten, and the top surface of the interlayer insulating film 104 is removed with tungsten, and the conductor inherently connected to the lower wiring 102 by including the adhesive metal layer 109. Plug 112 'is formed.

그 다음 도 7에 나타난 바와 같이 전면 식각 공정을 실시하여 층간 절연막(104)의 상부면에 잔여된 접착 금속층(109)을 제거한다. 이때, 전면 식각 공정은 텅스텐과 Ti/TiN의 선택 식각비를 1:3∼4로 높이기 위해 BCl3를 55∼60sccm, Cl2를 25∼30sccm의 조건으로 한다. 즉, 도전체 플러그(112')를 이루는 텅스텐은 Cl2에 의해 식각이 잘 이루어지지 않으면서 접착 금속층(109)을 이루는 Ti막(108)과 TiN막(110)은 BCl3와 Cl2에 의해 식각이 잘 이루어지게 된다. 또한, 식각이 진행되는 동안 공정 온도를 낮추면 텅스텐의 식각율이 감소되어 도전체 플러그(112') 표면의 식각이 접착 금속층(109)의 식각에 비해 낮아진다. 이로 인해 도전체 플러그(112')가 형성된 층간 절연막(104) 표면에는 접착 금속층(109)이 제거되어 도전체 플러그(112')의 높이와 동일한 층간 절연막(104)이 얻어진다.Next, as shown in FIG. 7, the entire surface etching process is performed to remove the adhesive metal layer 109 remaining on the upper surface of the interlayer insulating layer 104. At this time, in the front etching process, BCl 3 is 55 to 60 sccm and Cl 2 is 25 to 30 sccm in order to increase the selective etching ratio of tungsten and Ti / TiN to 1: 3 to 4. That is, the tungsten constituting the conductor plug 112 'is not etched by Cl 2 , but the Ti film 108 and the TiN film 110 forming the adhesive metal layer 109 are formed by BCl 3 and Cl 2 . Etching works well. In addition, when the process temperature is lowered during the etching process, the etching rate of tungsten is decreased, so that the etching of the surface of the conductor plug 112 'is lower than that of the adhesive metal layer 109. As a result, the adhesive metal layer 109 is removed from the surface of the interlayer insulating film 104 on which the conductor plug 112 'is formed, thereby obtaining the interlayer insulating film 104 having the same height as the conductor plug 112'.

본 발명에 의하면, 도전체 전면 식각을 이용한 플러그 공정시 플러그 형성 영역의 함몰 현상과 접착 금속층의 높이 따른 단차를 발생하는 접착 금속층을 상부 배선 공정시 제거하지 않고 도전체 플러그 공정 후 제거시킨다. 이에 따라 상부 배선이 형성될 하부 표면이 균일하게 되어 화학적 연마 공정에 준하는 평탄화 효과를 얻을 수 있다.According to the present invention, in the plug process using the conductor entire surface etching, the adhesive metal layer, which generates the depression of the plug formation region and the height difference according to the height of the adhesive metal layer, is removed after the conductor plug process without being removed during the upper wiring process. As a result, the lower surface on which the upper wiring is to be formed is uniform, thereby obtaining a planarization effect similar to that of the chemical polishing process.

도 8은 본 발명에 따른 도전체 플러그 형성 공정시 접착 금속막을 제거하고자 감광막을 사용한 제조 공정을 나타낸 단면도이다.8 is a cross-sectional view showing a manufacturing process using a photosensitive film to remove the adhesive metal film during the conductor plug forming process according to the present invention.

위에서 설명한 바와 같이 접착 금속층(109) 식각 공정시 도전체 플러그(112')의 텅스텐과 접착 금속층(109)의 Ti/TiN에 해당하는 식각 선택비를 높게 얻기 어려울 경우에는 다음과 같은 제조 공정으로 접착 금속층(109)을 제거한다.As described above, when the etching selectivity corresponding to the tungsten of the conductor plug 112 'and the Ti / TiN of the bonding metal layer 109 is difficult to be obtained during the etching process of the bonding metal layer 109, the bonding is performed by the following manufacturing process. The metal layer 109 is removed.

전면 식각 공정을 실시하여 플라즈마로 텅스텐(112)을 평탄화하여 층간 절연막(104)의 개구부(106)에 도전체 플러그(112')를 형성한다. 이어서 도 8에 나타난 바와 같이 도전체 플러그(112')를 포함한 층간 절연막(104) 전면에 감광막(114)을 900∼1100Å 두께로 도포한다. 그리고, 위에서 설명했던 전면 식각 공정을 이용하여 감광막(114)과 층간 절연막(104) 위에 형성된 접착 금속층(109)을 동시에 제거한다. 여기서, 감광막(114)은 피복성이 우수하여 도전체 플러그(112') 영역에도 고르게 도포된다. Cl2를 주성분으로 하는 가스로 이 감광막(114)과 접착 금속층(109)을 동시에 식각할 경우 TiN과 감광막은 1:1의 식각 선택비를 가지게 되므로 도전체 플러그 영역내의 텅스텐을 식각 가스에 노출시키지 않고 보다 안전하게 식각 공정이 이루어진다.The entire surface etching process is performed to planarize the tungsten 112 by plasma to form the conductor plug 112 ′ in the opening 106 of the interlayer insulating layer 104. Subsequently, as shown in FIG. 8, a photosensitive film 114 is applied to the entire surface of the interlayer insulating film 104 including the conductor plug 112 ′ in a thickness of 900 to 1100 Å. Then, the adhesive metal layer 109 formed on the photoresist film 114 and the interlayer insulating film 104 is removed at the same time by using the entire surface etching process described above. Here, the photosensitive film 114 is excellent in coating property and is evenly applied to the region of the conductor plug 112 '. When the photoresist 114 and the adhesive metal layer 109 are simultaneously etched using a gas containing Cl 2 as a main component, the TiN and the photoresist have an etching selectivity of 1: 1. Etching process is done more safely

본 발명은 도전체 전면 식각을 이용한 플러그 공정시 플러그 형성 영역의 함몰 현상과 접착 금속층의 높이 따른 단차를 발생하는 접착 금속층을 상부 배선 공정시 제거하지 않고 도전체 플러그 공정 후 제거시킨다. 이에 따라 상부 배선이 형성될 하부 표면이 균일하게 되어 화학적 연마 공정에 준하는 평탄화 효과를 얻을 수 있다. 또한, 본 발명은 후속 금속 증착시 피복성의 취약성을 제거하면서 감광막의 패터닝 측면에서도 단차 감소로 인해 디자인 룰에 보다 근접하게 금속 배선 패턴을 정의할 수 있다.According to the present invention, an adhesive metal layer, which generates a recess in the plug forming region and a height difference according to the height of the adhesive metal layer, is removed after the conductor plug process without the upper wiring process. As a result, the lower surface on which the upper wiring is to be formed is uniform, thereby obtaining a planarization effect similar to that of the chemical polishing process. In addition, the present invention can define a metal wiring pattern closer to the design rule due to the step reduction in terms of patterning of the photoresist film while eliminating the fragility of the coating during subsequent metal deposition.

Claims (2)

반도체 장치의 하부 배선과 상부 배선을 절연하기 위한 층간 절연막 내의 콘택홀을 통해서 하부 배선과 상부 배선이 전기적으로 연결되는 도전체 플러그를 형성함에 있어서,In forming a conductor plug in which the lower wiring and the upper wiring are electrically connected through contact holes in the interlayer insulating film for insulating the lower wiring and the upper wiring of the semiconductor device, 상기 하부 배선 위의 층간 절연막을 선택 식각하여 하부 배선 표면을 개방하는 개구부를 형성하는 단계;Selectively etching the interlayer insulating film on the lower wiring to form an opening for opening the lower wiring surface; 상기 개구부가 형성된 층간 절연막 전면에 접착 금속층을 형성하는 단계;Forming an adhesive metal layer on an entire surface of the interlayer insulating layer on which the opening is formed; 상기 접착 금속층 전면에 도전체를 개구부에 매립하도록 형성하는 단계;Forming a conductor in an opening in an entire surface of the adhesive metal layer; 상기 도전체를 평탄화하여 층간 절연막의 개구부에 도전체 플러그를 형성하는 단계; 및Planarizing the conductor to form a conductor plug in an opening of the interlayer insulating film; And 상기 층간 절연막의 상부면에 잔여된 접착 금속층을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 도전체 플러그 형성 방법.And removing the adhesive metal layer remaining on the upper surface of the interlayer insulating film. 제1항에 있어서, 상기 접착 금속층 제거 공정은 도전체 플러그를 포함한 층간 절연막 전면에 감광막을 900∼1100Å 두께로 도포하는 단계; 및The method of claim 1, wherein the removing of the adhesive metal layer comprises: applying a photosensitive film to the entire surface of the interlayer insulating film including a conductor plug to a thickness of 900 to 1100 μs; And 상기 감광막과 층간 절연막 위에 형성된 접착 금속층을 동시에 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 도전체 플러그 형성 방법.And removing the adhesive metal layer formed on the photosensitive film and the interlayer insulating film at the same time.
KR1019970082305A 1997-12-31 1997-12-31 Method for manufacturing conductor plug of semiconductor device KR100269662B1 (en)

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Citations (1)

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Publication number Priority date Publication date Assignee Title
JPH0922881A (en) * 1995-07-06 1997-01-21 Sony Corp Formation of contact plug

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0922881A (en) * 1995-07-06 1997-01-21 Sony Corp Formation of contact plug

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