KR20010004188A - Method of fabricating of dual damascene of semiconductor device - Google Patents
Method of fabricating of dual damascene of semiconductor device Download PDFInfo
- Publication number
- KR20010004188A KR20010004188A KR1019990024808A KR19990024808A KR20010004188A KR 20010004188 A KR20010004188 A KR 20010004188A KR 1019990024808 A KR1019990024808 A KR 1019990024808A KR 19990024808 A KR19990024808 A KR 19990024808A KR 20010004188 A KR20010004188 A KR 20010004188A
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- South Korea
- Prior art keywords
- forming
- metal
- dual damascene
- etching
- via contact
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- 230000009977 dual effect Effects 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title description 7
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000002184 metal Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000010949 copper Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000000654 additive Substances 0.000 claims description 2
- 230000000996 additive effect Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 239000012495 reaction gas Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 18
- 230000008569 process Effects 0.000 abstract description 15
- 238000009413 insulation Methods 0.000 abstract description 6
- 239000011229 interlayer Substances 0.000 abstract description 5
- 238000010276 construction Methods 0.000 abstract 2
- 238000012856 packing Methods 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 듀얼 대머신공정에 관한 것으로, 특히 기존의 층간 식각방지층을 제거하고 플러그를 도입하여 충진율과 유전율을 증가시키는 듀얼 대머신공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual damascene process of a semiconductor device, and more particularly, to a dual damascene process of removing a conventional interlayer etch stop layer and introducing a plug to increase filling and dielectric constants.
반도체 칩내의 배선물질로는 SiO2와의 부착성, 형성의 용이성등의 측면에서 장점을 가지는 알루미늄(Al)이 사용되고 있다. 그러나 집적도가 높아지고 동작속도에 대한 요구가 증대되면서 Al배선은 EM(electromigration) 현상 및 비교적 높은 저항율로 인해 칩의 특성을 저해하는 요소로 작용하고 있다.As the wiring material in the semiconductor chip, aluminum (Al) having advantages in terms of adhesion to SiO 2 and ease of formation is used. However, as the degree of integration increases and the demand for operation speed increases, Al wiring acts as a factor that hinders the characteristics of the chip due to the phenomenon of electromigration (EM) and relatively high resistivity.
최근 배선 기술에 있어 구리(Cu)의 도입은 Al의 단점을 극복할 수 이쓴 새로운 대안을 제시해준다. 그러나 Cu 배선기술이 지금까지 도입되지 못한 가장 큰 요인은 기술적 어려움 때문인데, Cu경우 식각기술이 개발되어 있지 못하고 층간절연막 매립의 어려움 때문에 기존의 플러그 및 패턴 공정은 사용하기 힘들며 듀얼 대머신(dual damascene)공정을 통해 배선이 이루어진다.The introduction of copper (Cu) in recent wiring technology offers a new alternative to overcome the disadvantages of Al. However, the biggest factor that Cu wiring technology has not been introduced so far is due to technical difficulties. In the case of Cu, since the etching technology is not developed and the difficulty of embedding the interlayer insulating film, the existing plug and pattern process is difficult to use and the dual damascene Wiring is done through the process.
도 1a 내지 1c에 종래의 듀얼 대머신 공정을 나타내었다. 도 1a에 나타낸 바와 같이 기판(도시하지 않음)상에 형성된 제1산화막(1)위에 식각방지막으로서 질화막(2)을 증착한 후, 그위에 비아콘택 형성용 포토레지스트패턴(3)을 형성한다. 이어서 도 1b에 나타낸 바와 같이 상기 포토레지스트패턴(3)을 마스크로 이용하여 질화막(2)을 식각한 후, 그 전면에 제2산화막(3)을 형성한 다음, 그 상부에 금속라인 형성용 포토레지스트패턴(4)을 형성한다. 다음에 도 1c에 나타낸 바와 같이 상기 포토레지스트패턴(4)을 마스크로 이용하여 제2산화막(3)을 트렌치식각함과 동시에 제1산화막을 식각하여 비아콘택을 형성한다. 이때, 중간층인 질화막(2)이 비아 콘택홀 형성을 위한 식각방지막으로 사용되므로 산화막에 비해 높은 식각선택비를 가져야 한다. 특히 산화막의 두께가 증가함에 따라 20:1 이상의 높은 선택비가 필요하다. 그러나 이때 질화막에 대한 산화막의 선택비는 제1산화막의 두께만큼 식각이 필요하므로 높은 선택비를 얻어야 한다.1A to 1C show a conventional dual damascene process. As shown in FIG. 1A, a nitride film 2 is deposited as an etch stop film on a first oxide film 1 formed on a substrate (not shown), and then a photoresist pattern 3 for via contact formation is formed thereon. Subsequently, as shown in FIG. 1B, after the nitride film 2 is etched using the photoresist pattern 3 as a mask, a second oxide film 3 is formed on the entire surface thereof, and then a metal line forming photo is formed thereon. The resist pattern 4 is formed. Next, as shown in FIG. 1C, the second oxide film 3 is trench-etched using the photoresist pattern 4 as a mask and the first oxide film is etched to form via contacts. In this case, since the nitride layer 2, which is an intermediate layer, is used as an etch stop layer for forming a via contact hole, the nitride layer 2 should have a higher etching selectivity than the oxide layer. In particular, as the thickness of the oxide film is increased, a high selectivity of 20: 1 or more is required. However, at this time, the selectivity of the oxide film to the nitride film needs to be etched as much as the thickness of the first oxide film.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 기존에 사용하던 고선택비를 요구하는 층간 식각방지층을 제거하고 플러그를 도입하여 충진율과 유전율을 증가시킬 수 있도록 하는 듀얼 대머신 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems, and provides a dual damascene forming method that can increase the filling rate and the dielectric constant by removing the interlayer etch stop layer that requires a high selectivity, and introducing a plug used in the existing There is a purpose.
상기 목적을 달성하기 위한 본 발명의 반도체소자의 듀얼 대머신 형성방법은 하부구조물층상에 절연막을 형성하는 단계와, 상기 절연막 상부에 소정의 비아콘택 마스크패턴을 형성하는 단계, 상기 마스크패턴을 이용하여 상기 절연막을 식각하여 상기 하부구조물층을 노출시키는 비아콘택을 형성하는 단계, 상기 마스크패턴을 제거하는 단계, 상기 비아콘택내에 금속을 매립하여 금속 플러그를 형성하는 단계, 상기 절연막상의 소정부분에 금속라인 패턴을 형성하는 단계, 상기 금속라인 패턴을 따라 상기 절연막을 트렌치 식각하여 듀얼 대머신구조를 형성하는 단계를 포함한다.In order to achieve the above object, the dual damascene forming method of the semiconductor device of the present invention includes forming an insulating film on a lower structure layer, forming a predetermined via contact mask pattern on the insulating film, and using the mask pattern. Etching the insulating layer to form a via contact exposing the lower structure layer, removing the mask pattern, embedding a metal in the via contact to form a metal plug, and forming a metal line on a predetermined portion of the insulating layer Forming a pattern, and forming a dual damascene structure by trench etching the insulating layer along the metal line pattern.
도 1a 내지 1c는 종래 기술에 의한 반도체소자의 듀얼 대머신공정을 나타낸 공정순서도,1A to 1C are process flowcharts illustrating a dual damascene process of a semiconductor device according to the prior art;
도 2a 내지 2e는 본 발명에 의한 반도체소자의 듀얼 대머신공정을 나타낸 공정순서도.Figures 2a to 2e is a process flow chart showing a dual damascene process of the semiconductor device according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
20.하부구조물 21.절연막(산화막)20.Substructure 21.Insulation film (oxide)
22.비아콘택 마스크패턴 23.금속플러그22.via contact mask pattern 23.metal plug
24.금속라인 마스크패턴 25.금속배선24. Metal line mask pattern 25. Metal wiring
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 2e에 본 발명에 의한 반도체소자의 듀얼 대머신공정을 그 순서에 따라 도시하였다.2A to 2E illustrate the dual damascene process of the semiconductor device according to the present invention in that order.
먼저, 도 2a를 참조하면, 하부구조물층(20)상에 절연막인 산화막(21)을 형성하고, 소정의 비아콘택 마스크패턴(22)을 상기 산화막(21)상에 형성한다. 상기 산화막(21) 대신에 k가 낮은 물질로 절연막을 형성할 수도 있다.First, referring to FIG. 2A, an oxide film 21 as an insulating film is formed on the lower structure layer 20, and a predetermined via contact mask pattern 22 is formed on the oxide film 21. Instead of the oxide film 21, an insulating film may be formed of a material having a low k.
이어서 도 2b에 나타낸 바와 같이 상기 마스크패턴(22)을 이용하여 상기 산화막(21)을 식각하여 상기 하부구조물층(20)을 노출시키는 비아콘택을 형성한 후, 상기 마스크패턴을 제거하고 금속으로서, 예컨대 구리를 상기 비아콘택내에 매립하여 플러그(23)를 형성한다. 이때는 CMP적용이 필요치 않으며, 스텝 커버리지를 높일 수 있다. 상기 산화막 식각시에는 주반응가스로 C-F계를 사용하고 첨가가스로 CHF계를 사용하며 O2가스로 식각속도를 조절하는 건식식각을 이용하는 것이 바람직하다. 상기 금속플러그는 구리이외에 텅스텐, 알루미늄등을 사용하여 다층으로 형성할 수도 있다.Subsequently, as shown in FIG. 2B, the oxide layer 21 is etched using the mask pattern 22 to form a via contact exposing the substructure layer 20, and then the mask pattern is removed to form a metal. For example, copper is embedded in the via contact to form a plug 23. In this case, CMP application is not required, and step coverage can be increased. When the oxide film is etched, it is preferable to use a dry etching method using a C-F system as a main reaction gas, a CHF system as an additive gas, and controlling an etching rate with an O 2 gas. The metal plug may be formed in a multilayer using tungsten, aluminum, or the like in addition to copper.
다음에 도 2c에 나타낸 바와 같이 상기 산화막(21)상의 소정부분에 금속라인 패턴(24)을 형성한다.Next, as shown in FIG. 2C, a metal line pattern 24 is formed on a predetermined portion on the oxide film 21.
이어서 도 2d에 나타낸 바와 같이 상기 금속라인 패턴(24)을 따라 산화막(21)을 트렌치 식각한다. 이때, 구리 플러그(23)는 어느 정도 손상되어도 무관하다.Next, as illustrated in FIG. 2D, the oxide layer 21 is trench-etched along the metal line pattern 24. At this time, the copper plug 23 may be damaged to some extent.
다음에 도 2e에 나타낸 바와 같이 상기와 같이 형성된 듀얼 대머신구조에 금속으로서, 예컨대 구리를 증착하여 금속배선(25)을 완성한다.Next, as shown in FIG. 2E, the metal wiring 25 is completed by depositing, for example, copper as a metal on the dual damascene structure formed as described above.
이와 같이 함으로써 층간에 적용된 식각방지막으로 인한 유전율 감소를 해결하고 공정을 단순화시킨다.This solves the reduction in permittivity due to the etch barrier applied between the layers and simplifies the process.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
본 발명에 의하면, 기존의 듀얼 대머신공정에서 사용하던 층간 식각방지막을 제거함으로써 공정을 단순화시켜 생산성을 향상시킬 수 있으며, 유전율의 증가로 인하여 소자의 특성을 개선시킬 수 있다.According to the present invention, the productivity can be improved by simplifying the process by removing the interlayer etch barrier used in the conventional dual damascene process, and the characteristics of the device can be improved by increasing the dielectric constant.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990024808A KR100578223B1 (en) | 1999-06-28 | 1999-06-28 | Method of fabricating of dual damascene of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990024808A KR100578223B1 (en) | 1999-06-28 | 1999-06-28 | Method of fabricating of dual damascene of semiconductor device |
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| Publication Number | Publication Date |
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| KR20010004188A true KR20010004188A (en) | 2001-01-15 |
| KR100578223B1 KR100578223B1 (en) | 2006-05-12 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100404479B1 (en) * | 2001-06-21 | 2003-11-05 | 주식회사 하이닉스반도체 | Method for forming the dual damascene line |
| KR100891401B1 (en) * | 2007-06-28 | 2009-04-02 | 주식회사 하이닉스반도체 | Chemical mechanical polishing method of semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08335634A (en) * | 1995-06-08 | 1996-12-17 | Toshiba Corp | Manufacturing method for semiconductor device |
| KR19980040639A (en) * | 1996-11-29 | 1998-08-17 | 김광호 | Bit line formation method of semiconductor device |
| KR100219508B1 (en) * | 1996-12-30 | 1999-09-01 | 윤종용 | Forming method for matal wiring layer of semiconductor device |
| JPH11154703A (en) * | 1997-11-20 | 1999-06-08 | Toshiba Corp | Manufacture of semiconductor device |
-
1999
- 1999-06-28 KR KR1019990024808A patent/KR100578223B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100404479B1 (en) * | 2001-06-21 | 2003-11-05 | 주식회사 하이닉스반도체 | Method for forming the dual damascene line |
| KR100891401B1 (en) * | 2007-06-28 | 2009-04-02 | 주식회사 하이닉스반도체 | Chemical mechanical polishing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100578223B1 (en) | 2006-05-12 |
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