KR20000044892A - Method for forming metal wiring of semiconductor device - Google Patents

Method for forming metal wiring of semiconductor device Download PDF

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Publication number
KR20000044892A
KR20000044892A KR1019980061395A KR19980061395A KR20000044892A KR 20000044892 A KR20000044892 A KR 20000044892A KR 1019980061395 A KR1019980061395 A KR 1019980061395A KR 19980061395 A KR19980061395 A KR 19980061395A KR 20000044892 A KR20000044892 A KR 20000044892A
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South Korea
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metal wiring
interlayer insulating
forming
insulating film
photoresist pattern
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KR1019980061395A
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Korean (ko)
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여인석
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김영환
현대전자산업 주식회사
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Publication of KR20000044892A publication Critical patent/KR20000044892A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H

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Abstract

PURPOSE: A method for forming a metal wiring of a semiconductor device is provided to guarantee stabilization of a metal wiring process by improving a dual damascene pattern. CONSTITUTION: A method for forming a metal wire of a semiconductor device comprises the following steps. An interlayer dielectric(12) is formed on a substrate(11). A via contact hole for exposing the substrate is formed by etching a part of the interlayer dielectric. A photoresist is applied on the first interlayer dielectric including the via contact hole. A photoresist pattern is formed by patterning the photoresist. A second interlayer dielectric(15) is formed on the first interlayer dielectric including the photoresist pattern. A chemical mechanical polishing process is performed to expose an upper portion of the photoresist pattern. The exposed photoresist pattern is removed to form a trench and a via contact hole and a dual damascene pattern are formed therefrom. A metal wiring(16) is formed within the dual damascene pattern.

Description

반도체 소자의 금속 배선 형성 방법Metal wiring formation method of semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 비아 콘택홀과 트랜치를 갖는 듀얼 다마신 패턴(dual damascene pattern) 형성 공정을 개선하여, 금속 배선 형성 공정의 안정성 확보와 더불어 소자의 신뢰성 및 수율을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and in particular, to improve a process of forming a dual damascene pattern having a via contact hole and a trench, thereby ensuring the stability of the metal wiring forming process and the reliability of the device. A metal wiring formation method of a semiconductor element which can improve a yield.

일반적으로, 반도체 소자 형성 공정중 금속 배선은 구리, 알루미늄, 텅스텐 등과 같은 고전도성 물질을 증착한 후, 포토리소그라피(photolithography) 공정 및 식각 공정에 의해 형성한다. 이 경우 반도체 소자가 고집적화 및 소형화되어 감에 따라 포토레지스트의 애스팩트 비(aspect ratio)가 높아져 포토레지스트 패턴이 쓰러지거나, 건식 식각 후에 부식(corrosion) 발생 가능성 등의 문제점이 있다. 또한, 금속 배선 재료가 바뀔 때마다 새로운 식각 레시피를 개발해야 하는 번거로움이 있고, 특히 구리는 휘발성이 낮은 화합물을 형성하므로 건식 식각이 어렵다. 이러한 문제를 해결하기 위해 최근 개발된 방법으로 싱글 다마신(single damascene) 방법을 개선한 듀얼 다마신 방법이 있다. 듀얼 다마신 방법은 제 1 절연막 및 식각 정지층을 형성한 후에 포토리소그라피 공정 및 식각 공정으로 식각 정지층의 일부분을 식각 하여 비아 콘택홀이 형성될 부분을 정의(define)하고, 그 상부에 제 2 절연막을 형성한 후, 다시 포토리소그라피 공정 및 식각 공정으로 트랜치 및 비아 콘택홀을 형성하여 듀얼 다마신 패턴을 형성한다. 이후 듀얼 다마신을 포함한 제 2 절연막 상에 금속 증착 및 화학 기계적 연마 공정으로 금속층을 연마하여 금속 배선을 형성한다. 상기한 듀얼 다마신 방법은 포토리소그라피 공정과 식각 공정을 2번 실시하여 듀얼 다마신 패턴을 형성하는데, 이때 포토레지스트 패턴의 애스팩트 비가 높을 경우 포토레지스트 패턴이 쓰러지는 문제가 존재하고, 더욱이 상하부 절연막이 모두 산화물(oxide) 계통이므로 건식 식각시 정확한 식각 정지점을 조절하기 어려워 금속 배선의 두께를 정확히 조절할 수 없어, 결국 금속 배선 형성 공정의 안정성이 부족하고 소자의 신뢰성 및 수율 저하를 초래하는 문제가 있다.In general, the metal wiring during the semiconductor device forming process is formed by depositing a highly conductive material such as copper, aluminum, tungsten, etc., by a photolithography process and an etching process. In this case, as the semiconductor devices are highly integrated and miniaturized, the aspect ratio of the photoresist increases, resulting in the photoresist pattern falling down or the possibility of corrosion after dry etching. In addition, it is cumbersome to develop a new etching recipe every time the metal wiring material is changed, and in particular, dry etching is difficult because copper forms a compound having low volatility. To solve this problem, a recently developed method is the dual damascene method, which is an improvement of the single damascene method. In the dual damascene method, after forming the first insulating layer and the etch stop layer, a portion of the etch stop layer is etched by the photolithography process and the etch process to define a portion where the via contact hole is to be formed, and a second portion thereon. After the insulating film is formed, trenches and via contact holes are again formed by a photolithography process and an etching process to form a dual damascene pattern. Thereafter, the metal layer is polished on the second insulating film including dual damascene by metal deposition and chemical mechanical polishing to form a metal wiring. In the dual damascene method, a dual damascene pattern is formed by performing a photolithography process and an etching process twice. In this case, when the aspect ratio of the photoresist pattern is high, there is a problem that the photoresist pattern collapses. Since all are oxides, it is difficult to precisely control the etch stop point during dry etching, so that the thickness of the metal wiring cannot be precisely controlled, resulting in a lack of stability of the metal wiring forming process and a decrease in reliability and yield of devices. .

따라서, 본 발명은 비아 콘택홀과 트랜치를 갖는 듀얼 다마신 패턴 형성 공정을 개선하여 상기한 문제점을 해결하므로써, 금속 배선 형성 공정의 안정성 확보와 더불어 소자의 신뢰성 및 수율을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention solves the above problems by improving the dual damascene pattern forming process having via contact holes and trenches, thereby ensuring the stability of the metal wiring forming process and improving the reliability and yield of the device. It is an object to provide a method for forming metal wiring.

이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 형성 방법은 기판 상에 제 1 층간 절연막을 형성한 후, 상기 제 1 층간 절연막의 일부분을 식각 하여 상기 기판이 노출되는 비아 콘택홀을 형성하는 단계; 상기 비아 콘택홀을 포함한 제 1 층간 절연막 상에 포토레지스트 물질을 도포한 후 패터닝하여 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 포함한 제 1 층간 절연막 상에 제 2 층간 절연막을 형성하는 단계; 상기 포토레지스트 패턴의 상부가 노출되도록 화학 기계적 연마 공정으로 상기 제 2 층간 절연막을 연마하는 단계; 상기 노출된 포토레지스트 패턴을 제거하여 트랜치를 형성하고, 이로 인하여 상기 비아 콘택홀과 함께 듀얼 다마신 패턴이 형성되는 단계; 및 상기 듀얼 다마신 패턴 내에 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a metal wiring forming method of a semiconductor device of the present invention forms a first interlayer insulating film on a substrate, and then forms a via contact hole through which the substrate is exposed by etching a portion of the first interlayer insulating film. step; Forming a photoresist pattern by coating and patterning a photoresist material on the first interlayer insulating layer including the via contact hole; Forming a second interlayer insulating film on the first interlayer insulating film including the photoresist pattern; Polishing the second interlayer insulating layer by a chemical mechanical polishing process to expose an upper portion of the photoresist pattern; Forming a trench by removing the exposed photoresist pattern, thereby forming a dual damascene pattern together with the via contact hole; And forming a metal line in the dual damascene pattern.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11: 기판 12: 제 1 층간 절연막11: substrate 12: first interlayer insulating film

13: 듀얼 다마신 패턴 13A: 비아 콘택홀13: Dual damascene pattern 13A: Via contact hole

13B: 트랜치 14: 포토레지스트 패턴13B: trench 14: photoresist pattern

15: 제 2 층간 절연막 16: 금속 배선15: second interlayer insulating film 16: metal wiring

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1F are cross-sectional views of devices for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 기판(11)상에 제 1 층간 절연막(12)을 형성한다. 포토리소그라피 공정 및 식각 공정으로 제 1 층간 절연막(12)의 일부분을 식각 하여 기판(11)이 노출되는 비아 콘택홀(13A)을 형성한다.Referring to FIG. 1A, a first interlayer insulating layer 12 is formed on a substrate 11. A portion of the first interlayer insulating layer 12 is etched through a photolithography process and an etching process to form a via contact hole 13A through which the substrate 11 is exposed.

상기에서, 기판(11)은 웰 및 접합부가 형성된 반도체 기판이거나, 다층 금속 배선 구조에서 하부 금속 배선이거나, 반도체 소자의 전극으로 사용되는 도전성 패턴을 포함하고 있다. 제 1 층간 절연막(12)은 산화질화물(oxynitride), 화학기상증착 산화물(CVD oxide), 실리콘나이트라이드(Si3N4) 등과 같은 절연물을 적어도 어느 하나를 사용하여 1000 내지 10000Å의 두께로 증착 하여 형성된다.In the above, the substrate 11 is a semiconductor substrate on which wells and junctions are formed, a lower metal wiring in a multilayer metal wiring structure, or includes a conductive pattern used as an electrode of a semiconductor device. The first interlayer insulating film 12 is formed by depositing an insulator such as oxynitride, CVD oxide, silicon nitride (Si 3 N 4 ) and the like to have a thickness of 1000 to 10000 μs by using at least one of them. Is formed.

도 1b를 참조하면, 비아 콘택홀(13A)을 포함한 제 1 층간 절연막(12)상에 포토레지스트 물질을 도포한 후 패터닝하여 포토레지스트 패턴(14)을 형성한다.Referring to FIG. 1B, a photoresist material is coated on the first interlayer insulating layer 12 including the via contact hole 13A and then patterned to form a photoresist pattern 14.

상기에서, 포토레지스트 패턴(14)은 포토레지스트 물질을 4000 내지 12000Å의 두께로 도포한 후 현상하여 형성된다. 포토레지스트 패턴(14)은 금속 배선이 형성될 부분과 금속 배선의 폭 및 높이를 정의(define)한다.In the above, the photoresist pattern 14 is formed by applying a photoresist material to a thickness of 4000 to 12000 kPa and then developing. The photoresist pattern 14 defines the portion where the metal wiring is to be formed and the width and height of the metal wiring.

도 1c를 참조하면, 포토레지스트 패턴(14)을 포함한 제 1 층간 절연막(12)상에 극저온의 산화막을 증착 하여 제 2 층간 절연막(15)을 형성한다.Referring to FIG. 1C, a cryogenic oxide film is deposited on the first interlayer insulating layer 12 including the photoresist pattern 14 to form a second interlayer insulating layer 15.

상기에서 극저온 산화막은 APL(advanced planarization layer) 또는 PECVD를 사용하며, SOG를 사용할 수 있다. 극저온 산화막의 증착 온도는 200℃ 이하이다.The cryogenic oxide layer may use an advanced planarization layer (APL) or PECVD, and SOG may be used. The deposition temperature of the cryogenic oxide film is 200 ° C. or less.

도 1d를 참조하면, 포토레지스트 패턴(14)의 상부가 노출되도록 화학 기계적 연마(CMP) 공정으로 제 2 층간 절연막(15)을 연마한다.Referring to FIG. 1D, the second interlayer insulating layer 15 is polished by a chemical mechanical polishing (CMP) process so that the upper portion of the photoresist pattern 14 is exposed.

도 1e를 참조하면, 노출된 포토레지스트 패턴(14)을 제거하여 트랜치(13B)를 형성하고, 이로 인하여 최초 형성된 비아 콘택홀(13A)과 함께 듀얼 다마신 패턴(dual damascene pattern; 13)이 완성된다.Referring to FIG. 1E, the trench 13B is formed by removing the exposed photoresist pattern 14, thereby completing the dual damascene pattern 13 together with the first via contact hole 13A. do.

상기에서, 포토레지스트 패턴(14)은 건식 식각, 습식 식각 또는 건식 및 습식 식각의 혼합에 의해 제거한다.In the above, the photoresist pattern 14 is removed by dry etching, wet etching, or a mixture of dry and wet etching.

도 1f를 참조하면, 비아 콘택홀(13A)과 트랜치(13B)로 이루어진 듀얼 다마신 패턴(13)을 포함한 제 2 층간 절연막(15)상에 금속층 증착 및 화학 기계적 연마 공정으로 듀얼 다마신 패턴(13) 내에 금속 배선(16)을 형성한다.Referring to FIG. 1F, a dual damascene pattern may be formed by depositing a metal layer on a second interlayer insulating layer 15 including a dual damascene pattern 13 including a via contact hole 13A and a trench 13B and performing a chemical mechanical polishing process. The metal wiring 16 is formed in 13).

상기에서, 금속층 증착 공정 전에 극저온 산화막으로 된 제 2 층간 절연막(15)을 열처리하여 막질을 치밀화(densification)시킨다. 금속 배선(16)은 텅스텐, 알루미늄, 구리 등의 금속 물질을 PVD 또는 CVD 방법으로 증착 하여 형성된다. 금속 배선(16)은 확산 장벽층, 반사방지막을 포함한 복수층으로 구성시킬 수 있다.In the above, the second interlayer insulating film 15 made of the cryogenic oxide film is heat treated before the metal layer deposition process to densify the film quality. The metal wiring 16 is formed by depositing a metal material such as tungsten, aluminum, copper, or the like by PVD or CVD. The metal wiring 16 can be composed of a plurality of layers including a diffusion barrier layer and an antireflection film.

상술한 바와 같이, 본 발명은 제 1 층간 절연막에 먼저 비아 콘택홀을 형성한 후에 포토레지스트 패턴을 이용하여 금속 배선이 형성될 부분과 금속 배선의 폭 및 높이를 정의하고, 극저온의 산화막을 증착한 후 포토레지스트 패턴의 상부가 노출되도록 화학 기계적 연마(CMP) 공정으로 제 2 층간 절연막을 연마하고, 포토레지스트 패턴을 제거하여 트랜치를 형성하므로 비아 콘택홀과 함께 듀얼 다마신 패턴을 형성시키므로써, 기존의 듀얼 다마신 패턴 형성 공정에 있어 식각 마스크로 사용되는 포토레지스트 패턴의 부러짐 현상 및 트랜치의 깊이를 정확히 제어하기 어려운 문제를 해결할 수 있고, 공정 또한 단순하여 금속 배선 형성 공정의 안정성 확보와 더불어 소자의 신뢰성 및 수율을 향상시킬 수 있다.As described above, the present invention defines the width and height of the metal wiring and the portion where the metal wiring is to be formed by using the photoresist pattern after forming the via contact hole in the first interlayer insulating film, and depositing the cryogenic oxide film. After the second interlayer insulating film is polished by a chemical mechanical polishing (CMP) process to expose the upper portion of the photoresist pattern, and a trench is formed by removing the photoresist pattern, a dual damascene pattern is formed together with the via contact hole. In the dual damascene pattern formation process of the photoresist pattern used as an etch mask, it is possible to solve the problem of difficulty in precisely controlling the depth of the trench and the process is simple. Reliability and yield can be improved.

Claims (7)

기판 상에 제 1 층간 절연막을 형성한 후, 상기 제 1 층간 절연막의 일부분을 식각 하여 상기 기판이 노출되는 비아 콘택홀을 형성하는 단계;After forming a first interlayer insulating film on a substrate, etching a portion of the first interlayer insulating film to form a via contact hole through which the substrate is exposed; 상기 비아 콘택홀을 포함한 제 1 층간 절연막 상에 포토레지스트 물질을 도포한 후 패터닝하여 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern by coating and patterning a photoresist material on the first interlayer insulating layer including the via contact hole; 상기 포토레지스트 패턴을 포함한 제 1 층간 절연막 상에 제 2 층간 절연막을 형성하는 단계;Forming a second interlayer insulating film on the first interlayer insulating film including the photoresist pattern; 상기 포토레지스트 패턴의 상부가 노출되도록 화학 기계적 연마 공정으로 상기 제 2 층간 절연막을 연마하는 단계;Polishing the second interlayer insulating layer by a chemical mechanical polishing process to expose an upper portion of the photoresist pattern; 상기 노출된 포토레지스트 패턴을 제거하여 트랜치를 형성하고, 이로 인하여 상기 비아 콘택홀과 함께 듀얼 다마신 패턴이 형성되는 단계; 및Forming a trench by removing the exposed photoresist pattern, thereby forming a dual damascene pattern together with the via contact hole; And 상기 듀얼 다마신 패턴 내에 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.Forming a metal wiring in the dual damascene pattern. 제 1 항에 있어서,The method of claim 1, 상기 기판은 웰 및 접합부가 형성된 반도체 기판이거나, 다층 금속 배선 구조에서 하부 금속 배선이거나, 반도체 소자의 전극으로 사용되는 도전성 패턴을 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The substrate is a semiconductor substrate formed with a well and a junction, or a lower metal wiring in a multi-layer metal wiring structure, or a metal wiring forming method comprising a conductive pattern used as an electrode of the semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 제 1 층간 절연막은 산화질화물, 화학기상증착 산화물, 실리콘나이트라이드와 같은 절연물을 적어도 어느 하나를 사용하여 1000 내지 10000Å의 두께로 증착 하여 형성되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The first interlayer insulating film is formed by depositing an insulating material such as oxynitride, chemical vapor deposition oxide, silicon nitride to a thickness of 1000 to 10000 Å using at least one of the metal wirings forming method of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 포토레지스트 패턴은 상기 금속 배선이 형성될 부분과 금속 배선의 폭 및 높이를 정의하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the photoresist pattern defines a portion where the metal wiring is to be formed and a width and a height of the metal wiring. 제 1 항에 있어서,The method of claim 1, 상기 제 2 층간 절연막은 극저온 산화막인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the second interlayer insulating film is a cryogenic oxide film. 제 1 항에 있어서,The method of claim 1, 상기 제 2 층간 절연막은 APL, PECVD, SOG중 어느 하나를 사용하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the second interlayer insulating film is any one of APL, PECVD, and SOG. 제 1 항에 있어서,The method of claim 1, 상기 금속 배선은 텅스텐, 알루미늄, 구리와 같은 금속 물질을 PVD법이나 CVD법으로 증착 하여 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The metal wiring is formed by depositing a metal material such as tungsten, aluminum, copper by PVD method or CVD method.
KR1019980061395A 1998-12-30 1998-12-30 Method for forming metal wiring of semiconductor device KR20000044892A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379551B1 (en) * 2001-03-09 2003-04-10 주식회사 하이닉스반도체 Method for Fabricating of Semiconductor Device Using the Dual Damascene Process
KR20030080317A (en) * 2002-04-08 2003-10-17 동부전자 주식회사 Method for fabricating damascene pattern of smiconductor
KR100431086B1 (en) * 2002-07-11 2004-05-12 주식회사 하이닉스반도체 Method of forming a copper wiring in a semiconductor device
KR100735479B1 (en) * 2005-10-28 2007-07-03 동부일렉트로닉스 주식회사 Fabricating method of Metal line in semiconductor device
KR100788380B1 (en) 2006-09-29 2008-01-02 동부일렉트로닉스 주식회사 Method for forming semiconductor device
KR100799068B1 (en) 2006-12-21 2008-01-29 동부일렉트로닉스 주식회사 The fabricating method of semiconductor device
KR100874829B1 (en) * 2006-12-26 2008-12-19 동부일렉트로닉스 주식회사 Metal wiring formation method of semiconductor device
KR100905996B1 (en) * 2002-06-29 2009-07-06 주식회사 하이닉스반도체 Method for fabricating semiconductor device using dual damascene process

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379551B1 (en) * 2001-03-09 2003-04-10 주식회사 하이닉스반도체 Method for Fabricating of Semiconductor Device Using the Dual Damascene Process
KR20030080317A (en) * 2002-04-08 2003-10-17 동부전자 주식회사 Method for fabricating damascene pattern of smiconductor
KR100905996B1 (en) * 2002-06-29 2009-07-06 주식회사 하이닉스반도체 Method for fabricating semiconductor device using dual damascene process
KR100431086B1 (en) * 2002-07-11 2004-05-12 주식회사 하이닉스반도체 Method of forming a copper wiring in a semiconductor device
KR100735479B1 (en) * 2005-10-28 2007-07-03 동부일렉트로닉스 주식회사 Fabricating method of Metal line in semiconductor device
KR100788380B1 (en) 2006-09-29 2008-01-02 동부일렉트로닉스 주식회사 Method for forming semiconductor device
KR100799068B1 (en) 2006-12-21 2008-01-29 동부일렉트로닉스 주식회사 The fabricating method of semiconductor device
KR100874829B1 (en) * 2006-12-26 2008-12-19 동부일렉트로닉스 주식회사 Metal wiring formation method of semiconductor device

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