KR100447322B1 - Method of forming a metal line in semiconductor device - Google Patents
Method of forming a metal line in semiconductor device Download PDFInfo
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- KR100447322B1 KR100447322B1 KR10-2001-0085346A KR20010085346A KR100447322B1 KR 100447322 B1 KR100447322 B1 KR 100447322B1 KR 20010085346 A KR20010085346 A KR 20010085346A KR 100447322 B1 KR100447322 B1 KR 100447322B1
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000002184 metal Substances 0.000 title claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims description 23
- 239000010410 layer Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 abstract description 5
- 239000007791 liquid phase Substances 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 230000009977 dual effect Effects 0.000 description 8
- 229920000642 polymer Polymers 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 241000723353 Chrysanthemum Species 0.000 description 1
- 235000005633 Chrysanthemum balsamita Nutrition 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000035622 drinking Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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Abstract
반도체 소자의 메탈 라인 형성 방법에 관한 것으로, 층간절연막 형성시 플라즈마를 이용하지 않고 선택적 LPD(Liquid Phase Deposition)공정을 이용하여 절연막을 증착함으로써 공정을 단순화하고 기생 정전용량을 감소시킬 수 있는 반도체 소자의 메탈 라인 형성 방법을 제공한다.The present invention relates to a method of forming a metal line of a semiconductor device, and to forming an insulating film using a selective liquid phase deposition (LPD) process instead of using a plasma to form an interlayer insulating film, which can simplify the process and reduce parasitic capacitance. Provided is a method of forming a metal line.
Description
본 발명은 반도체 소자의 메탈 라인 형성 방법에 관한 것으로, 듀얼다마신 공정을 이용하여 메탈라인을 형성하는데 있어서 플라즈마를 이용하여 층간절연막을 형성하지 않고 선택적 LPD(Liquid Phase Deposition)공정을 이용하여 층간 절연막을 형성함으로써 공정의 단순화 및 기생정전용량을 감소시킬 수 있는 반도체 소자의 메탈 라인 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal line of a semiconductor device, and to forming a metal line using a dual damascene process, an interlayer insulating film using a selective liquid phase deposition (LPD) process without forming an interlayer insulating film using plasma. The present invention relates to a method for forming a metal line of a semiconductor device capable of simplifying the process and reducing the parasitic capacitance.
CMOS 로직 디바이스(CMOS Logic device)에서는 게이트 길이(Gate length)가 감소함에 따라 게이트 딜레이타임(Gate delay time)을 줄임으로써 스피드(Speed)를 증가 시켰다. 하지만 디바이스가 집적화 될수록 BEOL(Back End of Line) 메탈라이제이션(Metalization)에 의한 RC(Resistance Capacitance) 딜레이(Delay)가 디바이스 스피드(Device Speed)를 좌우하게 된다.In a CMOS logic device, as the gate length decreases, the speed is increased by reducing the gate delay time. However, as devices are integrated, the device speed is determined by the delay (RC) delay due to back end of line (BEOL) metallization.
이러한 RC 딜레이를 줄이기 위해 저항이 낮은 구리(Cu)를 메탈(Metal)로 사용하고 유전체(Dielectric)로는 낮은 유전율의 물질을 사용하여 비아홀(Via hole)과 메탈배선을 동시에 형성하는 듀얼 다마신(Dual Damascene) 방법을 사용한다.To reduce this RC delay, dual damascene is used to form via holes and metal wires simultaneously using low-resistance copper (Cu) as metal and low-dielectric materials as dielectric. Damascene) method.
듀얼 다마신을 형성하는 방법은 여러 가지가 있다. 일반적으로 층간 절연막은 플라즈마를 이용하여 형성하게된다. 이때 비아홀과 트랜치(Trench)를 형성하기 위해서는 반드시 플라즈마 에칭(Plasma Etching)공정이 필요하다. 그러나 플라즈마 에칭(Plasma Etching)시 플라즈마 형성이 불안정할 경우 소자에 플라즈마 데미지(Plasma Damage)를 유발하게 되어 소자특성을 악화시키는 결과를 초래하게 된다.There are several ways to form dual damascene. In general, the interlayer insulating film is formed using plasma. In this case, in order to form the via hole and the trench, a plasma etching process is required. However, if plasma formation is unstable during plasma etching, plasma damage may occur to the device, resulting in deterioration of device characteristics.
또한 에칭공정 진행을 위하여 각 에칭 공정마다 필름(Film)증착, 포토마스크(Phot mask), 포토레지스트 스트립(Photo resist strip) 및 크리닝(Cleaning)공정이 필요함으로 공정 스텝(Step)이 증가하게 된다.In addition, in order to proceed with the etching process, a film deposition process, a photo mask, a photo resist strip, and a cleaning process are required for each etching process, thereby increasing the process step.
일반적으로 메탈라인(Metal line)을 형성하기 위하여 트랜치 식각시 식각 정지층과 층간 절연막(SiO2)의 선택비를 높이기 위해 식각 정지층으로는 Si3N4를 사용한다. 하지만 층간 절연막의 유전상수는 약 4 인데 비해 Si3N4는 유전상수가 약 7로써 식각 정지층이 층간 절연막보다 높은 유전율을 가지게 된다. 이로 인해 인터 커패시턴스(Inter capacitance)가 증가되어 디바이스 특성을 악화시킨다.In general, Si 3 N 4 is used as the etch stop layer to increase the selectivity between the etch stop layer and the interlayer insulating layer (SiO 2 ) during the trench etching to form a metal line. However, the dielectric constant of the interlayer insulating film is about 4, whereas Si 3 N 4 has a dielectric constant of about 7, and the etch stop layer has a higher dielectric constant than the interlayer insulating film. This increases inter capacitance, which degrades device characteristics.
따라서 본 발명은 상술한 단점을 해소할 수 있는 반도체 소자의 메탈 라인 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal line of a semiconductor device that can solve the above-mentioned disadvantages.
본 발명의 다른 목적은 메탈라인을 위한 층간 절연막 형성시 플라즈마를 이용하지 않고 상온에서 침적 방법에 의해 선택적으로 절연막을 증착함으로써 공정을 단순화할 수 있는 반도체 소자의 메탈 라인 형성 방법을 제공하는데 그 목적이 있다.Another object of the present invention is to provide a method for forming a metal line of a semiconductor device capable of simplifying the process by selectively depositing an insulating film by deposition method at room temperature without using plasma when forming an interlayer insulating film for metal lines. have.
본 발명의 특징에 의하면, 유전율이 높은 식각정지층을 형성하지 않음으로써 기생정전용량을 감소시킬 수 있다.According to a feature of the present invention, the parasitic capacitance can be reduced by not forming an etch stop layer having a high dielectric constant.
도 1a 내지 1g는 본 발명에 따른 듀얼 다마신 공정을 이용한 반도체 소자의 메탈라인 형성 방법을 설명하기 위한 단면도.1A to 1G are cross-sectional views illustrating a metal line forming method of a semiconductor device using a dual damascene process according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 : 하지층 2, 5, 9 : 절연막1: base layer 2, 5, 9: insulating film
3, 10 : 메탈 4a, 4b : 질화막3, 10: metal 4a, 4b: nitride film
6, 8 : 포토레지스트 7 : 비아홀6, 8: photoresist 7: via hole
싱글 다마신공정을 이용하여 하지층 상에 제 1 메탈라인을 형성하는 단계, 상기 제 1 메탈라인을 포함한 전체 구조상부에 질화막을 형성하는 단계, 상기 질화막 상부에 제 1 절연막을 증착한 후 상기 제 1 절연막을 패터닝하여 비아홀을 형성하는 단계, 패터닝된 상기 제 1 절연막 상부에 제 2 절연막이 선택적으로 형성되어 그로 인하여 트랜치가 형성되는 단계, 상기 비아홀 하부의 상기 질화막을 제거하는 단계 및 상기 전체 기판상부에 메탈을 증착하여 상기 제 1 메탈라인과 연결되는 제 2 메탈라인을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 메탈 라인 형성 방법을 제공한다.Forming a first metal line on the underlying layer using a single damascene process, forming a nitride film on the entire structure including the first metal line, depositing a first insulating film on the nitride film, and then Patterning an insulating film to form a via hole, selectively forming a second insulating film over the patterned first insulating film, thereby forming a trench, removing the nitride film under the via hole, and over the entire substrate Forming a second metal line connected to the first metal line by depositing a metal to provide a method for forming a metal line of a semiconductor device.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 1g는 본 발명에 따른 듀얼 다마신 공정을 이용한 반도체 소자의 메탈라인 형성 방법을 설명하기 위한 단면도이다.1A to 1G are cross-sectional views illustrating a metal line forming method of a semiconductor device using a dual damascene process according to the present invention.
도 1a는 싱글 다마신(Single damascene)공정을 이용하여 제 1 메탈라인(Copper line)(3)이 형성된 상태의 단면도이다. 제 1 절연막(2)으로는 산화막을, 제 1 메탈라인(3)으로는 구리를 사용한다. 참조 부호(1)는 하지층을 나타내며, 참조부호(4a)는 제 1 질화막을 나타낸다. 제 1 메탈라인(3)이 형성된 전체구조 상부에 제 1 메탈라인(3)의 확산을 막기 위한 하부캐핑용 제 2 질화막(Bottom capping nitride)(4b)이 약 500Å의 두께로 증착된다.1A is a cross-sectional view of a state in which a first metal line 3 is formed using a single damascene process. An oxide film is used as the first insulating film 2 and copper is used as the first metal line 3. Reference numeral 1 denotes an underlayer, and reference numeral 4a denotes a first nitride film. A bottom capping nitride 4b for lower capping to prevent diffusion of the first metal line 3 is deposited on the entire structure on which the first metal line 3 is formed to a thickness of about 500 GPa.
도 1b에 도시한 바와 같이, 전체 구조상부에 제 2 절연막(5)을 증착다. 제 2 절연막(5)상에 포토레지스트(Photoresist)를 도포한 후 비아 포토 마스크(Via Photomask)를 이용한 노광공정을 실시하여 비아용 포토 마스크 패턴(Photomaskpattern)(6)을 형성한다.As shown in Fig. 1B, the second insulating film 5 is deposited on the entire structure. After the photoresist is applied on the second insulating film 5, an exposure process using a via photomask is performed to form a photomask pattern 6 for a via.
이때 제 2 절연막(5)은 PE CVD(Chemical vapor deposition)에 의해 형성된 산화막(SiO2)을 4000 내지 5000Å의 두께로 증착하여 형성된다.At this time, the second insulating film 5 is formed by depositing an oxide film (SiO 2 ) formed by PE CVD (Chemical Vapor Deposition) to a thickness of 4000 to 5000 Pa.
도 1c에 도시한 바와 같이, 상층 배선과 하층 배선을 연결하기 위하여 제 2 절연막(5)을 상기의 비아용 포토 마스크 패턴(6)을 이용하여 프라즈마 식각공정을 수행함으로써 비아홀(Via hole)(7)을 형성한다.As shown in FIG. 1C, in order to connect the upper layer wiring and the lower layer wiring, a via etching process is performed by using the second insulating film 5 using the above photo mask pattern 6 for vias. ).
이때 비아홀(7) 식각조건은 하부캐핑용 제 2 질화막(4b)과 제 2 절연막(5)의 식각 선택비를 높게 하는 조건으로 실시한다. 카본(Carbon)대 플루오린(Fluorine)의 비가 높은 C4F8또는 C5F8과 같은 가스를 사용하여 폴리머(Polymer)를 다량 발생시킬 수 있다. 그리고 하부온도를 20 내지 40℃로 진행하여 아래층(Under layer)에 증착되는 폴리머 구조를 카본(Carbon)성분이 많이 함유된 CFx폴리머 구조로 변화시킬 수 있다.At this time, the etching conditions of the via hole 7 are performed under the condition of increasing the etching selectivity of the second nitride film 4b and the second insulating film 5 for lower capping. A large amount of polymer may be generated by using a gas such as C 4 F 8 or C 5 F 8 having a high ratio of carbon to fluorine. The lower temperature may be increased to 20 to 40 ° C. to change the polymer structure deposited on the under layer to a CF x polymer structure containing a large amount of carbon.
또한 수소(Hydrogen)가 함유된 CH2F2가스를 첨가함으로써 플라즈마(Plasma)에 의해 발생된 프리 플루오린(Free fluorine)을 제거하는 수소의 특성을 이용하여 폴리머 발생을 유리하게 한다. 따라서 상기의 조건들에 의해 발생된 폴리머가 하부의 제 2 질화막(4b) 상부에 침적되어 제 2 질화막(4b)이 식각되는 것을 방지한다.In addition, by generating a CH 2 F 2 gas containing hydrogen (Hydrogen), the generation of the polymer is advantageous by utilizing the property of hydrogen to remove the free fluorine generated by the plasma (Plasma). Accordingly, the polymer generated by the above conditions is deposited on the lower portion of the second nitride film 4b to prevent the second nitride film 4b from being etched.
상기 비아홀(7)의 형성공정은 미디엄 이온 덴시티(Medium ion density)가 1E10 내지 1E11/㎤을 갖는 장비를 사용하여 실시되는데, 이때 30 내지 50mT의 압력, 1800 내지 2000와트의 소스파워(Source power)와 1500 내지 1700와트의 바이어스 파워(Bias power)를 가한 상태에서 수행된다. 또한 공급가스로는 15 내지 25sccm의 C5F8, 2 내지 3sccm의 CH2F2, 10 내지 20sccm의 O2및 400 내지 600sccm의 Ar이 사용된다.The formation process of the via hole 7 is performed using a device having a medium ion density of 1E10 to 1E11 / cm 3, wherein a pressure of 30 to 50 mT and a source power of 1800 to 2000 watts are used. ) And a bias power of 1500 to 1700 watts are applied. As the feed gas, C 5 F 8 of 15 to 25 sccm, CH 2 F 2 of 2 to 3 sccm, O 2 of 10 to 20 sccm, and Ar of 400 to 600 sccm are used.
상기 비아홀(7)의 종횡비는 기존의 듀얼 다마신공정에 의한 4 내지 5의 종횡비보다 낮은 2 내지 2.5로 낮아질 수 있다. 또한 상기 제 2 절연막(5)을 멀티필름스택(Multi film stack)구조 즉 ONO(Oxide/nitride/oxide)대신 단일 산화막으로 형성함으로써 식각조건 설정이 용이하다.The aspect ratio of the via hole 7 may be lowered to 2 to 2.5, which is lower than the aspect ratio of 4 to 5 by the conventional dual damascene process. In addition, since the second insulating film 5 is formed as a single oxide film instead of a multi film stack structure, that is, an oxide / nitride / oxide (ONO), etching conditions can be easily set.
바이어스드(Biased) O2플라즈마를 이용하여 비아용 포토 마스크 패턴과 상기의 식각공정시 발행하는 폴리머를 제거함과 동시에 바이어스 파워에 의한 스퍼터링(Sputtering)효과를 크게 하여 비아홀(7) 상단부에 간면(Faceting)을 유발한다. 이로써 후속의 트랜치 포토레지스트(Trench Photo Resist) 코팅(Coating)및 듀얼다마신 패터닝(Dual damascene patterning)후 메탈 증착시 스텝 커버리지를 개선함으로써 비아 저항을 개선할 수 있다.By using a biased O 2 plasma, the photo mask pattern for the via and the polymer issued during the etching process are removed, and the sputtering effect by the bias power is increased to face the upper portion of the via hole 7. Cause). This can improve via resistance by improving step coverage during metal deposition following subsequent trench photoresist coating and dual damascene patterning.
이때 레지스트 스트립(Resist strip)을 위해 100 내지 200mT의 압력, 1800 내지 2000와트의 소스파워와 300 내지 500와트의 바이어스 파워에서 200 내지 300sccm의 O2를 공급한다.At this time, 200 to 300 sccm of O 2 is supplied at a pressure of 100 to 200 mT, a source power of 1800 to 2000 watts, and a bias power of 300 to 500 watts for the resist strip.
도 1d에 도시한 바와 같이, 전체 구조 상부에 네거티브 포토레지스트(Negative photo resist)를 회전 도포방식을 이용하여 5000 내지 6000Å 코팅하여 비아홀(7)을 완전히 매립한다. 그리고 제 1 메탈라인을 형성하기 위한트랜치용 마스크를 이용한 노광 및 세정공정을 실시하여 제 2 절연막(5)의 일부를 노출시킨다.As shown in FIG. 1D, a negative photoresist is coated on the entire structure by using 5000 to 6000 microseconds by using a rotary coating method to completely fill the via hole 7. Then, a part of the second insulating film 5 is exposed by performing exposure and cleaning processes using a trench mask for forming the first metal line.
이는 도 1a의 싱글 다마신공정시 제 1 메탈라인을 형성하기 위한 트랜치와 역상이 된다. 구체적으로 네거티브 포토레지스트(8)와 트랜치용 마스크를 이용하여 구리라인이 형성된 상부에는 포토레지스트가 존재하고 제 1 절연막(2)이 형성된 상부에는 포토레지스트가 제거되어 트랜치가 형성된다.This is reversed to the trench for forming the first metal line in the single damascene process of FIG. 1A. In detail, a photoresist exists on the upper portion where the copper line is formed using the negative photoresist 8 and the trench mask, and a trench is formed by removing the photoresist on the upper portion where the first insulating layer 2 is formed.
도 1e에 도시한 바와 같이, 네거티브 포토레지스트(8)의 일부를 제거함으로써 형성된 트랜치가 제 3 절연막(9)에 의해 매립된다. 즉 선택적(Selective) LPD(Liquid Phase Deposition)공정을 수행하여 제 2 절연막(5)의 노출부에만 제 3 질화막(9)이 3500 내지 4000Å 두께로 형성된다.As shown in FIG. 1E, the trench formed by removing a part of the negative photoresist 8 is filled by the third insulating film 9. That is, the third nitride film 9 is formed to have a thickness of 3500 to 4000 kV only in the exposed portion of the second insulating film 5 by performing a selective liquid phase deposition (LPD) process.
LPD공정은 H3BO3가 첨가된 상온의 과포화 H2SiF6수용액에 반도체 기판을 침적하여 실리콘과 옥사이드 위에만 SiOF 즉, FSG(Fluorinate Silica Glass)를 성장시킨다. 이를 이용하여 노출된 제 2 절연막(5)에만 선택적으로 제 3 절연막(9)을 증착하고 네거티브 포토레지스트(8)가 존재하는 곳 즉 트렌치 라인이 형성될 부분에는 제 3 절연막(9) 성장이 이루어지지 않는다.In the LPD process, a semiconductor substrate is deposited on a supersaturated H 2 SiF 6 aqueous solution containing H 3 BO 3 to grow SiOF, that is, FSG (Fluorinate Silica Glass) on silicon and oxide. By using this, the third insulating film 9 is selectively deposited only on the exposed second insulating film 5, and the third insulating film 9 is grown where the negative photoresist 8 is present, that is, where the trench line is to be formed. I do not lose.
상기의 방법에 의해 유전율이 높은 식각정지층을 사용하지 않으므로 인터커패시턴스(Inter capacitance) 증가에 따른 디바이스 특성 악화를 막을 수 있다. 종래 기술의 식각정지층의 추가 증착 공정을 생략할 수 있으므로 공정 단순화를 할 수 있다. 트랜치 식각공정을 생략함으로써 식각에 따른 문제점인 고선택비의 식각조건을 필요하거나 폴리머제거를 위한 추가 세정에 대한 우려가 없고 공정을 단순화 할 수 있다. 플라즈마방법 대신 상온에서 침적 방법에 의해 제 3 절연막을 증착함으로써 플라즈마로 인한 데미지 발생이 없다.By using the above method, since the etch stop layer having a high dielectric constant is not used, deterioration of device characteristics due to an increase in inter capacitance can be prevented. Since the additional deposition process of the etch stop layer of the prior art can be omitted, the process can be simplified. By eliminating the trench etching process, there is no need for a high selectivity etching condition, which is a problem with etching, or there is no concern about additional cleaning for polymer removal, and the process can be simplified. There is no damage caused by plasma by depositing the third insulating film by the deposition method at room temperature instead of the plasma method.
도 1f에 도시한 바와 같이, O2플라즈마를 이용하여 포토레지스트(8)를 제거하여 메탈라인이 형성될 트랜치가 형성된다. 상기 트랜치 하부의 하부캐핑용 제 1 질화막(4)의 일부가 플라즈마 건식 식각방법에 의해 제거되어 제 1 메탈(3)이 노출된다.As shown in FIG. 1F, the trench in which the metal line is to be formed is formed by removing the photoresist 8 using an O 2 plasma. A portion of the first nitride film 4 for lower capping under the trench is removed by a plasma dry etching method to expose the first metal 3.
구체적으로 하부 캐핑용 제 1 질화막(4)의 제거공정은 제 1 질화막(4)과 산화막의 선택비가 약 1.5 : 1로 하여 듀얼 다마신 패턴을 왜곡시키지 않고 트랜치 라인 윗부분에 약간의 간면을 유발되도록 실시한다. 또한 하부캐핑용 제 2 질화막 (4b)식각공정은 제 1 메탈(13)이 노출되었을 때 백 스퍼터링(Back sputtering)에 의한 메탈베일(Veil)을 최소화하는 식각조건으로 실시한다.Specifically, in the removal process of the lower capping first nitride film 4, the selectivity ratio between the first nitride film 4 and the oxide film is about 1.5: 1 so that a slight interfacial surface is caused in the upper portion of the trench line without distorting the dual damascene pattern. Conduct. In addition, the etching process of the second nitride film 4b for lower capping is performed under an etching condition of minimizing a metal veil due to back sputtering when the first metal 13 is exposed.
식각 장비로는 미디엄 이온 덴시티(Medium ion density)가 1E10 내지 1E11/㎤을 갖는 장비를 사용하여, 50 내지 70mT의 압력, 800 내지 1200와트의 소스파워(Source power)와 200 내지 300와트의 바이어스 파워(Bias power)를 가한 상태에서 수행된다. 공급가스로는 50 내지 80sccm의 CF4, 10 내지 20sccm의 CHF2, 10 내지 20sccm의 O2및 400 내지 600sccm의 Ar이 사용된다.Etching equipment is a device having a medium ion density of 1E10 to 1E11 / cm 3, a pressure of 50 to 70mT, a source power of 800 to 1200W and a bias of 200 to 300W It is performed in the state of applying bias power. As the feed gas, CF 4 of 50 to 80 sccm, CHF 2 of 10 to 20 sccm, O 2 of 10 to 20 sccm and Ar of 400 to 600 sccm are used.
도 1g에 도시된 바와 같이, 식각시 발생된 폴리머를 제거하기 위하여 세정공정을 수행한 다음 전체 기판상부에 제 2 메탈을 증착한 후 제 3 절연막을 식각정지층으로하는 CMP공정을 수행하여 듀얼 다마신패턴을 형성한다.As shown in FIG. 1G, after the cleaning process is performed to remove the polymer generated during etching, the second metal is deposited on the entire substrate, followed by a CMP process using the third insulating layer as an etch stop layer. A drinking pattern is formed.
이와 같이 본발명에 의한 반도체 소자의 메탈 라인 형성 방법은 선택적 LPD(Liquid Phase Deposition)공정을 이용하여 절연막을 형성함으로써 플라즈마를 이용한 절연막증착 및 식각공정의 단계를 줄임으로 인해 공정의 단순화와 프라즈마 데이지 발생을 제거할 수 있다.As described above, the metal line forming method of the semiconductor device according to the present invention simplifies the process and generates plasma daisy by reducing the steps of the deposition and etching process using plasma by forming an insulating film using a selective liquid phase deposition (LPD) process. Can be removed.
또한 비아 식각시 종횡비를 낮게 함으로써 식각조건 설정을 유리하게 할 수 있다.In addition, it is advantageous to set the etching conditions by lowering the aspect ratio during the via etching.
또한 비아홀 형성 후 비아 홀의 상단부를 간면으로 형성시킴으로써 비아저항을 개선할 수 있다.In addition, the via resistance may be improved by forming the upper end of the via hole as an interfacial surface after the via hole is formed.
또한 층간 절연막보다 높은 유전율의 식각 정지층을 형성하지 않음으로써 기생정전용량을 감소시킬 수 있다.In addition, the parasitic capacitance can be reduced by not forming an etch stop layer having a higher dielectric constant than the interlayer insulating film.
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