KR100512051B1 - Method of forming a metal line in semiconductor device - Google Patents
Method of forming a metal line in semiconductor device Download PDFInfo
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- KR100512051B1 KR100512051B1 KR10-2003-0080040A KR20030080040A KR100512051B1 KR 100512051 B1 KR100512051 B1 KR 100512051B1 KR 20030080040 A KR20030080040 A KR 20030080040A KR 100512051 B1 KR100512051 B1 KR 100512051B1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 식각정지층을 갖는 다층의 금속배선 형성에 있어서, 상부의 저 유전율 절연막 형성전에 하부의 저 유전율 절연막을 플라즈마 이온 또는 가스 클러스터 이온을 이용한 표면처리를 통해 하부의 저 유전율 절연막 상에 계면층을 형성함으로써 저 유전율 절연막과 유사한 유전상수를 갖는 식각정지막을 형성할 수 있고, 저 유전율 절연막 매트릭스와 유사한 구조의 계면층을 형성하여 서로 다른 물질을 사용하는 것에 기인한 식각율차 또는 열팽창계수 차이의 문제없이 안정한 트렌치와 비아홀을 형성할 수 있으며, 금속배선의 BM 및 BTS 저항성을 갖는 신뢰성 있는 저유전율막 다층 구리 배선을 형성할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, wherein in forming a multi-layered metal wiring having an etch stop layer, a surface treatment using a plasma ion or a gas cluster ion is performed on a lower dielectric constant insulating film before forming an upper dielectric constant insulating film thereon. By forming an interfacial layer on the lower dielectric constant insulating layer through the etch stop film having a dielectric constant similar to that of the low dielectric constant insulating film, and forming an interface layer of a structure similar to the low dielectric constant insulating film matrix to use a different material Metal wiring formation of a semiconductor device capable of forming stable trenches and via holes without problems of etching rate differences or thermal expansion coefficients due to the above-mentioned material, and forming a reliable low-k film multilayer copper wiring having BM and BTS resistance of the metal wiring. Provide a method.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 저 유전율 절연막을 이용한 듀얼 다마신 공정에 있어서 금속배선용 트렌치 형성을 위해 사용되는 식각정지막에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to an etch stop film used for forming trenches for metal wiring in a dual damascene process using a low dielectric constant insulating film.
저유전율 절연막을 사용한 다마신 방법에 의한 다층의 금속배선 형성에 있어서, 비아 상부층에 금속 트렌치 식각정지막으로 질화막이나 실리콘 카바이드막 또는 이들의 혼합막을 증착하여 사용하고 있다. 하지만, 이들 막은 높은 유전 상수값을 갖고 있기 때문에 이로인한 전체 구리 배선 저 유전율막 구조의 실제 유전율(Effective k)값 상승의 문제와 실리콘 카바이드막에 존재하는 탄소성분에 의한 식각공정시 폴리머 생성에 따른 비아 불량등의 문제점이 발생한다. 또한, 식각 공정시 이들 층의 저 유전율막에 대한 식각율 차이에 의한 후속 구리 확산 방지 금속막의 증착불량이나 저 유전율막과의 열팽창 계수 차이에 의한 스트레스 마이그레이션(Stress Migration; SM), 편향된 온도 스트레스(Biased Temperature Stress; BTS) 불량 등의 신뢰성 악화의 원인이 된다. In forming a multi-layered metal wiring by the damascene method using a low dielectric constant insulating film, a nitride film, a silicon carbide film, or a mixed film thereof is deposited on the via upper layer by a metal trench etch stop film. However, since these films have high dielectric constant values, there is a problem of increasing the actual dielectric constant (k) value of the entire copper wiring low permittivity film structure and the formation of polymer during the etching process by the carbon component present in the silicon carbide film. Problems such as via failure occur. Also, during the etching process, stress migration (SM) due to poor deposition of subsequent copper diffusion preventing metal films due to the difference in etching rates of the low dielectric constant films of the layers or the difference in thermal expansion coefficient with the low dielectric constant films, deflection temperature stress ( Biased Temperature Stress (BTS) may cause deterioration of reliability such as failure.
물론, 낮은 유전율 달성을 위해 트렌치 형성시 식각정지막을 형성하지 않는 구조의 저 유전율 절연막 형성에 대한 연구도 진행되고 있으나, 양호한 트렌치 형상 및 한 웨이퍼 내에서 다양한 패턴 밀도를 갖는 비아홀 및 트렌치 구조의 균일한 프로파일을 얻는데는 한계가 있는 실정이다. Of course, the research on the formation of a low dielectric constant insulating film having a structure that does not form an etch stop film when forming a trench to achieve a low dielectric constant, but is a uniform trench hole and trench structure having a good trench shape and various pattern densities in one wafer There is a limit to obtaining a profile.
도 1은 종래 공정에 따라 형성된 금속배선의 단면도 이다. 1 is a cross-sectional view of a metal wiring formed according to a conventional process.
도 1을 참조하면, 하부 구리배선(12)이 형성된 반도체 기판(10) 상에 하부 구리배선(12)의 확산을 방지하기 위한 배리어막(14)을 형성한다. 제 1 저유전율 절연막(16), 트렌치 식각정지막(18) 및 제 2 저유전율 절연막(20)을 형성한다. 패터닝 공정을 통해 하부 구리 배선 상부의 제 2 저유전율 절연막(20), 식각정지막(18) 및 제 1 저유전율 절연막(16)을 식각하여 비아홀(미도시)을 형성한다. 패터닝 공정을 통해 비아홀 상부의 제 2 저 유전율 절연막(20)을 식각하여 트렌치(미도시)를 형성한다. 전체 구조의 단차를 따라 확산 방지막(22) 및 씨드막(미도시)을 증착한 다음, 금속 도금법을 이용하여 전체 구조상에 구리막을 형성한다. 평탄화 공정을 통해 제 2 저유전율 절연막(20) 상의 구리막을 제거하여 듀얼 다마신 구조의 구리금속배선(30)을 형성한다. Referring to FIG. 1, a barrier layer 14 is formed on the semiconductor substrate 10 on which the lower copper wiring 12 is formed to prevent diffusion of the lower copper wiring 12. The first low dielectric constant insulating film 16, the trench etch stop film 18, and the second low dielectric constant insulating film 20 are formed. Through the patterning process, via holes (not shown) are formed by etching the second low dielectric constant insulating film 20, the etch stop layer 18, and the first low dielectric constant insulating film 16 on the lower copper wiring. A trench (not shown) is formed by etching the second low dielectric constant insulating film 20 over the via hole through a patterning process. The diffusion barrier 22 and the seed film (not shown) are deposited along the level difference of the entire structure, and then a copper film is formed on the entire structure by using metal plating. The copper film on the second low dielectric constant insulating film 20 is removed through the planarization process to form the copper metal wiring 30 having the dual damascene structure.
이러한 공정에 있어서, 수십 나노 두께의 높은 유전 상수(K= 4~5)를 갖는 식각정지막에 의해 소자 전체의 유효 유전상수 값이 증가하게 되는 문제점이 발생하게 된다. 또한, 식각정지막이 제 2 저유전율 절연막(20)에 대한 식각율차이에 의해 트렌치 측벽에 요철일 발생하게 되고(도 1의 A영역 참조), 이로인한 구리 확산 방지를 위한 확산방지막(22)의 불연속 증착 및 열팽창 계수 차이에 따라 상술한 BM 및 BTS 등의 신뢰성 불량이 발생하게 된다. In this process, a problem arises in that the effective dielectric constant value of the entire device is increased by the etch stop film having a high dielectric constant (K = 4 to 5) of several tens of nanometers in thickness. In addition, the etch stop film causes irregularities on the sidewalls of the trench due to the difference in the etch rate with respect to the second low dielectric constant insulating film 20 (see region A of FIG. 1), thereby preventing the diffusion of the diffusion film 22 to prevent copper diffusion. According to the discontinuous deposition and the difference in thermal expansion coefficient, the reliability failures such as the above-described BM and BTS are generated.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 플라즈마나 가스 클러스터 이온빔 등의 표면 처리 방법을 이용하여 트렌치 식각정지 특성을 가지며 저유전율막 매트릭스와 유사한 구조의 얇은 계면층을 형성함으로써 신뢰성이 향상된 저유전율막을 사용한 듀얼 다마신 구조의 금속배선을 형성할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공한다. Accordingly, in order to solve the above problems, the present invention has a trench etch stop characteristic using a surface treatment method such as plasma or gas cluster ion beam, and has a low dielectric constant with improved reliability by forming a thin interface layer having a structure similar to that of a low dielectric constant film matrix. Provided is a method of forming a metal wiring of a semiconductor device capable of forming a metal wiring having a dual damascene structure using a film.
본 발명에 따른 하부 금속배선이 형성된 반도체 기판이 제공되는 단계와, 상기 반도체 기판상에 배리어막 및 제 1 저유전율 절연막을 형성하는 단계와, 표면처리를 실시하여 상기 제 1 저유전율 절연막 표면을 경화 시키고, 상기 제 1 저유전율 절연막과 유사한 구조를 갖고, 상이한 식각특성을 갖는 계면층을 형성하는 단계와, 상기 계면층 상에 제 2 저유전율 절연막을 형성하는 단계와, 상기 제 2 저유전율 절연막, 상기 계면층, 상기 제 1 저유전율 절연막 및 상기 배리어막을 패터닝하여 비아홀을 형성하고, 상기 제 2 저유전율 절연막 및 상기 계면층을 패터닝 하여 상기 비아홀 상부에 상기 비아홀보다 개구부가 넓은 트렌치를 형성하는 단계 및 상기 비아홀 및 상기 트렌치를 구리막으로 매립한 다음, 상기 제 2 저유전율 절연막을 정지막으로 하는 평탄화 공정을 통해 다마신 구조의 상부 금속배선을 형성하는 단계를 포함하는 반도체 소자의 금속배선 형성 방법을 제공한다. Providing a semiconductor substrate having a lower metal wiring according to the present invention, forming a barrier film and a first low dielectric constant insulating film on the semiconductor substrate, and performing a surface treatment to cure the surface of the first low dielectric constant insulating film And forming an interface layer having a structure similar to that of the first low dielectric constant insulating film and having different etching characteristics, forming a second low dielectric constant insulating film on the interface layer, the second low dielectric constant insulating film, Patterning the interfacial layer, the first low dielectric constant insulating film, and the barrier film to form a via hole, and patterning the second low dielectric constant insulating film and the interface layer to form a trench having an opening wider than the via hole on the via hole; Filling the via hole and the trench with a copper film, and then using the second low dielectric constant insulating film as a stop film. Forming a top metal wiring of damascene structure by the process provides a metal line forming a semiconductor device.
또한, 상기 계면층을 형성하는 단계 후, 제 2 저유전율 절연막을 형성하는 단계 전에, 상기 표면처리중에 형성된 수분을 제거하고 상기 계면층을 안정화 하기 위해 불활성 가스 분위기하에서 100 내지 500℃ 온도로 약 1 내지 60분간 열처리 공정을 실시하는 단계를 더 포함한다. Further, after the forming of the interfacial layer, and before forming the second low dielectric constant insulating film, at a temperature of about 1 to about 500 ° C. under an inert gas atmosphere to remove moisture formed during the surface treatment and to stabilize the interfacial layer. It further comprises the step of performing a heat treatment process for 60 minutes.
바람직하게, 상기 표면처리는 플라즈마 처리 또는 가스 클러스터 이온빔처리를 이용하여 실시하되, 상기 계면층의 산소 농도가 60%를 넘지 않도록 한다. Preferably, the surface treatment is performed using a plasma treatment or a gas cluster ion beam treatment, so that the oxygen concentration of the interfacial layer does not exceed 60%.
바람직하게, 상기 플라즈마 처리는 100 내지 400℃ 온도와 약 10mtorr 내지 10torr의 압력하에서 Ar, O2, CO2 및 He 중 적어도 어느 하나의 가스를 이용하여 실시한다.Preferably, the plasma treatment is performed using at least one of Ar, O 2 , CO 2 and He at a temperature of 100 to 400 ° C. and a pressure of about 10 mtorr to 10 torr.
바람직하게, 상기 가스 클러스터 이온빔 처리는 Ar, O2 CO2 및 He 중 적어도 어느 하나의 가스를 이용한 100 내지 9000 마이크론 크기의 가스 클러스터 이온빔을 사용한다.Preferably, the gas cluster ion beam treatment uses a gas cluster ion beam having a size of 100 to 9000 microns using at least one of Ar, O 2 CO 2 and He.
바람직하게, 상기 계면층은 상기 제 1 및 제 2 저유전율 절연막 매트릭스와 유사한 구조를 갖고, 상기 제 1 및 제 2 저유전율 절연막과는 상이한 식각특성을 갖는 막으로 약 10 내지 500Å 두께로 형성한다. Preferably, the interfacial layer has a structure similar to that of the first and second low dielectric constant insulating films, and has a thickness different from that of the first and second low dielectric constant insulating films, and is formed to a thickness of about 10 to 500 kPa.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다. 그러나 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 도면상에서 동일 부호는 동일한 요소를 지칭한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.
도 2a 내지 도 2d는 본 발명에 다른 금속 배선 형성 방법을 설명하기 위한 단면도들이다. 2A to 2D are cross-sectional views illustrating another method for forming metal wirings according to the present invention.
도 2a를 참조하면, 트랜지스터나 커패시터와 같은 반도체 소자(미도시)를 포함하는 여러 요소(접합부)가 형성된 반도체 기판(110) 상에 절연막(112)을 형성한 다음 절연막(112)을 패터닝 하여 하부 금속용 트렌치를 형성한다. 상기 트렌치를 구리를 이용하여 매립 평탄화 하여 하부 금속배선(114)을 형성한다. Referring to FIG. 2A, an insulating film 112 is formed on a semiconductor substrate 110 on which various elements (junctions) including a semiconductor device (not shown), such as a transistor or a capacitor, are formed, and then the insulating film 112 is patterned to form a lower portion. Form a trench for metal. The trench is buried and planarized using copper to form the lower metal wiring 114.
하부 금속배선(114)이 형성된 반도체 구조물 상에 배리어막(116)과 제 1 저유전율 절연막(118)을 순차적으로 형성한다. 배리어막(116)은 반도체 기판(110)상에 형성된 여러 요소를 보호하고, 구리의 확산을 방지하기 위해 질화막 계열의 물질막 또는 SiC 계열의 물질막을 사용하여 형성하는 것이 바람직하다. 제 1 저유전율 절연막(118)은 듀얼 다마신 패턴중 하부 금속배선(114)과 전기적으로 연결될 비아홀이 형성될 물질막으로 낮은 유전 상수(K < 3.8)를 갖는 물질막을 지칭한다. 제 1 저유전율 절연막(118)은 유기 또는 무기 계열의 물질막을 스핀온(Spin on)방식으로 도포하거나 화학기상증착법(Chemical Vapor Deposition; CVD)을 이용하여 탄소를 함유하거나 저밀도 물질막으로 약 3000 내지 10000Å 두께로 형성하는 것이 바람직하다.The barrier layer 116 and the first low dielectric constant insulating layer 118 are sequentially formed on the semiconductor structure on which the lower metal wiring 114 is formed. The barrier film 116 is preferably formed using a nitride film-based material film or a SiC-based material film to protect various elements formed on the semiconductor substrate 110 and to prevent diffusion of copper. The first low dielectric constant insulating layer 118 refers to a material layer having a low dielectric constant (K <3.8) as a material layer in which a via hole to be electrically connected to the lower metal wiring 114 is formed among the dual damascene patterns. The first low dielectric constant insulating layer 118 may be formed by applying a spin film on an organic or inorganic material layer or by using chemical vapor deposition (CVD) to contain carbon or a low density material layer of about 3000 to about 3000 to It is preferable to form in thickness of 10000 kPa.
도 2b를 참조하면, 표면처리를 실시하여 제 1 저유전율 절연막(118) 표면을 경화 시키고, 제 1 저유전율 절연막(118)과 유사한 구조를 갖고 상이한 식각특성을 갖는 계면층(120)을 형성한다. Referring to FIG. 2B, the surface treatment is performed to harden the surface of the first low dielectric constant insulating film 118, thereby forming an interface layer 120 having a structure similar to that of the first low dielectric constant insulating film 118 and having different etching characteristics. .
계면층(120)은 제 1 저유전율 절연막(118) 표면에 10 내지 500Å 두께로 형성하되, 제 1 저유전율 절연막(118) 매트릭스와 유사한 구조를 갖고 제 1 유전율 절연막(118)과는 상이한 식각특성으로 인해 후속 트렌치 형성을 위한 식각공정시 식각정지막 역할을 할 수 있는 물질막을 지칭한다. The interfacial layer 120 is formed on the surface of the first low dielectric constant insulating film 118 to have a thickness of 10 to 500 Å, and has a similar structure to the matrix of the first low dielectric constant insulating film 118 and has different etching characteristics from the first dielectric constant insulating film 118. This refers to a material film that can serve as an etch stop layer during the etching process for subsequent trench formation.
표면 처리는 플라즈마 처리 및/또는 가스 클러스터 이온빔 처리를 실시하는 것이 바람직하다. 플라즈마 표면 처리는 100 내지 400℃ 온도와 약 10mtorr 내지 10torr의 압력하에서 Ar, O2, CO2 및 He 중 적어도 어느 하나의 가스를 이용하여 실시하는 것이 효과적이다. 가스 클러스터 이온빔 처리는 Ar, O2, CO2 및 He 중 적어도 어느 하나의 가스를 이용한 100 내지 9000 마이크론 크기의 가스 클러스터 이온빔을 사용하는 것이 바람직하다. 가스 클러스터 이온은 Ar, N2, O2, CO2, SF6 등의 가스 이온들이 각각의 이온빔과는 달리 낮은 에너지 상태의 이온들이 뭉쳐져, 큰 질량을 형성하고 이들이 표면에 충돌함으로써, 원하는 계면의 표면층에만 한정적으로 영향을 미치고 표면 손상을 최소화하는 표면 처리시 사용하는 이온을 지칭한다. 플라즈마 표면 처리 및 가스 클러스트 이온빔 처리를 통해 형성된 계면층(120)의 산소 농도가 60%를 넘지 않도록 하는 것이 바람직하다.Surface treatment is preferably performed by plasma treatment and / or gas cluster ion beam treatment. Plasma surface treatment is effective using at least one of Ar, O 2 , CO 2 and He at a temperature of 100 to 400 ° C. and a pressure of about 10 mtorr to 10 torr. The gas cluster ion beam treatment preferably uses a gas cluster ion beam having a size of 100 to 9000 microns using at least one of Ar, O 2 , CO 2 and He. The gas cluster ions, unlike Ar, N 2 , O 2 , CO 2 and SF 6 , are different from each other in the ion beam, the ions in the low energy state aggregate to form a large mass and impinge on the surface. It refers to the ions used in the surface treatment that affects only the surface layer only and minimizes surface damage. It is preferable that the oxygen concentration of the interfacial layer 120 formed through the plasma surface treatment and the gas cluster ion beam treatment not exceed 60%.
계면층(120) 형성후, 표면 처리중에 형성된 수분을 제거하고 계면층(120)을 안정화하기 위한 열처리 공정을 실시한다. 열처리 공정은 불활성 가스 분위기하에서 100 내지 500℃ 온도로 약 1 내지 60분간 실시하는 것이 바람직하다. After the formation of the interfacial layer 120, a heat treatment process is performed to remove moisture formed during the surface treatment and to stabilize the interfacial layer 120. The heat treatment step is preferably performed at an inert gas atmosphere at a temperature of 100 to 500 ° C. for about 1 to 60 minutes.
상술한 바와 같이 비아용 제 1 저유전율 절연막(118)의 표면처리에 의해 형성된 얇고 치밀화된 계면층(120)은 플라즈마 이온충돌이나 가스 클러스터 이온 충돌에 의해 제 1 저유전율 절연막(118) 표면을 경화 시킨다. 기존의 저유전율막 매트릭스로부터 형성된 저농도 산소 함유 산화층의 얇은 계면 형성으로 k값 증가나 저유전율층과 전혀 다른 물질을 사용하는 것에 기인한 식각율 차이 또는 열팽창계수 차이등의 문제 없이 안정한 듀얼 다마신 패턴의 금속배선을 형성할 수 있다. 또한, 우수한 스트레스 마이크레이션 및 BTS 저항성을 갖는 신뢰성 있는 저유전율막 다층 구리 배선을 형성할 수 있다. As described above, the thin and dense interfacial layer 120 formed by the surface treatment of the first low dielectric constant insulating film 118 for vias hardens the surface of the first low dielectric constant insulating film 118 by plasma ion collision or gas cluster ion collision. Let's do it. Stable dual damascene pattern without problems such as difference in etch rate or thermal expansion coefficient due to the increase of k value or the use of a material very different from that of the low dielectric constant layer by forming a thin interface of a low concentration oxygen-containing oxide layer formed from the existing low dielectric constant film matrix Can form a metal wiring. In addition, it is possible to form a reliable low dielectric constant film multilayer copper interconnection having excellent stress micronization and BTS resistance.
도 2c를 참조하면, 계면층(120) 상에 제 2 저유전율 절연막(122)을 형성한다. 제 2 저유전율 절연막(122), 계면층(120), 제 1 저유전율 절연막(118) 및 배리어막(116)을 패터닝하여 비아홀(124)을 형성하고, 제 2 저유전율 절연막(122) 및 계면층(120)을 패터닝 하여 비아홀(124) 상부에 비아홀(124)보다 개구부가 넓은 트렌치(126)를 형성한다. Referring to FIG. 2C, a second low dielectric constant insulating film 122 is formed on the interface layer 120. The second low dielectric constant insulating film 122, the interface layer 120, the first low dielectric constant insulating film 118, and the barrier film 116 are patterned to form a via hole 124, and the second low dielectric constant insulating film 122 and the interface are formed. The layer 120 is patterned to form a trench 126 having an opening wider than the via hole 124 on the via hole 124.
제 2 저유전율 절연막(122)상에 저유전율 절연막을 보호하기 위한 하드마스크막(미도시)을 더 형성할 수도 있다. 이는 저유전율 절연막은 물에 약한 특성이 있기 때문이다. 제 2 저유전율 절연막(122)은 제 1 저유전율 절연막(118)과 동일한 물질막을 사용하는 것이 바람직하다. A hard mask film (not shown) may be further formed on the second low dielectric constant insulating film 122 to protect the low dielectric constant insulating film. This is because the low dielectric constant insulating film is weak in water. For the second low dielectric constant insulating film 122, it is preferable to use the same material film as the first low dielectric constant insulating film 118.
상기에서, 제 2 저유전율 절연막(122) 형성 후, 전체구조상에 감광막을 도포한 다음 비아홀 마스크를 이용한 사진 식각 공정을 실시하여 하부 금속배선 상부의 소정영역을 개방하는 제 1 감광막 패턴(미도시)을 형성한다. 상기 제 1 감광막 패턴을 식각 마스크로 하는 식각공정을 실시하여 제 2 저유전율 절연막(122), 계면층(120), 제 1 유전율 절연막(118) 및 배리어막(116)을 순차적으로 제거하여 비아홀(124)을 형성한다. 상기 제 1 감광막 패턴을 제거한 다음 전체 구조 상부에 감광막을 도포한다. 트렌치 마스크를 이용한 사진 식각 공정을 실시하여 비아홀(124) 상부에 비아홀(124) 보다 개구부가 넓은 제 2 감광막 패턴(미도시)을 형성한다. 상기 제 2 감광막 패턴을 식각 마스크로 하는 식각공정을 실시하여 제 2 저유전율 절연막(122) 및 계면층(120)을 제거하여 비아홀(124) 상부에 상부 금속배선용 트렌치(126)를 형성하고, 상기 제 2 감광막 패턴을 제거한다. 트렌치 형성을 위한 식각공정시 계면층(120)과 제 2 저유전율 절연막(122)간의 식각 선택비를 높게하여 제 2 저유전율 절연막(122) 만이 식각되도록 하여 하부에 형성된 구조물(제 1 저유전율 절연막; 120)이 식각되는 것을 방지하는 것이 바람직하다. 이를 통해 상부 금속배선용 트렌치(126)의 깊이를 조절할 수 있다. After the formation of the second low dielectric constant insulating film 122, the first photoresist pattern (not shown) is applied to the entire structure and then subjected to a photolithography process using a via hole mask to open a predetermined region above the lower metal wiring. To form. An etching process using the first photoresist pattern as an etch mask is performed to sequentially remove the second low dielectric constant insulating film 122, the interfacial layer 120, the first dielectric constant insulating film 118, and the barrier film 116. 124). After removing the first photoresist pattern, a photoresist is applied over the entire structure. A photolithography process using a trench mask is performed to form a second photoresist pattern (not shown) having an opening larger than the via hole 124 on the via hole 124. An etching process using the second photoresist layer pattern as an etch mask is performed to remove the second low dielectric constant insulating layer 122 and the interfacial layer 120 to form an upper metal wiring trench 126 on the via hole 124. The second photosensitive film pattern is removed. In the etching process for forming the trench, an etching selectivity between the interfacial layer 120 and the second low dielectric constant insulating layer 122 is increased so that only the second low dielectric constant insulating layer 122 is etched, thereby forming a lower structure (first low dielectric constant insulating layer). 120) is preferably prevented from etching. Through this, the depth of the upper metal wiring trench 126 may be adjusted.
도 2d를 참조하면, 전체 구조상에 구리의 확산을 방지하는 확산 방지막(128)과, 씨드층(미도시)을 그 단차를 따라 형성한다. 확산 방지막(128)은 Ta막, TaN막, TiN막, WN막, W-Si-N막 및 Ti-Si-N막 중 적어도 어느 하나의 막으로 형성하는 것이 바람직하다. Referring to FIG. 2D, a diffusion barrier film 128 for preventing the diffusion of copper and a seed layer (not shown) are formed along the steps on the entire structure. The diffusion barrier 128 is preferably formed of at least one of a Ta film, a TaN film, a TiN film, a WN film, a W-Si-N film, and a Ti-Si-N film.
금속 도금 방법을 이용하여 구리 도금층을 형성한다. 금속 도금 방법으로는 전해 도금법 및 무전해 도금법을 이용하여 상기 씨드층 상에 구리막을 형성하는 것이 바람직하다. 구리 도금층을 치밀화 하기 위한어닐 공정을 실시한 다음 CMP를 이용한 평탄화 공정을 실시하여 제 2 저유전율 절연막(122) 상에 형성된 구리 도금층을 제거하여 듀얼 다마신 패턴의 상부 금속 배선(130)을 형성한다. A copper plating layer is formed using a metal plating method. As a metal plating method, it is preferable to form a copper film on the said seed layer using an electrolytic plating method and an electroless plating method. After performing an annealing process to densify the copper plating layer and then performing a planarization process using CMP, the copper plating layer formed on the second low dielectric constant insulating film 122 is removed to form the upper metal wiring 130 of the dual damascene pattern.
본 발명은 상술한 비아 퍼스트 스킴 뿐만 아니라 트렌치 퍼스트 스킴에서도 적용될 수 있다. The present invention can be applied not only to the above-described via first scheme but also to the trench first scheme.
즉, 하부 금속배선이 형성된 전체 구조상에 배리어막 및 제 1 저유전율 절연막을 순차적으로 형성한 다음 표면처리를 실시하여 제 1 저유전율 절연막 상에 계면층을 형성한다. 계면층 상에 제 2 저유전율 절연막을 형성한다. 패터닝 공정을 통해 하부 금속 배선 상부의 제 2 저유전율 절연막 및 계면층의 일부를 제거하여 트렌치를 형성한다. 다시한번 패터닝 공정을 실시하여 트렌치 하부의 제 1 저유전율 절연막 및 배리어막의 일부를 식각하여 하부 금속배선의 일부를 노출시키는 비아홀을 형성한다. 확산방지막 및 시드층을 전체 구조의 단차를 따라 형성한 다음, 금속도금법을 이용하여 구리 도금막을 형성하여 비아홀과 트렌치를 매립한다. 평탄화 공정을 실시하여 듀얼 다마신 구조의 상부 금속 배선을 형성한다. That is, the barrier film and the first low dielectric constant insulating film are sequentially formed on the entire structure where the lower metal wiring is formed, and then surface treatment is performed to form the interface layer on the first low dielectric constant insulating film. A second low dielectric constant insulating film is formed on the interface layer. The trench is formed by removing a portion of the second low dielectric constant insulating film and the interfacial layer on the lower metal wiring through the patterning process. The patterning process is performed once again to form a via hole exposing a portion of the lower metal wiring by etching a portion of the first low dielectric constant insulating film and the barrier film under the trench. The diffusion barrier layer and the seed layer are formed along the level of the entire structure, and then a copper plating layer is formed using a metal plating method to fill the via holes and trenches. The planarization process is performed to form the upper metal wiring of the dual damascene structure.
상술한 바와 같이, 본 발명은 식각정지층을 갖는 다층의 금속배선 형성에 있어서, 상부의 저 유전율 절연막 형성전에 하부의 저 유전율 절연막을 플라즈마 이온 또는 가스 클러스터 이온을 이용한 표면처리를 통해 하부의 저 유전율 절연막 상에 계면층을 형성함으로써 저 유전율 절연막과 유사한 유전상수를 갖는 식각정지막을 형성할 수 있다. As described above, in the present invention, in forming a multi-layered metal wiring having an etch stop layer, the lower dielectric constant of the lower layer is subjected to surface treatment using plasma ions or gas cluster ions with the lower dielectric constant insulating layer before forming the upper dielectric constant insulating layer. By forming the interfacial layer on the insulating film, an etch stop film having a dielectric constant similar to that of the low dielectric constant insulating film can be formed.
또한, 저 유전율 절연막 매트릭스와 유사한 구조의 계면층을 형성하여 서로 다른 물질을 사용하는 것에 기인한 식각율차 또는 열팽창계수 차이의 문제없이 안정한 트렌치와 비아홀을 형성할 수 있다. In addition, by forming an interfacial layer having a structure similar to that of the low dielectric constant insulating matrix, it is possible to form stable trenches and via holes without problems of etching rate differences or thermal expansion coefficient differences caused by using different materials.
또한, 금속배선의 BM 및 BTS 저항성을 갖는 신뢰성 있는 저유전율막 다층 구리 배선을 형성할 수 있다. In addition, it is possible to form a reliable low dielectric constant film multilayer copper wiring having the BM and BTS resistance of the metal wiring.
도 1은 종래 공정에 따라 형성된 금속배선의 단면도 이다. 1 is a cross-sectional view of a metal wiring formed according to a conventional process.
도 2a 내지 도 2d는 본 발명에 다른 금속 배선 형성 방법을 설명하기 위한 단면도들이다. 2A to 2D are cross-sectional views illustrating another method for forming metal wirings according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10, 110 : 반도체 기판 12, 30, 114, 130 : 금속배선10, 110: semiconductor substrate 12, 30, 114, 130: metal wiring
14, 116 : 배리어막 16, 20, 118, 122 : 저유전율 절연막14, 116: barrier film 16, 20, 118, 122: low dielectric constant insulating film
18 : 식각정지막 22, 128 : 확산 방지막18: etch stop film 22, 128: diffusion barrier film
112 : 절연막 120 : 계면층112: insulating film 120: interface layer
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