JP2007157959A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device excellent in processing controllability of a wiring trench and reduced in interwiring capacitance, and to provide the semiconductor device. <P>SOLUTION: An interwiring insulating film 2 is obtained by stacking sequentially on a base substrate 1 a first low dielectric material layer 2a consisting of an organic low dielectric material or amorphous carbon, and a second low dielectric material layer 2b consisted of an inorganic low dielectric material. A first wiring trench 3 to the base substrate 1 is formed on the interwiring insulating film, and a first wiring 5 is formed by embedding a conductive film in the first wiring trench 3. Then, an interwiring layer insulating film 8 is formed on the first wiring 5 and on the second low dielectric material layer 2b, and thereafter a connection hole 9 to the first wiring 5 is formed in the interwiring layer insulating film 8. A conductive film is embedded in the connection hole 9 to form a via 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a single-damascene multilayer wiring structure having a good shape on an interlayer insulating film having a low dielectric constant. About.

  With the miniaturization and high integration of semiconductor devices, the delay of electrical signals due to the wiring time constant has become a serious problem. Therefore, low electrical resistance copper (Cu) wiring is introduced into the conductive layer used in the multilayer wiring structure instead of aluminum (Al) alloy wiring.

  Unlike metal materials such as Al used in conventional multilayer wiring structures, Cu is difficult to pattern by dry etching. Therefore, wiring grooves are formed in the insulating film and Cu films are embedded in the wiring grooves. In general, the damascene method for forming a wiring pattern is applied to a Cu multilayer wiring structure. In the damascene method, a dual damascene method in which a Cu film is embedded in the wiring groove provided in the interlayer insulating film and a connection hole communicating with the bottom thereof in the same process, and a Cu film is embedded in the wiring groove and the connection hole in a separate process. There is a single damascene method.

Further, in a highly integrated semiconductor device, an increase in inter-wiring capacitance leads to a decrease in the operation speed of the semiconductor device. Therefore, the dielectric constant is lower than that of silicon oxide (SiO ₂ ) conventionally used as an interlayer insulating film. A fine multilayer wiring structure in which a dielectric material is used for an interlayer insulating film and an increase in capacitance between wirings is suppressed is indispensable. Low dielectric materials include fluorine-containing silicon oxide (FSG) with a relative dielectric constant of about 3.5 that has been used for a long time, organic polymers such as polyaryl ether (PAE), and hydrogen. Examples thereof include low dielectric materials having a relative dielectric constant of about 2.7, such as inorganic materials typified by silsesquioxane (HSQ) and methylsilsesquioxane (MSQ). Furthermore, in recent years, attempts have been made to apply low dielectric materials having a relative dielectric constant of around 2.2 by making them porous.

By the way, when the dual damascene method is applied to an interlayer insulating film having a low dielectric material layer, the first mask made of a silicon oxide (SiO ₂ ) layer, the _second mask made of a silicon nitride (SiN) layer, and the SiO ₂ layer. There has been reported an example in which a wiring mask and a connection hole are formed in an interlayer insulating film by applying a triple mask in which third masks are sequentially stacked (see, for example, Patent Document 1).

  Such a dual damascene method has an advantage that the number of processes is reduced because the wiring groove and the connection hole are simultaneously filled with the Cu film. However, as the miniaturization progresses, the aspect ratio of the recess formed by the wiring groove and the connection hole communicating with the bottom thereof becomes higher, and not only is the Cu film not easily embedded, but the inner wall of the recess is covered. Also, the coverage of the barrier film formed by is deteriorated. Further, in the heat treatment step after filling the wiring trench and the connection hole with the Cu film, Cu “sucking” is likely to occur, and voids are likely to be formed in the via. Furthermore, in the above-described method for manufacturing a semiconductor device by the dual damascene method, since the alignment of both the upper layer wiring and the via is performed with respect to the lower layer wiring, misalignment is likely to occur, and the dimensions of the wiring groove and the connection hole are reduced. Since it is necessary to control simultaneously, dimensional control is also difficult.

  On the other hand, in the single damascene method, since the wiring trench and the connection hole are separately embedded with the Cu film, the Cu burying property and the barrier film coverage are improved, and Cu “sucking” is suppressed. In addition, alignment of vias is performed with respect to lower layer wiring, and upper layer wirings are aligned with respect to vias, so there is little misalignment and wiring and via dimensions can be controlled independently, resulting in excellent dimensional controllability. There is an advantage that.

  Here, when the single damascene method is applied to an interlayer insulating film having a low dielectric material layer, an example of performing the following steps has been reported (for example, see Patent Document 2).

First, as shown in FIG. 8A, after a carbon-containing silicon (SiC (SiCH)) etching stopper film 102 is formed on the base substrate 101, an SiOC film as an inter-wiring insulating film 103 is formed on the etching stopper film 102. The (SiOCH) layer 103a and the SiO ₂ layer 103b are sequentially stacked. Next, a first wiring groove 104 reaching the etching stopper film 102 is formed in the inter-wiring insulating film 103, and the etching stopper film 102 at the bottom of the first wiring groove 104 is removed to expose the base substrate 101. Next, a barrier film 105 is formed on the SiO ₂ layer 103 b so as to cover the inner wall of the first wiring groove 104. Subsequently, a Cu film is formed on the barrier film 105 in a state in which the first wiring groove 104 is embedded, and then an unnecessary Cu film and barrier film are formed as a wiring pattern by a chemical mechanical polishing (CMP) method. 105 is removed and a first wiring 106 is formed. Subsequently, an etching stopper film (barrier insulating film) 107 is formed on the first wiring 106 and the SiO ₂ layer 103b.

Next, as shown in FIG. 8B, a SiOC (SiOCH) layer 108 a and a SiO ₂ layer 108 b are sequentially stacked on the etching stopper film 107 as a wiring interlayer insulating film 108. Next, a connection hole 109 reaching the etching stopper film 107 is formed in the wiring interlayer insulating film 108, and the etching stopper film 107 at the bottom of the connection hole 109 is removed to expose the surface of the first wiring 106. Next, vias (conductor plugs) 111 made of Cu are formed in the connection holes 109 through the barrier film 110 in the same manner as the first wiring 106. Subsequently, an etching stopper film 112 is formed on the via 111 and the SiO ₂ layer 108b.

Next, as shown in FIG. 8C, a SiOC (SiOCH) layer 113 a and a SiO ₂ layer 113 b are sequentially stacked on the etching stopper film 112 as the inter-wiring insulating film 113. Next, a second wiring groove 114 reaching the etching stopper film 112 is formed in the inter-wiring insulating film 113, and the etching stopper film 112 at the bottom of the second wiring groove 114 is removed to expose the surface of the via 111. . Next, a second wiring 116 made of Cu is formed in the second wiring groove 114 through the barrier film 115 by the same method as the first wiring 106.

  As described above, a multilayer wiring structure of Cu by a single damascene method is formed.

JP 2004-63859 A JP 2004-221275 A

However, as shown in FIG. 9A, in the method of manufacturing a semiconductor device as described above, in the step described with reference to FIG. 8C, the SiO ₂ layer 108b constituting the upper layer of the wiring interlayer insulating film 108. And the etching stopper film 112 made of SiC formed thereon are small in etching selectivity. Therefore, after the second wiring grooves 114A and 114B having different opening widths are formed in a state of reaching the etching stopper film 112, the second wiring When the etching stopper film 112 at the bottom of the grooves 114A and 114B is removed, the depth of the second wiring groove 114 varies depending on the opening width of the second wiring groove 114. The variation in the depth of the second wiring groove 114 also occurs depending on the position of the second wiring groove 114 in the wafer surface.

  Therefore, as shown in FIG. 9B, in the semiconductor device having a single damascene structure in which the second wiring 116 is formed in the second wiring trenches 114A and 114B via the barrier film 115, the wiring resistance and the capacitance between the wirings are high. Device performance deteriorates due to variations.

Further, the upper side of the inter-wiring insulating films 103 and 113 and the wiring interlayer insulating film 108 is not only formed by the SiO ₂ layers 103b, 108b and 113b having a relative dielectric constant of about 4.2, but also the etching stopper films 102, 107 and 112. 117 is formed of a SiC film having a relative dielectric constant of about 3.5 to 5, the effective relative dielectric constant between wirings and between wiring layers is difficult to decrease.

  In view of the above, an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device that are excellent in process controllability of wiring grooves and have a reduced inter-wiring capacitance.

  In order to achieve the above object, a manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device provided with an inter-wiring insulating film and an inter-wiring insulating film made of a low dielectric material, on a base substrate. An inter-wiring insulating film formed by sequentially laminating a first low dielectric material layer composed of an organic low dielectric material or amorphous carbon and a second low dielectric material layer composed of an inorganic low dielectric material After forming a wiring groove, a wiring groove reaching the base substrate is formed in the inter-wiring insulating film, and a conductive film is buried in the wiring groove to form a wiring, and an inorganic low dielectric constant is formed on the base substrate. Forming a wiring interlayer insulating film made of a material, forming a connection hole reaching the base substrate in the wiring interlayer insulating film, and filling the conductive film into the connection hole to form a via; Yes. And it is characterized in that either the first step or the second step is performed first.

  According to such a method of manufacturing a semiconductor device, since the inter-wiring insulating film and the wiring interlayer insulating film are made of a low dielectric material, the effective relative dielectric constant between the wirings and the wiring layers is reduced. In addition, by performing the first step continuously after the second step, the first low step made of an organic low dielectric material or amorphous carbon is formed on the wiring interlayer insulating film made of an inorganic low dielectric material. Since the dielectric material layer is formed, the etching selectivity of the first low dielectric material layer with respect to the wiring interlayer insulating film increases when the wiring groove is formed. This prevents the wiring groove from being dug to different depths depending on the opening width of the wiring groove or the position of the wiring groove in the wafer surface, and it is possible to form a wiring groove having a uniform depth with good process controllability. It becomes possible.

  The semiconductor device of the present invention is a semiconductor device including an inter-wiring insulating film and a wiring interlayer insulating film made of a low dielectric material, and is a first device made of an organic low dielectric material or amorphous carbon. A first layer provided with wiring in a state of penetrating an inter-wiring insulating film formed by sequentially laminating a low dielectric material layer and a second low dielectric material layer composed of an inorganic low dielectric material; And a second layer provided with vias in a state of penetrating through a wiring interlayer insulating film made of a low dielectric material. Then, the first layer and the second layer are stacked on the base substrate in a state where the wiring and the via communicate with each other.

  According to such a semiconductor device, since the inter-wiring insulating film and the wiring interlayer insulating film are made of a low dielectric material, the effective relative dielectric constant between the wirings and the wiring layer is reduced.

  As described above, according to the semiconductor device manufacturing method and the semiconductor device of the present invention, the effective relative dielectric constant between the wirings and between the wiring layers is reduced, so that the capacitance between the wirings can be reduced. Moreover, since the process controllability of the wiring groove is excellent, it is possible to suppress variations in wiring resistance and inter-wiring capacitance. Therefore, device performance can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
This embodiment is an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention, and relates to the formation of a single damascene structure. The first embodiment of the present invention will be described below with reference to the cross-sectional views of the manufacturing steps shown in FIGS.

First, as shown in FIG. 1A, a base insulating film (interlayer insulating film) made of, for example, silicon oxide (SiO ₂ ) is formed on a semiconductor substrate on which element regions and the like (not shown) are formed. A first low dielectric material layer 2a made of an organic low dielectric material and a second low dielectric material layer 2b made of an inorganic low dielectric material are sequentially formed on the base substrate 1 as an inter-wiring insulating film 2. Laminate. As the first low dielectric material layer 2a, for example, a PAE film having a relative dielectric constant of about 2.4 is formed with a film thickness of 60 nm. The PAE film can be formed by depositing a PAE precursor by a spin coating method and then performing a heat curing process at 350 ° C. to 450 ° C. Of course, it is also possible to prepare a porous film by adjusting the precursor of PAE. As the first low dielectric material layer 2a, an organic low dielectric material film such as a BCB (Benzocyclobutene) film or a polyimide film can be used in addition to the PAE film. An amorphous carbon film may be used as the first low dielectric material layer 2a.

Next, for example, a carbon-containing silicon oxide (SiOC) film having a relative dielectric constant of about 2.5 to 3 is formed on the first low dielectric material layer 2a as the second low dielectric material layer 2b to a thickness of 100 nm. Form. As an example, a parallel plate type plasma CVD (Chemical Vapor Deposition) apparatus is used, and methylsilane is used as a gas used as a silicon source. As film formation conditions, the substrate temperature is set to 300 ° C. to 400 ° C., the plasma power is set to 100 W to 800 W, and the pressure of the film formation atmosphere is set to about 100 Pa to 1350 Pa. Here, although the wiring interlayer insulating film 8 is formed of a SiOC film, it may be formed of HSQ. Then, on the second low dielectric material layer 2b, the first wiring trench pattern to form a resist mask R ₁ provided.

Next, as shown in FIG. 1B, a first low dielectric material layer 2a and a second low dielectric material layer 2b are sequentially stacked using a resist mask R ₁ (see FIG. 1A). The inter-wiring insulating film 2 thus formed is etched. First, when etching the second low dielectric material layer (SiOC) 2b, a general magnetron type etching apparatus is used. For example, trifluoromethane (CHF ₃ ), tetrafluoromethane (CF ₄ ), And argon (Ar), the gas flow ratio (CHF ₃ : CF ₄ : Ar) is set to 1: 3: 8, the bias power is set to 1300 W, and the substrate temperature is set to 20 ° C. Under this etching condition, the etching selectivity (SiOC / PAE) of SiOC constituting the second low dielectric material layer 2b to PAE constituting the first low dielectric material layer 2a is about 3, so that this etching The SiO ₂ film of the underlying substrate 1 is not etched through the first low dielectric material layer 2a.

Subsequently, the first low dielectric material layer 2 a is etched to form the first wiring groove 3. In this case, a general magnetron etching apparatus is used. For example, ammonia (NH ₃ ) is used as an etching gas, the gas flow rate is 100 cm ³ / min, the bias power is 400 W, and the substrate temperature is 20 ° C. Under this etching condition, a high selectivity (PAE / SiO ₂ ) of 100 or more can be obtained with respect to the SiO ₂ film of the base substrate 1, so that the SiO ₂ film is hardly etched. After the inter-wiring insulating film 2 is etched, for example, an ashing process based on NH ₃ plasma and an organic amine-based chemical process are performed to remove the residual mask generated during the resist mask R ₁ and the etching process. Remove completely.

  Thereafter, as shown in FIG. 1C, the barrier film 4 made of, for example, tantalum (Ta) is formed on the first low dielectric material layer 2b in a state of covering the inner wall of the first wiring groove 3 by, for example, sputtering. Is formed with a film thickness of about 10 nm. Subsequently, a conductive film (not shown) made of Cu, for example, is formed on the barrier film 4 in a state where the first wiring groove 3 is embedded by, for example, electrolytic plating or sputtering. Thereafter, the conductive film and the barrier film 4 which are unnecessary as a wiring pattern are removed by CMP, and the second low dielectric material layer 2b is exposed. Thus, a buried wiring (first wiring) 5 made of Cu having a single damascene structure is formed in the first wiring groove 3. At this time, the polishing time of the CMP is adjusted so that the wiring film thickness becomes 110 nm.

Subsequently, the surface of the second low dielectric material layer 2b exposed after the CMP is subjected to a modification process to form the modified layer 6 on the surface side of the second low dielectric material layer 2b. The modification treatment includes densification, nitridation, carbonization and oxidation. Examples of the densification method include surface treatment with helium (He) plasma or Ar plasma, curing treatment made of EB-Cure or UV-Cure, and nitridation methods include surface treatment with NH ₃ plasma or nitrogen (N ₂ ) plasma. There are processing. Further, as carbonization method, plasma treatment with C _x H _y based gas such as methane (CH _4), as the oxidation method, a plasma treatment, and the like due to O ₂ or dinitrogen monoxide (N ₂ O). Here, as the above-described modification treatment, the surface of the second low dielectric material layer 2b is subjected to surface treatment with He plasma, and the densified modification layer 6 is formed on the surface side of the second low dielectric material layer 2b. Form.

  By forming the modified layer 6, the etching selectivity of the wiring interlayer insulating film (SiOC) formed on the modified layer 6 in a later step with respect to the modified layer 6 becomes about 2, and the second low dielectric material layer It becomes larger than the etching selectivity with respect to (SiOC) 2b. As a result, when the connection hole is formed in the wiring interlayer insulating film, even if misalignment occurs between the connection hole and the first wiring 5, the modified layer is exposed at the bottom of the connection hole. The formation of slits is suppressed. The film thickness of the modified layer 6 is determined by the balance between the relative dielectric constant of the modified layer 6 and the etching selectivity with respect to the wiring interlayer insulating film provided on the modified layer 6, but a film thickness of about 5 nm to 15 nm. It is preferable to form by.

  Subsequently, as shown in FIG. 1D, a metal cap film 7 made of, for example, cobalt tungsten phosphorus (CoWP) is selectively formed on the first wiring 5 by, for example, an electroless plating method. This electroless plating is performed in the sequence of Cu oxide removal, catalyst treatment, film formation, and cleaning. Specifically, Cu oxide on the surface of the first wiring 5 is removed, and catalytic treatment is performed using a solution containing palladium (Pd) ions having high catalytic activity. Thereafter, a CoWP film is selectively formed on the surface of the first wiring 5 with a plating solution containing cobalt (Co) ions, tungsten (W) ions, and hypophosphite. In addition, hypophosphite in the plating solution acts as a reducing agent, and Co, W, and phosphorus (P) acquire the electrons released by the oxidation reaction of hypophosphite and eutectoidally react. As a result, a CoWP film is formed. The CoWP film thickness is about several nm to 20 nm. However, since CoWP is formed isotropically, the thicker the film thickness, the easier it is for the leak characteristics between the wirings to deteriorate, so about 5 nm is desirable. The plating solution is adjusted so that the composition ratio of Co, W, and P is about 90% / 2% / 8%.

  Here, an example in which the metal cap film 7 is formed of a CoWP film will be described. However, the film type of the metal cap film 7 is not limited to the CoWP film, and the composition of the plating solution used in the electroless plating method is changed. Thus, it is also possible to use cobalt tungsten boron (CoWB), nickel molybdenum phosphorus (NiMoP), or nickel molybdenum boron (NiMoB). Further, the metal cap film 7 made of W, for example, may be formed by selective CVD.

  Next, as shown in FIG. 2E, a wiring interlayer insulating film 8 made of, for example, SiOC is formed on the metal cap film 7 and the modified layer 6 as an inorganic low dielectric material with a film thickness of 90 nm. At this time, the film may be formed under the same conditions as those of the second low dielectric material layer (SiOC) 2b described above. However, the second low dielectric material layer (SiOC) can be made porous by using Poregen or the like. ) An SiOC layer having a relative dielectric constant of about 2 to 3 lower than that of 2b is formed. As a result, the etching selectivity of the wiring interlayer insulating film (SiOC) 8 with respect to the modified layer 6 when forming the connection hole in a later step is further increased to about 2.5 to 3.5, and the connection hole is formed. The formation of slits at the bottom of the connection hole can be further suppressed.

Next, as shown in FIG. 2F, a resist mask R ₂ having a connection hole pattern is formed on the wiring interlayer insulating film 8. Subsequently, as shown in FIG. 2G, the wiring interlayer insulating film 8 is etched by a dry etching method using the resist mask R ₂ (see FIG. 2F) as an etching mask, so that a metal cap film is formed. A connection hole 9 exposing the surface of 7 is opened. At this time, as described above, the wiring interlayer insulating film 8 is made porous, and the modified layer 6 is provided between the wiring interlayer insulating film 8 and the second low dielectric constant layer 2b. Even when misalignment occurs between the connection hole 9 and the first wiring 5, the etching selectivity of the wiring interlayer insulating film 8 is increased, and the formation of the slit at the bottom of the connection hole 9 is suppressed.

The wiring interlayer insulating film 8 is etched using, for example, CHF ₃ , O ₂ and Ar as etching gases, a gas flow ratio (CHF ₃ : O ₂ : Ar) of 5: 1: 50, a bias power of 1000 W, and a substrate temperature. Is set to 40 ° C. Thereafter, for example, an ashing process based on NH ₃ plasma and an organic amine chemical solution process are performed to completely remove the resist mask R ₂ and the residual deposits generated during the etching process.

  Next, as shown in this figure, a barrier film 10 made of, for example, Ta is formed on the wiring interlayer insulating film 8 so as to cover the inner wall of the connection hole 9 by, eg, sputtering. Subsequently, a conductive film 11 ′ made of, for example, Cu is formed on the barrier film 10 in a state where the connection hole 9 is embedded, for example, by electrolytic plating or sputtering.

  Thereafter, as shown in FIG. 2H, the conductive film 11 ′ unnecessary as a wiring pattern (see FIG. 2G) and the barrier film 10 are removed by CMP to expose the wiring interlayer insulating film 8. . As a result, vias 11 made of Cu are formed in the connection holes 9 via the barrier film 10. At this time, the polishing time of CMP is adjusted so that the height of the via 11 becomes 80 nm.

  Subsequently, a metal cap film 12 made of, for example, CoWP is selectively formed on the via 11 by, for example, an electroless plating method. Here, the metal cap film 12 is formed under the same conditions as the metal cap film 7 described above.

Since the subsequent steps are the same as those described with reference to FIGS. 1A to 2H, the film forming conditions and etching conditions of each film are omitted. That is, as shown in FIG. 3I, the first low dielectric material layer 13a made of an organic low dielectric material is formed on the metal cap film 12 and the wiring interlayer insulating film 8 as the inter-wiring insulating film 13. Then, a second low dielectric material layer 13b made of an inorganic low dielectric material is sequentially laminated. Here, as the first low dielectric material layer 13a, for example, a PAE film is formed with a film thickness of 65 nm, and as the second low dielectric material layer 13b, for example, a SiOC film is formed with a film thickness of 100 nm. Next, as shown in FIG. 3 (j), on the second low dielectric material layer 13b, the second wiring groove pattern to form a resist mask R ₃ provided.

Next, as shown in FIG. 3 (k), the first low dielectric material layer 13a and the second low dielectric material layer 13b are sequentially stacked using the resist mask R ₃ (see FIG. 3 (j)). The inter-wiring insulating film 13 thus etched is etched to form a second wiring groove 14 reaching the metal cap film 12 and the wiring interlayer insulating film 8 in the inter-wiring insulating film 13. At this time, since the etching selection ratio (PAE / SiOC) of the first low dielectric material layer 13a to the wiring interlayer insulating film 8 is a high selection ratio of 100 or more, the wiring interlayer insulating film 8 is hardly etched. No. Thus, the second wiring groove 14 having a uniform depth can be formed regardless of the opening width of the second wiring groove 14 and the position of the second wiring groove 14 in the wafer surface.

Thereafter, for example, an ashing process based on NH ₃ plasma and an organic amine chemical solution process are performed to completely remove the resist mask R ₃ and the residual deposits generated during the etching process.

  Next, as shown in FIG. 4L, a barrier film 15 made of Ta, for example, is formed on the second low dielectric material layer 13b so as to cover the inner wall of the second wiring groove 14 by, for example, sputtering. . Subsequently, a conductive film 16 ′ made of Cu, for example, is formed on the barrier film 15 in a state where the second wiring groove 14 is embedded by, for example, electrolytic plating or sputtering.

  Thereafter, as shown in FIG. 4 (m), the conductive film 16 ′ (see FIG. 4 (l)) and the barrier film 15 which are not necessary as a wiring pattern are removed by CMP to remove the second low dielectric material layer 13b. To expose. Thus, a buried wiring (second wiring) 16 made of Cu having a single damascene structure is formed in the second wiring trench 14. At this time, the polishing time of the CMP is adjusted so that the wiring film thickness becomes 115 nm. Subsequently, the surface of the second low dielectric material layer 13b exposed after CMP is subjected to a modification process to form a modified layer 17 on the surface side of the second low dielectric material layer 13b. Next, a metal cap film 18 made of COWP is selectively formed on the second wiring 16.

  According to such a semiconductor device manufacturing method and semiconductor device, since the inter-wiring insulating films 2 and 13 and the inter-wiring interlayer insulating film 8 are made of a low dielectric material, an effective ratio between the inter-wiring and inter-wiring layers is obtained. Since the dielectric constant is reduced, the capacitance between wirings can be reduced. In addition, since the first low dielectric material layer (PAE) 13a made of an organic low dielectric material is formed on the wiring interlayer insulation film (SiOC) 8 made of an inorganic low dielectric material, the wiring interlayer insulating film ( The etching selectivity of the first low dielectric material layer (PAE) 13a with respect to (SiOC) 8 is increased. Thereby, when the second wiring groove 14 is formed in the wiring interlayer insulating film 8, the second wiring groove 14 may be dug to a different depth depending on the opening width of the second wiring groove 14 or the position in the wafer surface. Thus, the second wiring groove 14 having a uniform depth can be formed with good process controllability. Therefore, variations in wiring resistance and wiring capacitance can be suppressed. From the above, device performance can be improved.

  Further, the surface of the second low dielectric material layer 2b constituting the upper layer side of the inter-wiring insulating film 2 is subjected to a modification process to form the modified layer 6, whereby the wiring formed on the modified layer 6 Since the etching selectivity with the interlayer insulating film 8 is high, even when misalignment occurs between the first wiring 5 and the connection hole 9 when the connection hole 9 is formed, a slit at the bottom of the connection hole 9 is formed. Can be suppressed. Therefore, it is possible to prevent a defective filling of the conductive film 11 ′ into the connection hole 9 due to the slit.

  Further, since the wiring interlayer insulating film 8 is formed of a porous SiOC film, the etching selectivity of the wiring interlayer insulating film 8 with respect to the modified layer 6 is further increased. Thereby, formation of the slit of the connection hole 9 bottom part can further be suppressed.

(Second Embodiment)
Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional view of FIG. In addition, the same number is attached | subjected and demonstrated to the structure similar to 1st Embodiment, and detailed description is abbreviate | omitted. In addition, until the step of forming the first wiring groove 3 in the inter-wiring insulating film 2 provided on the base substrate 1 described with reference to FIGS. 1A to 1B in the first embodiment, Suppose that it carries out similarly to 1st Embodiment.

  First, as shown in FIG. 5A, the second low-dielectric material is formed so as to cover the inner wall of the first wiring groove 3 by a physical vapor deposition (PVD) method such as a sputtering method. A seed layer 21 made of a Cu—Mn alloy containing about 2 atomic% manganese (Mn) is formed on the layer 2b.

Next, as shown in FIG. 5B, a conductive film made of, for example, Cu is formed on the seed layer 21 (see FIG. 5A) in a state where the first wiring groove 3 is embedded by, for example, electrolytic plating. 11 'is deposited to 1000 nm. Thereafter, heat treatment is performed at 300 ° C. for 30 minutes in an oxygen atmosphere to cause Mn in the seed layer 21 to react with the constituent material of the inter-wiring insulating film 2 (for example, Si, O or moisture in the film), thereby A self-forming barrier film 22 made of a Mn compound (for example, MnSi _x O _y , MnO _z ) is formed on the inner wall of the wiring trench 3 with a film thickness of about 2 nm to 3 nm. At this time, a part of excess Mn other than Mn necessary for the formation of the self-forming barrier film 22 reacts with oxygen in the atmosphere on the surface of the conductive film 11 ′ to form the MnO film 22 ′.

  Next, as shown in FIG. 5C, the CMP method is used together with the MnO film 22 ′ (see FIG. 5B) and the conductive film 11 ′ unnecessary as a wiring pattern (see FIG. 5B). Then, the self-forming barrier film 22 is removed, and the second low dielectric material layer 2b is exposed. As a result, the first wiring 5 is formed in the first wiring trench 3 through the self-forming barrier film 22. Thereafter, as in the first embodiment, the surface of the second low dielectric material layer 2b is subjected to a modification treatment to form the modified layer 6 on the surface side of the second low dielectric material layer 2b.

  Next, as shown in FIG. 5D, similarly to the first embodiment, a metal cap film 7 made of a CoWP film is selectively formed on the first wiring 5.

  Subsequent steps are performed in the same manner as in the first embodiment described with reference to FIGS. 2E to 4M to form a multilayer wiring structure as shown in FIG. However, the barrier film 10 (see FIG. 2 (g)) and the barrier film 15 (see FIG. 4 (l)) are not formed on the inner walls of the connection hole 9 and the second wiring trench 14, but the above-described self Self-formed barrier films 23 and 24 made of a Mn compound are formed by the same method as the formation barrier film 22, respectively.

  Even in such a method of manufacturing a semiconductor device and a semiconductor device, since the inter-wiring insulating films 2 and 13 and the inter-wiring interlayer insulating film 8 are made of a low dielectric material, effective between the inter-wiring and inter-wiring layers can be achieved. The relative dielectric constant is reduced. Further, since the first low dielectric material layer (PAE) 13a is formed on the wiring interlayer insulating film (SiOC) 8, the first low dielectric material layer (PAE) 13a with respect to the wiring interlayer insulating film (SiOC) 8 is formed. The etching selectivity is increased, and the second wiring groove 14 having a uniform depth can be formed with good process controllability. Further, since the modified layer 6 is formed on the surface of the second low dielectric material layer 2b and the wiring interlayer insulating film 8 is formed of a porous SiOC film, the connection hole 9 is formed when the connection hole 9 is formed. The formation of slits at the bottom of 9 is suppressed. Therefore, the same effect as that of the first embodiment can be obtained.

  In addition, as a barrier film covering the inner walls of the first wiring groove 3, the connection hole 9, and the second wiring groove 14, self-forming barrier films 22, 23, and 24 made of a Mn compound are formed, so that the first embodiment can be improved. Since the barrier film can be thinned, the wiring resistance can be reduced.

(Third embodiment)
Next, a third embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process sectional view of FIG. In addition, the same number is attached | subjected and demonstrated to the structure similar to 2nd Embodiment, and detailed description is abbreviate | omitted. Further, in the second embodiment, the first wiring groove 3 is formed in the inter-wiring insulating film 2 provided on the base substrate 1 described with reference to FIGS. The process from the formation of the first wiring 5 in the wiring groove 3 through the self-formed barrier film 22 to the step of forming the modified layer 6 on the surface side of the second low dielectric material layer 2b is the same as in the second embodiment. Suppose that

  First, as shown in FIG. 6A, a wiring interlayer insulating film (SiOC) 8 is formed on the first wiring 5 and the modified layer 6 by the CVD method. At this time, it was diffused into the first wiring 5 from the seed layer 21 (see FIG. 5A) made of a CuMn alloy provided so as to cover the inner wall of the first wiring groove 3 by heat during film formation. When Mn reacts with the constituent material of the wiring interlayer insulating film 8 (for example, Si, O or moisture in the film), a self-formed barrier film 25 made of a Mn compound is formed on the surface of the first wiring 5. Thereafter, heat treatment is performed at 300 ° C. for about 30 minutes in order to reliably form the self-forming barrier film 25. Thereby, the self-forming barrier film 25 is formed with a film thickness of 2 nm to 3 nm.

  Next, as shown in FIG. 6B, a connection hole 9 reaching the first wiring 5 is formed in the wiring interlayer insulating film 8. By this etching, the self-formed barrier film 25 is removed because it is thin.

  The subsequent steps are performed in the same manner as in the second embodiment described with reference to FIG. However, the metal cap film 12 (see FIG. 5E) is not formed on the via 11, and a self-formed barrier film (not shown) is formed on the surface of the via 11 by the same method as the self-formed barrier film 25. Form. Although illustration is omitted here, a wiring interlayer insulating film made of, for example, SiOC is formed on the second wiring 16 and the inter-wiring insulating film 13, and heat treatment is performed, so that the surface of the second wiring 16 is formed. A self-forming barrier film (not shown) is formed.

  Even in such a method of manufacturing a semiconductor device and a semiconductor device, since the inter-wiring insulating films 2 and 13 and the inter-wiring interlayer insulating film 8 are made of a low dielectric material, effective between the inter-wiring and inter-wiring layers can be achieved. The relative dielectric constant is reduced. Further, since the first low dielectric material layer (PAE) 13a is formed on the wiring interlayer insulating film (SiOC) 8, the first low dielectric material layer (PAE) 13a with respect to the wiring interlayer insulating film (SiOC) 8 is formed. The etching selectivity is increased, and the second wiring groove 14 having a uniform depth can be formed with good process controllability. Further, since the modified layer 6 is formed on the surface side of the second low dielectric material layer 2b, and the wiring interlayer insulating film 8 is formed of the porous SiOC film, the slit at the bottom of the connection hole 9 is formed. Is suppressed. In addition, by forming the self-formed barrier films 22, 23, and 24 made of the Mn compound, the barrier film can be made thinner than in the first embodiment, so that the wiring resistance can be reduced. Therefore, the same effect as in the second embodiment can be obtained.

  Furthermore, according to the semiconductor device manufacturing method and the semiconductor device of the present embodiment, the first wiring 5, the via 11, and the second wiring 16 are formed continuously without using a barrier film. Thereby, compared to the semiconductor device of the second embodiment, the wiring resistance can be reduced, and the wiring reliability such as EM resistance and SM resistance can be improved.

(Fourth embodiment)
Next, a fourth embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process sectional view of FIG. In the semiconductor device manufacturing method according to the first to third embodiments described above, the example in which the etching stopper film is not provided between the inter-wiring insulating film and the inter-wiring interlayer insulating film has been described. The present invention is applicable even if a stopper film is provided. Here, an example in which an etching stopper film is provided between the inter-wiring insulating film 2 and the inter-wiring interlayer insulating film 8 and on the inter-wiring insulating film 13 described with reference to FIG. 6B in the third embodiment will be described. .

  In addition, the same number is attached | subjected and demonstrated to the structure similar to 3rd Embodiment, and detailed description is abbreviate | omitted. In addition, the first wiring groove 3 is formed in the inter-wiring insulating film 2 provided on the base substrate 1 described with reference to FIG. 6A in the third embodiment, and the self-forming barrier is formed in the first wiring groove 3. The process up to forming the first wiring 5 via the film 22 is performed in the same manner as in the third embodiment.

  As shown in FIG. 7A, after the first wiring 5 is formed, an SiC film having a relative dielectric constant of about 3.5 to 5 is formed on the first wiring 5 and the second low dielectric constant layer 2b. The etching stopper film 26 to be formed is formed with a film thickness of 30 nm. When forming this SiC film, for example, a parallel plate type plasma CVD apparatus is used, and methylsilane is used as a gas used as a silicon source. As film formation conditions, the substrate temperature is set to 300 ° C. to 400 ° C., the plasma power is set to 150 W to 300 W, and the pressure of the film formation atmosphere is set to about 100 Pa to 1000 Pa.

  At this time, similarly to the third embodiment, Mn diffused in the first wiring 5 reacts with the constituent material of the etching stopper film 26 due to heat at the time of forming the etching stopper film 26, and the first wiring 5 A self-forming barrier film 25 made of a Mn compound is formed on the surface. Here, since the etching stopper film 26 is provided on the second low dielectric material layer 2b, the modified layer 6 (see FIG. 5C) on the surface side of the second low dielectric material layer 2b. May not be formed.

  Next, as shown in FIG. 7B, the wiring interlayer insulating film 8 is formed on the etching stopper film 26. At this time, in the first embodiment, a porous SiOC film is formed as the wiring interlayer insulating film 8, thereby selecting the etching of the wiring interlayer insulating film 8 with respect to the modified layer 6 (see FIG. 6A). In this case, since the etching stopper film 26 is provided on the second low dielectric material layer 2b, the SiOC film used for the wiring interlayer insulating film 8 need not be made porous. Good.

  Subsequently, the connection hole 9 that reaches the etching stopper film 26 is formed by etching, and the etching stopper film 26 at the bottom of the connection hole 9 is removed by etching to expose the surface of the first wiring 5. By this etching, the self-formed barrier film 25 provided on the surface of the first wiring 5 is removed. The subsequent steps are performed in the same manner as the steps described with reference to FIG. 6B in the third embodiment. However, an etching stopper film 27 made of, for example, SiC is formed with a thickness of 30 nm on the second wiring 16 and the second low dielectric material layer 13b. In this case, the modified layer 17 (see FIG. 6B) may not be formed on the surface side of the second low dielectric material layer 13b.

  According to such a method of manufacturing a semiconductor device and the semiconductor device, SiC having a relative dielectric constant of about 3.5 to 5 is formed between the inter-wiring insulating film 2 and the inter-wiring insulating film 8 and on the inter-wiring insulating film 13. Since the etching stopper films 26 and 27 are formed, the effective relative dielectric constant between the wirings and between the wiring layers is higher than that of the semiconductor device in the first to third embodiments. However, since the inter-wiring insulating films 2 and 13 and the inter-wiring insulating film 8 are made of a low dielectric material, and no etching stopper film is formed between the inter-wiring insulating film 8 and the inter-wiring insulating film 13. Compared with the conventional semiconductor device described with reference to FIG. 8 in the background art, the effective relative dielectric constant can be reduced.

  Further, since the first low dielectric material layer (PAE) 13a is formed on the wiring interlayer insulating film (SiOC) 8, the first low dielectric material layer (PAE) 13a with respect to the wiring interlayer insulating film (SiOC) 8 is formed. The etching selectivity is increased, and the second wiring groove 14 having a uniform depth can be formed with good process controllability. Furthermore, the wiring resistance can be reduced by forming the self-forming barrier films 22, 23, and 24 made of a Mn compound.

  In addition, since the first wiring 5, the via 11, and the second wiring 16 are formed continuously without using a barrier film, the wiring resistance can be reduced as compared with the semiconductor device of the second embodiment. In addition, wiring reliability such as EM resistance and SM resistance can be improved.

FIG. 6 is a manufacturing process cross-sectional view (No. 1) for describing the first embodiment of the semiconductor device manufacturing method of the present invention; FIG. 6 is a manufacturing process sectional view (No. 2) for describing the first embodiment of the manufacturing method of the semiconductor device of the invention; It is manufacturing process sectional drawing (the 3) for demonstrating 1st Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. FIG. 7 is a manufacturing process cross-sectional view (No. 4) for describing the first embodiment of the manufacturing method of the semiconductor device of the invention; It is manufacturing process sectional drawing for demonstrating 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing for demonstrating 3rd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing for demonstrating 4th Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device. It is manufacturing process sectional drawing for demonstrating the subject in the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Base substrate, 2, 13 ... Inter-wiring insulating film, 2a, 13a ... 1st low dielectric material layer, 2b, 13b ... 2nd low dielectric material layer, 3 ... 1st wiring groove, 5 ... 1st wiring 6, 17 ... modified layer, 7, 12, 18 ... metal cap film, 8 ... wiring interlayer insulating film, 9 ... connection hole, 11 ... via, 14 ... second wiring groove, 16 ... second wiring

Claims (11)

A method of manufacturing a semiconductor device comprising an inter-wiring insulating film and an inter-wiring insulating film made of a low dielectric material,
A first low dielectric material layer composed of an organic low dielectric material or amorphous carbon and a second low dielectric material layer composed of an inorganic low dielectric material are sequentially laminated on a base substrate. Forming a wiring groove reaching the base substrate in the inter-wiring insulating film after forming the inter-wiring insulating film, and embedding a conductive film in the wiring groove to form a wiring;
After forming a wiring interlayer insulating film made of an inorganic low dielectric material on the base substrate, a connection hole reaching the base substrate is formed in the wiring interlayer insulating film, and a conductive film is buried in the connection hole to form a via. A second step of forming,
Either of the first step and the second step is performed first. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
After the first step, perform the second step,
By performing a modification process on the surface of the second low dielectric material layer between the first step and the second step, a modified layer is formed on the surface side of the second low dielectric material layer. A method for manufacturing a semiconductor device, comprising performing a forming step. In the manufacturing method of the semiconductor device according to claim 1,
After the first step, perform the second step,
In the second step, the wiring interlayer insulating film is formed so that an etching selectivity of the wiring interlayer insulating film with respect to the second low dielectric material layer is increased. In the manufacturing method of the semiconductor device according to claim 1,
After the second step, the first step is continuously performed,
In the first step, the first low dielectric material layer is formed on the via and on the wiring interlayer insulating film. A method of manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the first step and the second step are alternately repeated. In the manufacturing method of the semiconductor device according to claim 1,
After the first step and after the second step,
A method of manufacturing a semiconductor device, comprising: selectively forming a metal cap film on the wiring or the via. In the manufacturing method of the semiconductor device according to claim 1,
In the first step, after forming the wiring groove, an alloy film made of a conductive material constituting the conductive film and a metal other than the conductive material is formed in a state of covering the inner wall of the wiring groove. By embedding the conductive film on the alloy film, the wiring is formed in the wiring groove via a barrier film obtained by reacting the metal and the constituent material of the inter-wiring insulating film,
In the second step, after forming the connection hole, an alloy film made of a conductive material constituting the conductive film and a metal other than the conductive material is formed in a state of covering the inner wall of the connection hole. By burying the conductive film through an alloy film, the via is formed in the connection hole through a barrier film formed by reacting the metal and the constituent material of the wiring interlayer insulating film. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 7.
After the first step, perform the second step continuously,
In the second step, the wiring interlayer insulating film is formed on the wiring and the second low dielectric material layer, and the metal in the alloy film and the wiring interlayer insulating film are formed on the surface of the wiring. A method of manufacturing a semiconductor device, comprising: forming the barrier film by reacting with a constituent material of: The method of manufacturing a semiconductor device according to claim 7.
After the second step, the first step is continuously performed,
In the first step, the first low dielectric material layer is formed on the via and on the wiring interlayer insulating film, and the metal in the alloy film and the first low dielectric material layer are formed on the surface of the via. A method of manufacturing a semiconductor device, comprising: forming the barrier film by reacting with a constituent material of a dielectric material layer. A semiconductor device comprising an inter-wiring insulating film and an inter-wiring insulating film made of a low dielectric material,
An inter-wiring insulating film formed by sequentially laminating a first low dielectric material layer composed of an organic low dielectric material or amorphous carbon and a second low dielectric material layer composed of an inorganic low dielectric material A first layer provided with wiring in a penetrating state;
A second layer provided with vias penetrating through a wiring interlayer insulating film made of an inorganic low dielectric material,
The semiconductor device, wherein the first layer and the second layer are stacked on a base substrate in a state where the wiring and the via communicate with each other. The semiconductor device according to claim 10.
The second layer is provided on the first layer;
A semiconductor device, wherein a modified layer formed by a modification process is provided on a surface side of the second low dielectric material layer constituting the first layer.

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