JP2009117673A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that while securing sufficient EM resistance for wiring, reduces inter-wiring-layer and inter-line leaks, increases a TDDB life, and secures a high selection ratio during via-hole etching to have high-reliability wiring, and to provide a manufacturing method thereof. <P>SOLUTION: The semiconductor device includes a wiring groove M1 formed on a first insulating film 1 on a silicon substrate, a tantalum-based barrier metal 2a formed on a sidewall and a bottom portion of the wiring groove M1, a Cu film 2b formed along the tantalum-based barrier metal 2a so as to bury the wiring groove M1, an alloy layer of copper and silicon or a CuSiN layer 3a of copper, silicon, and nitrogen formed on a surface of the Cu film 2b, and an SiNx film 3d formed on the CuSiN layer 3a and first insulating film 1 and having higher density than that of the first insulating film 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a wiring in a semiconductor device, and more particularly to a technique for improving reliability by forming a conductor cap film on the wiring.

  In recent years, as the integration, performance, and speed of semiconductor devices (particularly, semiconductor integrated circuit devices) have increased, copper (Cu) or copper-based wiring (hereinafter referred to as Cu wiring) is used as the internal wiring. Is often used. Even for such Cu wiring, since further cross-sectional area is reduced and current density in the wiring is increased due to further miniaturization, resistance to further electromigration (hereinafter referred to as EM) is increased. Improvement is demanded.

  As one of countermeasures, a method of forming a copper silicide (CuSix) or copper silicon nitride (CuSiN) layer on the upper surface of the Cu wiring has been proposed. In the conventional structure, the interface between the Cu wiring and the interlayer insulating film is the main Cu diffusion path. By forming a CuSix or CuSiN layer on the surface of the Cu wiring, the interface adhesion at the Cu upper interface is improved. In addition, Cu diffusion can be suppressed.

  As one method for forming the CuSiN layer, recently, gas cluster ion beam (hereinafter referred to as GCIB) irradiation has been proposed (see, for example, Patent Document 1, Non-Patent Documents 1 and 2). Has been.

A conventional method for manufacturing a semiconductor device in which a Cu wiring is formed by GCIB irradiation as described above will be described below with reference to the drawings.
FIG. 4 is a cross-sectional view showing each step in the conventional method of manufacturing a semiconductor device.

  First, a first metal wiring groove pattern is formed on a first insulating film 101 as a layer forming insulating film made of a carbon-containing silicon oxide film (SiOC) which is a low dielectric constant film on a silicon substrate (not shown) by photolithography. The first insulating film 101 is removed by etching using a dry etching method to form a wiring trench M1.

Thereafter, a tantalum-based barrier metal 102a and a seed Cu layer are formed by sputtering, and then a Cu film 102b is formed by electroplating. After annealing at 300 ° C. in an N ₂ atmosphere, chemical mechanical polishing ( First Cu wirings 102 are formed by a chemical mechanical polishing (CMP) method (FIG. 4A).

Next, the surface is irradiated with a gas cluster ion beam made of silane (SiH ₄ ), nitrogen (N ₂ ), and helium (He) by the GCIB method. At this time, the portion where the Cu surface is exposed is Cu and SiH ₄ and _{N 2} react with each CuSiN103a is formed, now the Cu surface is covered is the reaction SiH ₄ and _{N 2} in CuSiN103a, silicon Knight A ride (SiNx) film 103c is formed. On the other hand, a reaction layer 103b of SiOC, SiH ₄ and N ₂ is formed on the first insulating film 101, and then a SiNx film 103c is formed (FIG. 4B).

As described above, in the GCIB method, the CuSiN layer 103a is formed on the Cu wiring 102, and at the same time, the SiNx film 103c, which is an insulating film barrier layer, is continuously formed.
Thereafter, the second insulating film 104 as a layer forming insulating film made of SiOC for forming the upper layer wiring is formed, and the via hole H1 (FIG. 4C) and the wiring groove M2 (FIG. 4) are formed by a normal dual damascene method. 4 (d)) is formed, and the SiNx film 103c at the bottom of the via is removed by whole surface etching (FIG. 4E).

  Thereafter, the second Cu wiring 105 is formed by the same formation method as the first Cu wiring 102, and the CuSiN layer 106a, the reaction layer 106b, and the SiNx film 106c are formed again by the GCIB method (FIG. 4F). ).

A multilayer wiring can be formed by repeating the above steps.
JP-T-2006-507670 S. Kondo, et. al. "Infusion Processing for Reliable Copper Interconnects", Advanced Metallization Conference 2006 p. 75-76 R. Gras, et. al. , “Integration and Characterization of Gas Cluster Processing for Copper Interconnects Electromigration Implantation,” Materials for Advanced Metallization 2007

However, in the GCIB method used in the conventional method for manufacturing a semiconductor device as described above, the SiNx film 103c can be continuously formed on the CuSiN layer 103a as described above. However, in this GCIB method, the gas is mainly gas. Based on the collision energy of the cluster ion beam, SiH ₄ and N ₂ are reacted to form the SiNx film 103c, and since this is at room temperature only, sufficient decomposition, reaction, and bonding are not performed. As a result, the SiNx film 103c having a low density and a poor film quality in which the bonding between atoms is not sufficient is obtained.

Due to the above, various problems as shown below have occurred.
The electric barrier property of the SiNx film 103c is insufficient, and interlayer leakage between the first Cu wiring 102 and the second Cu wiring 105 and TDDB (Time Dependent Dielectric BreakDown) are deteriorated.

  Further, since the film quality of the SiNx film 103c is not good, the interface between the first insulating film 101, the reaction layer 103b, and the SiNx film 103c also has poor film quality, and the inter-wiring leakage between the Cu wirings 102 and the TDDB are also deteriorated. Furthermore, the adhesion is not so good.

  Further, it is necessary to stop the bottom of the via hole H1 with the SiNx film 103c at the time of via etching for forming the via hole H1 when forming the upper layer wiring 105 (see FIG. 4C), but the film quality is not so good. Since the etching rate is higher than that of SiN or the like and cannot be stopped, the Cu of the lower layer wiring 102 is exposed. Therefore, the Cu is scraped by subsequent ashing or cleaning, resulting in a defect. To prevent this, if the thickness of the SiNx film 103c is increased, the inter-wiring capacitance increases and the wiring delay increases.

  On the other hand, in order to prevent these problems, there is a method of stopping the GCIB irradiation before forming the SiNx film 103c. However, the formation of CuSiN 103a by GCIB largely depends on the Cu surface state, and the size of the gas cluster also varies, so when trying to form CuSiN 103a with the same film thickness within the wafer surface or between wafers / lots, Variations occur in the irradiation time of gas clusters and ion beams necessary for this.

  Therefore, in order to secure the CuSiN 103a having a film thickness necessary for improving the EM resistance, it is necessary to have a considerable margin in the irradiation time. In this case, it is not possible to form no SiNx 103c on the entire surface of the wafer. Is possible.

  The present invention solves the above-mentioned conventional problems, and while ensuring sufficient EM resistance for wiring, it can reduce wiring interlayer / line leakage and improve the TDDB life, and at the time of via etching. Provided are a semiconductor device and a method for manufacturing the same, which can ensure a high selection ratio and obtain highly reliable wiring.

  In order to solve the above-described problems, a semiconductor device according to claim 1 of the present invention includes a wiring groove formed in a layer forming insulating film on a semiconductor substrate, and a conductor formed so as to fill the wiring groove. And an alloy layer formed on the surface of the film made of the conductor, and an insulating barrier film containing nitrogen and silicon formed on the alloy layer and on the layer-forming insulating film. The alloy layer is an alloy layer of the conductor and silicon or an alloy layer of the conductor, silicon and nitrogen, and the insulating barrier film containing nitrogen and silicon has a higher density than the layer-forming insulating film. It is a film, and a layer containing nitrogen is formed in an upper part of the layer forming insulating film.

  A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the insulating barrier film is a laminated film of a SiNx film, a SiCN film, a SiCO film, and a SiCN film, or BN. It is characterized by having.

  According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: a step (a) of forming a wiring trench in a layer-forming insulating film formed on a semiconductor substrate; and the step (a), A step (b) of forming a wiring by depositing a film made of a conductor in the wiring groove; and after the step (b), the conductor and the silicon or the conductor on the surface of the film made of the conductor. A step (c) of forming an alloy layer of silicon and nitrogen, and forming an insulating barrier film containing nitrogen and silicon on the alloy layer and the layer-forming insulating film, and after the step (c), And a step (d) of treating the insulating barrier film containing nitrogen and silicon so as to have a higher density than the layer-forming insulating film.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the third aspect, wherein the step (d) includes UV curing, EB curing, annealing, or plasma processing. It is characterized by performing by.

  According to a fifth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a step (a) of forming a wiring trench in a layer forming insulating film formed on a semiconductor substrate; and the step (a), A step (b) of forming a wiring by depositing a film made of a conductor in a wiring groove; and after the step (b), the conductor and silicon or the conductor on the surface of the film made of the conductor. A step (c) of forming an alloy layer of silicon and nitrogen, and forming an insulating barrier film containing nitrogen and silicon on the alloy layer and the layer-forming insulating film, and after the step (c), And (d) removing the insulating barrier film containing nitrogen and silicon.

  The semiconductor device manufacturing method according to claim 6 of the present invention is the semiconductor device manufacturing method according to claim 5, wherein the alloy layer and the layer-forming insulating film are formed after the step (d). And (e) forming an insulating barrier film on the substrate.

  The semiconductor device manufacturing method according to claim 7 of the present invention is the semiconductor device manufacturing method according to claim 6, wherein the step (e) is performed by a plasma CVD method. To do.

  A method for manufacturing a semiconductor device according to claim 8 of the present invention is a method for manufacturing a semiconductor device according to any one of claims 3 to 7, wherein the step (c) It is performed by irradiation with an ion beam.

  A method for manufacturing a semiconductor device according to claim 9 of the present invention is the method for manufacturing a semiconductor device according to claim 8, wherein the gas cluster ion beam irradiation, the UV cure or the EB cure or The annealing or plasma treatment is continuously performed in the same apparatus.

  The semiconductor device manufacturing method according to claim 10 of the present invention is the semiconductor device manufacturing method according to claim 4 or 9, wherein the plasma treatment is performed by using an inert gas or a gas containing nitrogen. It is characterized by performing using.

  In addition, a semiconductor device manufacturing method according to an eleventh aspect of the present invention is the semiconductor device manufacturing method according to any one of the eighth to tenth aspects, wherein the gas cluster ion beam includes silane, It is formed by using any gas cluster ion of nitrogen, ammonia, or helium.

  A semiconductor device manufacturing method according to claim 12 of the present invention is the semiconductor device manufacturing method according to claim 6, wherein the insulating barrier film is a SiNx film, a SiCN film, a SiCO film, and a SiCN. It has a stacked film of films or BN.

  As described above, according to the present invention, a CuSiN layer is formed by irradiating a gas cluster / ion beam on the wiring, thereby improving the EM resistance of the wiring and forming a high-density and high-quality insulating film barrier. can do.

  Therefore, while ensuring sufficient EM resistance for wiring, it is possible to reduce wiring interlayer / line-to-line leakage and improve TDDB life, and to secure a high selection ratio during via etching and to provide highly reliable wiring. Obtainable.

Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be specifically described with reference to the drawings. Note that <> indicates a representative film thickness or dimension.
The manufacturing method of the semiconductor device of this embodiment includes, as basic steps, a step of forming a groove pattern in a layer-forming insulating film formed on a semiconductor substrate, and a barrier layer and copper as the upper layer of the layer-forming insulating film. A step of sequentially forming a film as a component, and a surface of the film containing copper as a main component and an exposed surface of the barrier layer are planarized by a chemical mechanical polishing method, and the copper as a main component only in the groove pattern A step of leaving the film and the barrier layer, and an alloy layer of copper and silicon or copper and silicon and nitrogen on the film mainly composed of copper embedded in the groove pattern by irradiation with a gas cluster ion beam And a step of forming a silicon nitride film on the entire surface thereof, and a step of performing UV cure, EB cure, annealing or plasma treatment.

In addition, as a basic process in another manufacturing method, a step of forming a groove pattern in a layer-forming insulating film formed on a semiconductor substrate, and a barrier layer and a film mainly composed of copper are formed on the layer-forming insulating film. A step of sequentially forming the surface of the copper-based film and the exposed surface of the barrier layer by chemical mechanical polishing, the copper-based film only in the groove pattern, and A step of leaving the barrier layer; irradiation with a gas cluster ion beam; and a copper-silicon or copper-silicon-nitrogen alloy layer on the copper-based film embedded in the groove pattern; The method includes a step of forming a silicon nitride film and a step of removing the silicon nitride film by wet etching.
(Embodiment 1)
Hereinafter, the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described.

FIG. 1 is a cross-sectional view showing each step in the method of manufacturing a semiconductor device according to the first embodiment.
First, a first insulating film 1 <150 nm> as a layer forming insulating film made of a carbon-containing silicon oxide film (SiOC) which is a low dielectric constant film on a silicon substrate (not shown) and a plasma oxide film (not shown). ) <30 nm> is formed. Thereafter, a first metal wiring groove pattern is formed by a photolithography method, and the plasma oxide film and the first insulating film 1 are etched away to a total of 170 nm by a dry etching method to form a wiring groove M1.

Thereafter, a tantalum-based barrier metal 2a <15 nm> and a seed Cu layer <30 nm> are formed by sputtering, and then a Cu film 2b <400 nm> is formed by electroplating, followed by annealing in an N ₂ atmosphere <300 ° C. >, The Cu film 2b and the barrier metal 2a other than those in the wiring trench M1 are removed by CMP, and the entire surface of the plasma oxide film and the SiOC film 1 are scraped by 20 nm to obtain the first Cu wiring 2 <high S: 120 nm> is formed (FIG. 1A).

Next, the surface is irradiated with a gas cluster ion beam made of SiH ₄ , N ₂ and He by the GCIB method. At this time, although the portion where the Cu surface are exposed CuSiN layer 3a reacts Cu and SiH ₄ and _{N 2} is formed, is now the Cu surface is covered with CuSiN layer 3a is SiH ₄ and _{N 2} By reacting, a silicon nitride (SiNx) film 3c <30 nm> is formed. On the other hand, a reaction layer 3b of SiOC, SiH ₄ and N ₂ is formed on the first insulating film 1, and thereafter, a SiNx film 3c is formed (FIG. 1B).

Thereafter, UV curing is performed to increase the density of the SiNx film 3c to form the SiNx film 3d (FIG. 1C).
Thereafter, a second insulating film 4 <240 nm> and a plasma oxide film 5 <80 nm> are formed as a layer forming insulating film made of SiOC for forming an upper wiring. Thereafter, a via hole H1 (FIG. 1D) is formed by a photolithography method, a dry etching method, ashing and cleaning by a normal dual damascene method. The via etching at this time prevents the SiNx film 3d from being completely removed.

  After that, the via hole H1 is filled and flattened with a resist plug, and then a wiring trench M2 (FIG. 1 (e)) is formed by photolithography, dry etching, ashing and cleaning, and then the entire bottom surface of the via hole H1 is etched. The SiNx film 3d is removed and washed (FIG. 1 (f)). During this entire surface etching, the plasma oxide film 5 on the surface is also removed by <50 nm>. At this time, the CuSiN layer 3a at the bottom of the via hole H1 may or may not be removed.

Thereafter, annealing in an H ₂ atmosphere is performed to reduce the oxide film on Cu at the bottom of the via hole H1, and the tantalum-based barrier metal 6a <15 nm> and the seed Cu layer <30 nm> are sputtered without being released to the atmosphere. After that, a Cu film 6b <400 nm> is formed by an electroplating method, and after annealing <300 ° C.> in an N ₂ atmosphere, the Cu film 6b other than the inside of the wiring trench M2 and the barrier are formed by a CMP method. The metal 6a is removed, and all of the plasma oxide film 5 and the surface of the SiOC film 4 are scraped by 20 nm to form a second Cu wiring 6 <height: 120 nm>.

  Thereafter, the CuSiN layer 7a, the reaction layer 7b, and the SiNx film are formed again by the GCIB method, and further UV curing is performed to form a densified SiNx film 7d (FIG. 1 (g)). By repeating the above steps, a multilayer wiring can be formed.

  According to the first embodiment described above, since the SiNx film formed by the GCIB method can be densified by UV curing, SiNx films 3d and 7d having good film quality can be obtained. Therefore, since the barrier property of the SiNx film can be sufficiently secured, the interlayer leakage between the first Cu wiring 2 and the second Cu wiring 6 can be reduced, and the TDDB life can be improved. The barrier property of the SiNx film referred to here is a barrier property against Cu diffusion and moisture.

  At the same time, the film quality of the interface between the first insulating film 1, the reaction layer 3b, and the SiNx film 3d is also improved, so that the leakage between the wirings between the first Cu wirings 2 and between the second Cu wirings 6 And the TDDB life is improved, and the adhesion between layers and films is also improved.

  In addition, since the SiNx film 3d becomes a high-density film at the time of via etching for forming a via hole at the time of forming the upper layer wiring (see FIG. 1D), it is possible to ensure a high etching selectivity with the second insulating film 4. As a result, the SiNx film thickness can be reduced while ensuring good contact characteristics, so that the effective dielectric constant between wirings can be lowered and wiring delay can be reduced.

In the first embodiment, UV cure is used to increase the density of the SiNx film. However, EB (Electron Beam) cure, about 300 to 400 ° C. (preferably about 300 to 400 ° C. is preferable, but 500 ° C. Density treatment by plasma treatment using rare gas such as annealing (furnace annealing, single wafer annealing, laser annealing, etc.), helium (He), argon (Ar) gas, etc. May be applied. All of these can promote densification and interatomic bonding by accelerating the de-polymerization reaction of the SiNx film by thermal energy, collision energy due to ions / electrons, and light energy such as ultraviolet rays. Here, due to UV curing, the SiNx film is a film having a higher density than an interlayer insulating film having a low dielectric constant (for example, a SiOC film (density: 1.2 kg / m ⁻³ or less)). It is known that a low dielectric constant insulating film generally has a high porosity. Therefore, the low dielectric constant insulating film has a low density. The SiNx film has a higher density due to UV curing (density: 2.2 to 3.0 kg / m ⁻³ ), but is at least higher than the density of the low dielectric constant insulating film. Here, the interlayer dielectric film having a low dielectric constant is not limited to the SiOC film.

Further, the reaction / bonding of the unreacted portion of the SiNx film may be promoted by plasma treatment using a reactive gas such as nitrogen (N ₂ ) gas or ammonia (NH ₃ ) gas. By using a reactive gas, in addition to the heat, collision, and light energy described above, bonding promotion and densification can be performed by reacting nitrogen (N) with unbound species. Moreover, you may apply repeatedly combining them.

By the way, as an example of He plasma conditions,

He: 180 sccm, pressure: 560 Pa
RF power: 1550W
Wafer temperature: 400 ° C

As an example of NH ₃ plasma conditions, in a 200 mm wafer compatible device,

NH ₃ : 300 sccm, pressure: 530 Pa
He: 100 sccm, pressure: 530 Pa
RF power: 400W
Wafer temperature: 400 ° C

In addition, after GCIB is performed, the above-described UV curing, EB curing, annealing, plasma processing, and the like are performed by another apparatus. However, since GCIB has a small irradiation spot, it is necessary to scan the wafer and irradiate the entire surface of the wafer, and the throughput is not so high.

  In addition, since the standing time from the GCIB irradiation to the UV curing or the like varies depending on the location, the film quality may slightly change depending on the location within the wafer depending on the standing time.

As a countermeasure, the above problem can be solved by using the apparatus shown in FIG.
In this apparatus, as shown in FIG. 2, the parts shown in 11 to 18 are parts corresponding to the GCIB apparatus, the parts shown in 19 to 21 are parts corresponding to the EB cure apparatus, and are mounted on the stage 17. The EB can be continuously irradiated on the wafer 16 after the GCIB irradiation.

  The GCIB apparatus includes a gas cluster nozzle 11, an ionizer 12, an acceleration high voltage electrode 13, a beam neutralizer 14, and an aperture 15, and irradiates a wafer 16 on a stage 17 with a gas cluster beam 18. By scanning the stage, the entire surface of the wafer can be irradiated with the gas cluster beam 18. The EB curing apparatus irradiates the desired wafer 16 with the deflecting magnet 21 after controlling the electron beam 22 generated from the EB tube 19 with the aperture 20.

  As described above, if the wafer is scanned with an apparatus that combines GCIB and EB cure, GCIB and EB cure can be continuously irradiated. Therefore, after depositing CuSiN and SiNx by GCIB, EB cure can be irradiated immediately. In addition, the processing time of combining GCIB and EB cure can be reduced, the throughput can be improved, and the standing time from GCIB to EB cure is constant regardless of the location, so that a uniform film quality can be realized in the wafer.

Moreover, since the space between GCIB and EB cure is not exposed to the atmosphere, there is no film quality fluctuation due to the influence of moisture adsorption or the like, and a good film quality can be obtained.
Similarly, the same effect can be obtained by using the same apparatus for the combination of GCIB and UV cure, GCIB and laser annealing, and GCIB and plasma treatment.

In addition, annealing can be performed immediately after GCIB without opening to the atmosphere by putting a heater on the stage.
(Embodiment 2)
Next, the semiconductor device and the manufacturing method thereof according to the second embodiment of the present invention will be described.

FIG. 3 is a cross-sectional view showing each step in the method of manufacturing the semiconductor device according to the second embodiment.
As in FIG. 1A of the first embodiment, a first insulating film 1 as a layer forming insulating film made of a carbon-containing silicon oxide film (SiOC) that is a low dielectric constant film on a silicon substrate, and a tantalum-based film A first Cu wiring 2 made of a barrier metal 2a and a Cu film 2b is formed (FIG. 3A).

Next, the surface is irradiated with a gas cluster ion beam made of SiH ₄ , N ₂ and He by the GCIB method. In this case, the portion where the Cu surface is exposed is Cu and SiH ₄ and _{N 2} are the reaction was CuSiN layer 33a is formed, so that the Cu surface in CuSiN layer is covered in turn with SiH ₄ N ₂ reacts to form a silicon nitride (SiNx) film 33c. On the other hand, a reaction layer 33b of SiOC, SiH ₄ and N ₂ is formed on the first insulating film 1, and thereafter, a SiNx film 33c is formed (FIG. 3B).

  Thereafter, the SiNx film 33c is removed by wet etching (FIG. 3C). If, for example, an HF system is used as the chemical solution used at this time, the SiNx film 33c can be securely formed while ensuring a selectivity with the CuSiN layer 33a, the Cu film 2b, the tantalum-based barrier metal 2a, and the first insulating film 1 made of SiOC. It is possible to remove.

Thereafter, after NH ₃ plasma treatment, a liner film 33d <30 nm> of SiCO (upper) / SiCN (lower) or the like or SiNx is formed by plasma CVD (FIG. 3D).
Thereafter, in the same manner as in the first embodiment, a second insulating film 4 <240 nm> and a plasma oxide film 5 <80 nm> are formed as a layer-forming insulating film made of SiOC for forming an upper layer wiring. Thereafter, a via hole H1 (FIG. 3E) is formed by a photolithography method, a dry etching method, ashing and cleaning by a normal dual damascene method. At this time, the via etching does not completely remove the liner film 33d.

  After that, the via hole H1 is filled with a resist plug and planarized, and then a wiring trench M2 (FIG. 3F) is formed by photolithography, dry etching, ashing, and cleaning, and then the entire surface of the via hole H1 is etched. The bottom liner film 33d is removed and cleaning is performed (FIG. 3G). During this entire surface etching, the plasma oxide film 5 on the surface is also removed by <50 nm>. At this time, the CuSiN layer 33a at the bottom of the via hole H1 may or may not be removed.

Thereafter, annealing in an H ₂ atmosphere is performed to reduce the oxide film on Cu at the bottom of the via hole H1, and the tantalum-based barrier metal 6a <15 nm> and the seed Cu layer <30 nm> are formed by sputtering without opening to the atmosphere. After forming a film, a Cu film 6b <400 nm> is formed by electroplating, and after annealing <300 ° C.> in an N ₂ atmosphere, the Cu film 6b and the barrier other than those in the wiring trench M2 are formed by CMP. The metal 6a is removed, and all of the plasma oxide film 5 and the surface of the SiOC film are scraped by 20 nm to form a second Cu wiring 6 <height: 120 nm>.

Thereafter, the CuSiN layer 37a, the reaction layer 37b, and the SiNx film are formed again by the GCIB method, the SiNx film is removed by wet etching, and then the NH ₃ plasma treatment is performed. Then, the SiCN single layer film or the SiCO (upper) / A laminated film such as SiCN (lower), a liner film 37d <30 nm> of SiNx, and a BN (boron nitride) film are formed by plasma CVD (FIG. 3H). A multilayer wiring can be formed by repeating the above steps. Here, the SiCO film is an Si-based O bonded. In addition, the SiOC film is based on the Si—O skeleton, and the density of the SiOC film having the Si—O skeleton with —CH ₃ group is lower than that of the SiCO film due to the difference in the skeleton base. ing.

  According to the GCIB method, the CuSiN layer formation time greatly depends on the Cu surface state. Therefore, due to variations in the Cu surface state, the time until the desired CuSiN layer is formed varies depending on the location. Therefore, when the desired CuSiN layer is secured over the entire wafer surface, there is always a place where a SiNx film with poor film quality can be formed. In addition, the film thickness varies (see FIG. 3B).

  However, according to the second embodiment, it is possible to remove the SiNx film 33c having a poor film quality and uneven film thickness formed by the GCIB method, and a new film quality and a good film thickness uniformity by the plasma CVD method. 33d can be formed.

  Therefore, since the barrier properties of the liner films 33d and 37d can be sufficiently secured, the interlayer leakage between the first Cu wiring 2 and the second Cu wiring 6 can be reduced, and the TDDB life is improved. At the same time, since the film quality is improved at the interface between the first insulating film 1, the reaction layer 33b, and the SiNx layer 33d, the leakage between the first Cu wirings 2 and between the second Cu wirings 6 is reduced. The TDDB life is improved and the adhesion is also improved.

  In addition, since the liner film 33d becomes a high-density film at the time of via etching for forming a via hole at the time of forming the upper layer wiring (see FIG. 3E), it is possible to secure a high etching selectivity with the second insulating film 4. For this reason, the liner films 33d and 37d can be made thin while ensuring good contact characteristics, so that the effective dielectric constant between the wirings can be lowered and the wiring delay can be reduced.

Incidentally, in the conventional example, the reaction layer 103b of SiOC, SiH ₄ and N ₂ and the SiNx film 103c thereon have a structure in which the components gradually and gradually change, but the structure finished in the present embodiment. Then, since the reaction layer 33b of SiOC, SiH ₄ and N ₂ and the liner film 33d are not continuous, the interface is clear.

  In addition, after forming the SiNx film by GCIB irradiation performed in the first embodiment, after performing UV curing or the like, the above-described wet etching is performed to remove the remaining SiNx film that is not sufficiently densified, thereby improving the film quality. It is effective enough to do.

  The semiconductor device and the manufacturing method thereof of the present invention can reduce the leakage between the wiring layers and between the lines and improve the TDDB life while ensuring sufficient EM resistance for the wiring, and also provide a high selection ratio at the time of via etching. It is possible to secure a highly reliable wiring, and it is useful for a technique for improving reliability by forming a conductor cap film on the wiring.

Sectional drawing which shows each process in the manufacturing method of the semiconductor device of Embodiment 1 of this invention The conceptual diagram of the manufacturing apparatus for performing GCIB and UV cure with the same apparatus in the manufacturing method of the semiconductor device of Embodiment 1 Sectional drawing which shows each process in the manufacturing method of the semiconductor device of Embodiment 2 of this invention Sectional drawing which shows each process in the manufacturing method of the conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st insulating film 2 1st Cu wiring 2a Tantalum system barrier metal 2b Cu film 3a, 33a CuSiN layer 3c, 33c Silicon nitride (SiNx) film 3b, 33b Reaction layer 3d (densified) SiNx film 33d , 37d (densified) SiNx liner film 4 second insulating film 5 plasma oxide film 6 second Cu wiring 6a tantalum-based barrier metal 6b Cu film 7a, 37a CuSiN layer 7b, 37b reaction layer 7d (high density) SiNx film M1, M2 Wiring trench H1 Via hole

Claims (12)

A wiring groove formed in a layer forming insulating film on the semiconductor substrate;
A film made of a conductor formed so as to fill the wiring trench;
An alloy layer formed on the surface of the film made of the conductor;
An insulating barrier film containing nitrogen and silicon formed on the alloy layer and on the layer-forming insulating film;
The alloy layer is an alloy layer of the conductor and silicon or an alloy layer of the conductor, silicon and nitrogen,
The insulating barrier film containing nitrogen and silicon is a film having a higher density than the layer forming insulating film,
A semiconductor device, wherein a layer containing nitrogen is formed in an upper portion of the layer forming insulating film.   The semiconductor device according to claim 1, wherein the insulating barrier film includes a SiNx film, a SiCN film, a SiCO film, and a laminated film of a SiCN film or BN. Forming a wiring groove in a layer-forming insulating film formed on the semiconductor substrate;
A step (b) of forming a wiring by depositing a film made of a conductor in the wiring groove after the step (a);
After the step (b), an alloy layer of the conductor and silicon or the conductor and silicon and nitrogen is formed on the surface of the film made of the conductor, and is formed on the alloy layer and the layer forming insulating film. Forming an insulating barrier film containing nitrogen and silicon on (c),
And a step (d) of processing the insulating barrier film containing nitrogen and silicon so as to have a higher density than the layer-forming insulating film after the step (c). .   The method of manufacturing a semiconductor device according to claim 3, wherein the step (d) is performed by UV curing, EB curing, annealing, or plasma processing. Forming a wiring groove in a layer-forming insulating film formed on the semiconductor substrate;
A step (b) of forming a wiring by depositing a film made of a conductor in the wiring groove after the step (a);
After the step (b), an alloy layer of the conductor and silicon or the conductor and silicon and nitrogen is formed on the surface of the film made of the conductor, and the alloy layer and the layer-forming insulating film are formed. Forming an insulating barrier film containing nitrogen and silicon on (c),
And (d) removing the insulating barrier film containing nitrogen and silicon after the step (c).   6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step (e) of forming an insulating barrier film on the alloy layer and the layer forming insulating film after the step (d). .   The method of manufacturing a semiconductor device according to claim 6, wherein the step (e) is performed by a plasma CVD method.   8. The method of manufacturing a semiconductor device according to claim 3, wherein the step (c) is performed by irradiation with a gas cluster ion beam. The gas cluster ion beam irradiation;
The UV cure or the EB cure or the annealing or plasma treatment
9. The method of manufacturing a semiconductor device according to claim 8, wherein the method is continuously executed in the same device.   The method for manufacturing a semiconductor device according to claim 4, wherein the plasma treatment is performed using an inert gas or a gas containing nitrogen.   11. The method of manufacturing a semiconductor device according to claim 8, wherein the gas cluster ion beam is formed by using any one of silane, nitrogen, ammonia, and helium gas cluster ions.   The method of manufacturing a semiconductor device according to claim 6, wherein the insulating barrier film includes a SiNx film, a SiCN film, a SiCO film, and a laminated film of a SiCN film or BN.

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