WO2010047038A1 - Semiconductor device and method for making same - Google Patents

Semiconductor device and method for making same Download PDF

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Publication number
WO2010047038A1
WO2010047038A1 PCT/JP2009/004685 JP2009004685W WO2010047038A1 WO 2010047038 A1 WO2010047038 A1 WO 2010047038A1 JP 2009004685 W JP2009004685 W JP 2009004685W WO 2010047038 A1 WO2010047038 A1 WO 2010047038A1
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WO
WIPO (PCT)
Prior art keywords
wiring
insulating film
interlayer insulating
film
semiconductor device
Prior art date
Application number
PCT/JP2009/004685
Other languages
French (fr)
Japanese (ja)
Inventor
小堀悦理
松本晋
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パナソニック株式会社
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Publication of WO2010047038A1 publication Critical patent/WO2010047038A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • FIG. 13 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
  • a barrier metal film is formed on the insulating film 300 and on the bottom and side walls of the wiring grooves 301a, 301b, and 301c by sputtering or the like, and then a seed film containing Cu is formed on the barrier metal film by sputtering or the like. To do. Thereafter, a plating film containing Cu is formed on the seed film by a plating method. In this manner, the conductive film containing Cu is embedded in the wiring trench 301 via the barrier metal film.
  • barrier metal films 302a, 302b, and 302c formed on the bottom and side walls of the wiring grooves 301a, 301b, and 301c, and the barrier metal film 302a in the wiring grooves 301a, 301b, and 301c.
  • 302b, and 302c wirings 305a, 305b, and 305c including conductive films 304a, 304b, and 304c embedded therein are formed.
  • FIG. 14 is a cross-sectional view showing a problem in a conventional method for manufacturing a semiconductor device.
  • a physical vapor deposition method (for example, a sputtering method) is used as a method for forming the barrier metal film and the seed film. Therefore, in each of the barrier metal film and the seed film, the portion formed on the insulating film tends to be formed thicker than the portions formed on the bottom and side walls of the wiring trench. In particular, in the seed film, the portion formed on the insulating film is formed much thicker than the portions formed on the bottom and side walls of the wiring trench, and as shown in FIG. There is a possibility that the overhang portions 303ax, 303bx, and 303cx are formed so as to protrude from the insulating film 300 into the wiring grooves 301a, 301b, and 301c.
  • the opposing overhang portions are in contact with each other and the wiring groove is closed.
  • the plating film cannot be embedded in the wiring groove, Voids are generated in the wiring.
  • the overhang portions 303ax, 303bx, and 303cx there is a high possibility that the overhang portions 303bx are in contact with each other. There is a high possibility.
  • conventionally there is a problem that a void is generated in the wiring due to the blockage of the wiring groove by the overhang portion.
  • FIG. 15 is a cross-sectional view showing a problem in a conventional method for manufacturing a semiconductor device.
  • the wiring trench having a high aspect ratio is particularly affected.
  • the wiring groove 401 b is not blocked by the overhang portion 403 bx, but the seed film 403 is not formed on the barrier metal film 402 in the wiring groove 401 b, resulting in poor formation of the seed film 403. Therefore, when the plating film is formed on the seed film, the plating film cannot be embedded with high precision in the wiring groove without the seed film, and voids are generated in the wiring.
  • an object of the present invention is to prevent a wiring groove from being blocked by an overhang portion and prevent a void from being generated without causing a seed film formation failure.
  • a semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate and a first first insulating film formed on the first interlayer insulating film.
  • the first wiring includes the first first wiring portion and the first second wiring portion, and is divided into a plurality of stages (for example, two stages). The Thereby, even if the aspect ratio of the first wiring is high, the aspect ratio of each wiring portion can be reduced. Therefore, it is possible to prevent the occurrence of voids in each wiring part. Therefore, the first wiring can be realized without generating voids.
  • the semiconductor device further includes a second wiring composed of a second first wiring portion formed in the first interlayer insulating film, and the height of the second first wiring portion is: It is preferable that the height of the second wiring is substantially the same as the height of the first first wiring portion, and the wiring height of the second wiring is lower than that of the first wiring.
  • the wiring width of the second wiring is substantially the same as the wiring width of the first wiring, and the resistance of the second wiring is higher than the resistance of the first wiring. It is preferable.
  • the semiconductor device further includes a second via portion formed in the second interlayer insulating film and connected to the second first wiring portion, and the height of the second via portion is: It is preferable that the height is substantially the same as the height of the first second wiring portion.
  • the first first wiring portion includes a barrier metal film formed on a bottom surface and a side wall of the wiring groove provided in the first interlayer insulating film, and in the wiring groove.
  • the first second wiring portion includes a barrier metal film formed on a side wall of a wiring trench provided in the second interlayer insulating film, and the wiring.
  • the conductive film is embedded through the barrier metal film.
  • the conductive film is formed in contact with the conductive film forming the first wiring portion, and is formed of a conductive film buried in the trench through the barrier metal film. It is preferable.
  • the cross-sectional shape of the first second wiring portion is a shape in which the bottom surface width is smaller than the top surface width.
  • the third interlayer insulating film formed on the second interlayer insulating film and the third interlayer insulating film are connected to the first second wiring portion.
  • a via, a third first wiring portion formed in the third interlayer insulating film and connected to the via, a fourth interlayer insulating film formed on the third interlayer insulating film, and a fourth interlayer insulation A third wiring formed on the film and connected to the third first wiring portion; and a third wiring comprising the third first wiring portion and the third second wiring portion. It is preferable to be configured.
  • the first interlayer insulating film and the second interlayer insulating film are preferably SiOC films.
  • the aspect ratio of the first wiring is preferably 0.5 or more and 1.0 or less.
  • the wiring width of the first wiring is preferably 70 nm or less.
  • the semiconductor device further includes a cap film that is formed between the first first wiring portion and the first second wiring portion and covers the surface of the first first wiring portion.
  • the cap film preferably includes a metal, and the first first wiring part is electrically connected to the first second wiring part via the cap film.
  • the metal is preferably Ti, W, Mo, Hf, or Zr.
  • a method of manufacturing a semiconductor device includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate, and a first interlayer insulating film.
  • the first wiring includes the first first wiring portion and the first second wiring portion, and is divided into a plurality of stages (for example, two stages). Configured.
  • the aspect ratio of the first wiring is high, the aspect ratio of each wiring portion can be reduced.
  • the first wiring can be realized without generating voids.
  • the step (b) further includes a step of forming a second first wiring portion in the first interlayer insulating film.
  • the second wiring composed of the two first wiring portions is configured.
  • the step (d) further includes a step of forming a second via portion connected to the second first wiring portion in the second interlayer insulating film. It is preferable.
  • the step (b) includes a step (b1) of forming a first wiring groove in the first interlayer insulating film, and a step formed on the bottom surface and the side wall of the first wiring groove.
  • the steps (b2) and (b2) of forming the first barrier metal film the first conductive film is embedded in the first wiring groove, and the first barrier metal film is interposed through the first barrier metal film.
  • the step (d3) includes a step (b3) of forming a first first wiring portion in which one conductive film is embedded.
  • the second conductive film is embedded in the second wiring trench, And (d3) forming a first second wiring portion in which the second conductive film is embedded via the second barrier metal film.
  • the second conductive film is preferably formed in contact with the first conductive film.
  • a cap film containing a metal is formed on the surface of the first first wiring portion after the step (b) and before the step (c). It is preferable that the method further includes a step (e), and the step (d1) is a step of forming a second wiring groove that exposes the surface of the cap film by etching using a fluorine-containing gas containing fluorine as an etching gas. .
  • the cap film is exposed in the second wiring groove instead of the first first wiring part, the metal (for example, copper) contained in the first conductive film in the first first wiring part is exposed. It is not sputtered. Therefore, even when, for example, a fluorine-containing gas is used as the etching gas, the fluorine atoms contained in the fluorine-containing gas are not trapped in the sputtered copper. Fluoride does not adhere and the etching rate can be stabilized.
  • a fluorine-containing gas is used as the etching gas
  • the metal contained in the cap film exposed in the second wiring trench is sputtered, and fluorine atoms contained in the fluorine-containing gas are trapped in the sputtered metal, thereby generating a metal fluoride. Even so, the metal fluoride vapor pressure is higher than the copper fluoride vapor pressure, so the metal fluoride can be exhausted outside the chamber without adhering to the inner wall of the chamber. The etching rate can be stabilized.
  • the metal is preferably Ti, W, Mo, Hf, or Zr.
  • the vapor pressure of the fluoride of Ti, W, Mo, Hf or Zr is higher than the vapor pressure of the fluoride of Cu.
  • a groove is formed in the second interlayer insulating film by first etching using a fluorine-containing gas containing fluorine as an etching gas. And the second etching using a rare gas as an etching gas to remove the second interlayer insulating film exposed in the trench, and the surface of the first first wiring portion is formed on the second interlayer insulating film. Forming a second wiring groove that exposes the groove, and in the step of forming the groove, the groove is formed so that the surface of the first first wiring portion is not exposed in the groove. It is preferable.
  • the metal for example, copper
  • the rare gas does not react with copper, the rare gas is not trapped by the sputtered copper, so that the etching rate can be stabilized.
  • the metal (for example, copper) contained in the first conductive film in the first first wiring part is sputtered so that the first first wiring part is not exposed in the groove. Absent. Therefore, even when, for example, a fluorine-containing gas is used as an etching gas, the fluorine atoms contained in the fluorine-containing gas are not trapped in the sputtered copper, so that the chamber in which the first etching is performed is performed. In this case, copper fluoride does not adhere to the inner wall, and the etching rate can be stabilized.
  • a fluorine-containing gas is used as an etching gas
  • the second wiring groove in the second barrier metal film is formed. It is preferable that it is the process of removing the part formed in the bottom face.
  • a step (f) of forming a third interlayer insulating film on the second interlayer insulating film after the step (d), and a third interlayer insulating film A step (g) of forming a via connected to the first second wiring portion and a third first wiring portion connected to the via; and after the step (g), on the third interlayer insulating film A step (h) of forming a fourth interlayer insulating film, a step (i) of forming a third second wiring portion connected to the third first wiring portion in the fourth interlayer insulating film, and In the step (i), it is preferable that a third wiring composed of a third first wiring portion and a third second wiring portion is configured.
  • the step (g) includes a step (g1) of forming a via hole and a wiring groove in the third interlayer insulating film, and forming a via in the via hole. And a step (g2) of forming a third first wiring portion in the wiring groove.
  • the first wiring includes the first first wiring portion and the first second wiring portion, and includes a plurality of stages (for example, two stages). It is configured separately. Thereby, even if the aspect ratio of the first wiring is high, the aspect ratio of each wiring portion can be reduced. For this reason, in each wiring part, it is possible to prevent the formation of the seed film, and the wiring groove can be prevented from being blocked by the overhang part. Therefore, it is possible to prevent the occurrence of voids in each wiring part. Therefore, the first wiring can be realized without generating voids.
  • FIGS. 1A to 1C are cross-sectional views of relevant steps showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.
  • 2 (a) to 2 (c) are cross-sectional views of essential parts showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.
  • FIGS. 3A to 3C are cross-sectional views of relevant steps showing the semiconductor device manufacturing method according to the first embodiment of the present invention in the order of steps.
  • FIGS. 4A and 4B are diagrams showing the configuration of the semiconductor device according to the first embodiment of the present invention.
  • FIGS. 4C and 4D are the configuration of the semiconductor device according to the comparative example.
  • FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 6 is a plan view showing a configuration of a semiconductor device according to the second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention.
  • FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention.
  • FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention.
  • FIG. 11A is a cross-sectional view when a global wiring is formed by applying the present invention
  • FIG. 11B is a cross-sectional view when a global wiring is formed without applying the present invention.
  • . 12 (a) to 12 (d) are cross-sectional views of relevant steps showing a method of manufacturing a semiconductor device according to Modification 3 of the first embodiment of the present invention in the order of steps.
  • FIG. 13 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
  • FIG. 14 is a cross-sectional view showing a problem in a conventional method for manufacturing a semiconductor device.
  • FIG. 15 is a cross-sectional view showing a problem in a conventional method for manufacturing a semiconductor device.
  • FIGS. 1A to FIG. 3C are cross-sectional views of relevant parts showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.
  • the left region is a power wiring region A in which power wiring is formed
  • the central region is a signal wiring region B in which signal wiring is formed
  • the right region is The region is a low resistance wiring region C where a low resistance wiring is formed.
  • Power wiring is a wiring through which a large current flows because power (current) is supplied from the power source that operates the LSI.
  • Signal wiring is a wiring that is used for a signal circuit and through which a minute current flows.
  • the “low resistance wiring” is a wiring that is used in a logic circuit and requires a high signal propagation speed.
  • an interlayer insulating film 10 is formed on a semiconductor substrate (not shown). Thereafter, wiring grooves 11a, 11b, and 11c are formed in the interlayer insulating film 10 by a known technique. Thereafter, barrier metal films 12a, 12b, and 12c are formed on the bottom and side walls of the wiring grooves 11a, 11b, and 11c by a known technique, and then, for example, copper is formed in the wiring grooves 11a, 11b, and 11c by a known technique.
  • the conductive films 13a, 13b and 13c made of (Cu) or the like are embedded.
  • the first wiring portion 14a composed of the barrier metal film 12a and the conductive film 13a is formed in the interlayer insulating film 10 in the power supply wiring region A, and the barrier metal is formed in the interlayer insulating film 10 in the signal wiring region B.
  • a first wiring portion 14b composed of the film 12b and the conductive film 13b is formed, and a first wiring portion 14c composed of the barrier metal film 12c and the conductive film 13c is formed in the interlayer insulating film 10 in the low resistance wiring region C.
  • the liner insulating film 15 is formed on the interlayer insulating film 10 and the first wiring portions 14a, 14b, and 14c. Thereafter, an interlayer insulating film 16 is formed on the liner insulating film 15.
  • a wiring groove 17a is formed in the liner insulating film 15 and the interlayer insulating film 16 in the power supply wiring region A by a lithography technique and an etching technique, and the low resistance wiring region C is formed.
  • a wiring groove 17 c is formed in the liner insulating film 15 and the interlayer insulating film 16. At this time, the wiring grooves 17a and 17c are formed so that the cross-sectional shape thereof becomes a tapered shape whose width increases from the lower surface toward the upper surface.
  • a barrier metal film 18 is formed on the interlayer insulating film 16 and on the bottom and side walls of the wiring grooves 17a and 17c by sputtering. Thereafter, the portion of the barrier metal film 18 formed on the bottom surfaces of the wiring grooves 17a and 17c is removed by reverse sputtering to expose the upper surfaces of the first wiring portions 14a and 14c. Thereafter, a seed film made of, for example, copper (Cu) is formed on the first wiring portions 14a and 14c and the barrier metal film 18 exposed in the wiring grooves 17a and 17c by sputtering. Thereafter, a plating film made of, for example, copper (Cu) or the like is formed on the seed film by plating. In this way, the conductive film 19 is embedded in the wiring grooves 17a and 17c via the barrier metal film 18.
  • the boundary line between the seed film and the plating film in the conductive film 19 is not illustrated because it is difficult to illustrate.
  • the portions of the conductive film 19 and the barrier metal film 18 formed outside the wiring grooves 17a and 17c are removed by CMP.
  • the second wiring portion 20a composed of the barrier metal film 18a and the conductive film 19a is formed in the liner insulating film 15 and the interlayer insulating film 16 in the power supply wiring region A, and the liner insulation in the low resistance wiring region C is formed.
  • a second wiring portion 20 c composed of a barrier metal film 18 c and a conductive film 19 c is formed on the film 15 and the interlayer insulating film 16.
  • a liner insulating film 21 is formed on the interlayer insulating film 16 and the second wiring portions 20a and 20c. Thereafter, an interlayer insulating film 22 is formed on the liner insulating film 21.
  • a wiring groove 23a is formed in the liner insulating film 21 and the interlayer insulating film 22 in the power supply wiring region A by lithography and etching techniques. At this time, the wiring groove 23a is formed so that the cross-sectional shape thereof becomes a tapered shape whose width increases from the lower surface toward the upper surface.
  • a barrier metal film 24 is formed on the interlayer insulating film 22 and on the bottom and side walls of the wiring groove 23a by sputtering. Thereafter, a portion of the barrier metal film 24 formed on the bottom surface of the wiring groove 23a is removed by reverse sputtering to expose the upper surface of the second wiring portion 20a. Thereafter, a seed film made of, for example, copper (Cu) or the like is formed on the second wiring portion 20a exposed in the wiring groove 23a and the barrier metal film 24 by sputtering. Thereafter, a plating film made of, for example, copper (Cu) or the like is formed on the seed film by plating. In this way, the conductive film 25 is embedded in the wiring groove 23 a via the barrier metal film 24.
  • the boundary line between the seed film and the plating film in the conductive film 25 is not illustrated because it is difficult to illustrate.
  • a portion of the conductive film 25 and the barrier metal film 24 formed outside the wiring trench 23a is removed by a CMP method.
  • the third wiring portion 26a composed of the barrier metal film 24a and the conductive film 25a is formed in the liner insulating film 21 and the interlayer insulating film 22 in the power supply wiring region A.
  • a liner insulating film 27 is formed on the interlayer insulating film 22 and the third wiring portion 26a.
  • the semiconductor device according to this embodiment can be manufactured.
  • the conductive film 19a of the second wiring portion 20a is formed in contact with the conductive film 13a of the first wiring portion 14a, and the third wiring The conductive film 25a of the part 26a is formed in contact with the conductive film 19a of the second wiring part 20a. Therefore, the first wiring part 14a, the second wiring part 20a, and the third wiring part 26a can be regarded as one wiring, and the first wiring part 14a and the second wiring part are included in the power supply wiring region A.
  • a wiring 26A composed of 20a and the third wiring portion 26a is configured.
  • a wiring 14B including the first wiring part 14b is configured.
  • the conductive film 19c of the second wiring part 20c is formed in contact with the conductive film 13c of the first wiring part 14c. Therefore, the first wiring portion 14c and the second wiring portion 20c can be regarded as one wiring, and the low resistance wiring region C includes a wiring made up of the first wiring portion 14c and the second wiring portion 20c. 20C is configured.
  • the semiconductor device includes an interlayer insulating film 10, a liner insulating film 15, an interlayer insulating film 16, and a liner insulating film sequentially formed on a semiconductor substrate (not shown).
  • Second wiring portions 20a and 20c connected to 14a and 14c, and a third wiring portion 26a formed on the liner insulating film 21 and the interlayer insulating film 22 and connected to the second wiring portion 20a are provided.
  • the power supply wiring area A includes the wiring 26A including the first wiring portion 14a, the second wiring portion 20a, and the third wiring portion 26a.
  • a wiring 14B including the first wiring portion 14b is configured in the signal wiring region B.
  • a wiring 20C including the first wiring part 14c and the second wiring part 20c is configured.
  • tantalum Ti
  • tantalum nitride TiN
  • ruthenium Ru
  • RuN ruthenium nitride
  • the interlayer insulating films 10, 16, and 22 are preferably films having a low dielectric constant.
  • a film having a relative dielectric constant of 2.2 to 4.5 is preferable.
  • Specific examples of these films include carbon (C) -containing SiOC films and porous SiOC films.
  • the liner insulating films 15, 21, and 27 are preferably films having a higher dielectric constant than the interlayer insulating films 10, 16, and 22.
  • a film having a relative dielectric constant of 4.5 or more and 7.0 or less is preferable.
  • Specific examples of these films include SiC films, SiCN films, and SiCO films.
  • wiring A a wiring having a relatively large cross sectional area
  • wiring B a wiring having a relatively small cross sectional area
  • the wiring 20C in the low resistance wiring region C has a larger cross-sectional area than the wiring 14B in the signal wiring region B, and the wiring 26A in the power wiring region A is in the low resistance wiring region C.
  • the cross-sectional area is large. Accordingly, the resistances of the wirings 26A, 14B, and 20C satisfy the relationship shown below.
  • Wiring 14B> Wiring 20C> Wiring 26A In this way, the wiring 26A in the power supply wiring region A is divided into three stages, and the cross-sectional area of the wiring 26A is increased (the resistance of the wiring 26A is reduced), whereby a power supply current (large current) is supplied to the wiring 26A. It can flow.
  • the wiring 20C in the low resistance wiring region C is divided into two stages, and the wiring 20C can be used as a low resistance wiring by increasing the cross-sectional area of the wiring 20C (reducing the resistance of the wiring 20C). it can.
  • the wiring 14B in the signal wiring region B does not need to flow a large current through the wiring 14B, and it is not necessary to use the wiring 14B as a low-resistance wiring, and thus is configured without being divided into multiple stages.
  • the wiring 26A in the power supply wiring area A includes the first wiring portion 14a, the second wiring portion 20a, and the third wiring portion 26a, and is configured in three stages.
  • aspect ratio means the wiring height / wiring width
  • the aspect ratio of each of the wiring portions 14a, 20a, and 26a is lowered. be able to. Therefore, in the wiring portions 14a, 20a, and 26a, when the seed film is formed by the sputtering method, it is possible to prevent the wiring grooves 11a, 17a, and 23a from being blocked by the overhang portion without causing a seed film formation failure. Therefore, it is possible to prevent voids from being generated in the wiring portions 14a, 20a, and 26a. Therefore, the wiring 26A can be realized without generating voids.
  • the wiring 20C in the low-resistance wiring region C includes a first wiring part 14c and a second wiring part 20c, and is configured in two stages.
  • the aspect ratio of the wiring 20C is high, the aspect ratio of each of the wiring portions 14c and 20c can be reduced. Therefore, in each of the wiring portions 14c and 20c, when the seed film is formed by the sputtering method, it is possible to prevent the wiring grooves 11c and 17c from being blocked by the overhang portion without causing a seed film formation failure. Generation of voids in the wiring portions 14c and 20c can be prevented. Therefore, the wiring 20C can be realized without generating voids.
  • the wiring heights H26A, H14B and H20C are made different so that the wirings 26A and 14B having different cross-sectional areas (that is, different resistances).
  • 20C. 4B is a plan view
  • FIG. 4A is a cross-sectional view taken along line IVa-IVa shown in FIG. 4B.
  • H104c are made substantially the same, while the wiring widths W104a, W104b, W104c are made different as shown in FIG. 4D, thereby realizing the wirings 104a, 104b, 104c having different cross-sectional areas.
  • 4D is a plan view
  • FIG. 4C is a cross-sectional view taken along line IVc-IVc shown in FIG. 4D.
  • the wiring widths are maximized by making the wiring widths substantially the same and different the wiring heights as in this embodiment. Since the width can be reduced, the chip size can be reduced.
  • the cross-sectional shapes of the second and third wiring portions 20a and 26a constituting the wiring 26A in the power supply wiring region A are tapered so that the width increases from the lower surface toward the upper surface. Therefore, for example, even if the second wiring portion 20a is formed closer to the first wiring portion 14b as shown in FIG. 5, the second wiring portion 20a is short-circuited with the first wiring portion 14b. Can be prevented.
  • the cross-sectional shape of the second wiring portion 20c constituting the wiring 20C in the low resistance wiring region C is tapered so that the width increases from the lower surface toward the upper surface.
  • the second and third wiring portions 20a, 20c, and 26a are tapered so that the width increases from the lower surface toward the upper surface, thereby forming the second and third wiring portions 20a, 20c, and 26a. Can be prevented from short-circuiting with other wiring portions.
  • the cross-sectional shape of the second wiring portions 20a and 20c is tapered so that the width increases from the lower surface toward the upper surface, thereby forming the wiring groove 17a as shown in FIG. , 17c, the conductive film 19 can be embedded with high accuracy.
  • the cross-sectional shape of the third wiring portion 26a is made into a tapered shape whose width increases from the lower surface to the upper surface, the conductive film 25 is formed in the wiring groove 23a as shown in FIG. Can be embedded with high accuracy.
  • the aspect ratio of the wiring 26A in the power supply wiring region A and the wiring 20C in the low resistance wiring region C is preferably 0.5 or more and 1.0 or less.
  • the present invention can be effectively exhibited.
  • the wiring width of the wiring 26A in the power supply wiring region A and the wiring 20C in the low resistance wiring region C is preferably 70 nm or less.
  • a wiring having a wiring width of 70 nm or less conventionally, there is a high possibility that a void will be generated in the wiring due to the blockage of the wiring groove by the overhang portion, and in the conventional technique, a void may be generated due to a seed film formation failure. Since this property is high, the present invention can be exhibited effectively.
  • FIG. 6 is a plan view showing a configuration of a semiconductor device according to the second embodiment of the present invention.
  • 7 to 10 are sectional views showing the configuration of the semiconductor device according to the second embodiment of the present invention. Specifically, FIG. 7 is a sectional view taken along line VII-VII shown in FIG. 8 is a sectional view taken along line VIII-VIII shown in FIG. 6, FIG. 9 is a sectional view taken along line IX-IX shown in FIG. 6, and FIG. 10 is a sectional view taken along line XX shown in FIG. FIG.
  • the left region is a power supply wiring region A where power supply wiring is formed
  • the central region is a signal wiring region B where signal wiring is formed
  • the right region is a low resistance wiring.
  • the low resistance wiring region C is formed.
  • the semiconductor device includes an interlayer insulating film 28, a liner insulating film 32, and an interlayer insulating film sequentially formed on the liner insulating film 27.
  • a film 33, a liner insulating film 37, and an interlayer insulating film 38 are further provided.
  • the semiconductor device includes a via 31 ax formed in the liner insulating film 27 and the interlayer insulating film 28 and a first layer formed in the interlayer insulating film 28 as illustrated in FIG. 8.
  • 1 wiring part 31ay, the 2nd wiring part 36a formed in the liner insulating film 32 and the interlayer insulating film 33, and the 3rd wiring part 41a formed in the liner insulating film 37 and the interlayer insulating film 38 are further provided. .
  • the via 31ax includes a barrier metal film 29ax formed on the bottom and side walls of the via hole, and a conductive film 30ax embedded in the via hole via the barrier metal film 29ax.
  • the first wiring portion 31ay includes a barrier metal film 29ay formed on the bottom and side walls of the wiring groove, and a conductive film 30ay embedded in the wiring groove via the barrier metal film 29ay.
  • the via 31ax and the first wiring portion 31ay are formed by a dual damascene method.
  • the second wiring portion 36a includes a barrier metal film 34a formed on the side wall of the wiring groove and a conductive film 35a embedded in the wiring groove via the barrier metal film 34a.
  • the third wiring portion 41a includes a barrier metal film 39a formed on the side wall of the wiring groove, and a conductive film 40a embedded in the wiring groove via the barrier metal film 39a.
  • the conductive film 35a of the second wiring part 36a is formed in contact with the conductive film 30ay of the first wiring part 31ay, and the conductive film 40a of the third wiring part 41a is formed in contact with the conductive film 35a of the second wiring part 36a.
  • a wiring 41A including the first wiring part 31ay, the second wiring part 36a, and the third wiring part 41a is configured.
  • the wiring 41A is connected to the wiring 26A via the via 31ax.
  • the semiconductor device includes the first via portion 20b formed in the liner insulating film 15 and the interlayer insulating film 16, the liner insulating film 21 and the interlayer as shown in FIG.
  • a second via portion 26 b formed in the insulating film 22, a via 31 bx formed in the liner insulating film 27 and the interlayer insulating film 28, and a first wiring portion 31 by formed in the interlayer insulating film 28 are provided.
  • the first via portion 20b includes a barrier metal film 18b formed on the side wall of the via hole and a conductive film 19b embedded in the via hole via the barrier metal film 18b.
  • the second via portion 26b includes a barrier metal film 24b formed on the sidewall of the via hole and a conductive film 25b embedded in the via hole via the barrier metal film 24b.
  • the conductive film 25b of the second via portion 26b is formed in contact with the conductive film 19b of the first via portion 20b. Therefore, the first via portion 20b and the second via portion 26b can be regarded as one via, and the signal wiring region B has a via 26Vb composed of the first via portion 20b and the second via portion 26b. Is configured.
  • the via 31bx includes a barrier metal film 29bx formed on the bottom and side walls of the via hole and a conductive film 30bx embedded in the via hole via the barrier metal film 29bx.
  • the first wiring part 31by includes a barrier metal film 29by formed on the bottom and side walls of the wiring groove, and a conductive film 30by embedded in the wiring groove via the barrier metal film 29by.
  • a wiring 31B is formed.
  • the via 31bx and the first wiring part 31by are formed by a dual damascene method.
  • the wiring 31B is connected to the wiring 14B via the via 31bx and the via 26Vb in this order.
  • the semiconductor device includes a first via portion 26c formed in the liner insulating film 21 and the interlayer insulating film 22, the liner insulating film 27, and the interlayer as shown in FIG. A via 31 cx formed in the insulating film 28, a first wiring part 31 cy formed in the interlayer insulating film 28, and a second wiring part 36 c formed in the liner insulating film 32 and the interlayer insulating film 33 are provided.
  • the first via portion 26c includes a barrier metal film 24c formed on the side wall of the via hole and a conductive film 25c embedded in the via hole via the barrier metal film 24c.
  • a via 26Vc composed of 26c is formed.
  • the via 31cx includes a barrier metal film 29cx formed on the bottom and side walls of the via hole and a conductive film 30cx embedded in the via hole via the barrier metal film 29cx.
  • the first wiring portion 31 cy includes a barrier metal film 29 cy formed on the bottom and side walls of the wiring groove, and a conductive film 30 cy embedded in the wiring groove via the barrier metal film 29 cy.
  • the via 31cx and the first wiring part 31cy are formed by a dual damascene method.
  • the second wiring portion 36c includes a barrier metal film 34c formed on the side wall of the wiring groove, and a conductive film 35c embedded in the wiring groove through the barrier metal film 34c.
  • the conductive film 35c of the second wiring portion 36c is formed in contact with the conductive film 30cy of the first wiring portion 31cy, and a wiring 36C including the first wiring portion 31cy and the second wiring portion 36c is configured.
  • the wiring 36C is connected to the wiring 20C through the via 31cx and the via 26Vc in this order.
  • wiring 26A in the power supply wiring area A, wiring 26A (see FIGS. 7 and 8) and wiring 41A (see FIG. 8) are configured.
  • a wiring 14B in the signal wiring region B, a wiring 14B (see FIGS. 7 and 9) and a wiring 31B (see FIG. 9) are configured.
  • a wiring 20C in the low resistance wiring region C, a wiring 20C (see FIGS. 7 and 10) and a wiring 36C (see FIG. 10) are configured.
  • the wiring 36C in the low resistance wiring region C has a larger cross-sectional area than the wiring 31B in the signal wiring region B, and the wiring 41A in the power supply wiring region A is compared with the wiring 36C in the low resistance wiring region C. Large cross-sectional area. Therefore, the resistances of the wirings 41A, 31B, and 36C satisfy the relationship shown below.
  • tantalum (Ta) as in the first embodiment. It is preferable to use tantalum nitride (TaN), ruthenium (Ru), or ruthenium nitride (RuN).
  • the material of the conductive films 19b, 25b, 25c, 30ax, 30bx, 30cx, 30ay, 30by, 30cy, 35a, 35c, and 40a for example, copper (Cu) is used as in the first embodiment. .
  • interlayer insulating films 28, 33, and 38 are preferably films having a low dielectric constant, as in the first embodiment.
  • the liner insulating films 32 and 37 are preferably films having a high dielectric constant, as in the first embodiment.
  • the aspect ratio of the wiring 41A in the power supply wiring area A and the wiring 36C in the low resistance wiring area C is preferably 0.5 or more and 1.0 or less, as in the first embodiment.
  • the wiring width of the wiring 41A in the power supply wiring region A and the wiring 36C in the low resistance wiring region C is preferably 70 nm or less, as in the first embodiment.
  • the seed film is formed by sputtering in each of the wiring portions 14a, 20a, 26a constituting the wiring 26A and each of the wiring portions 31ay, 36a, 41a constituting the wiring 41A.
  • the wiring grooves it is possible to prevent the wiring grooves from being blocked by the overhang portion without causing the formation failure of the seed film. Therefore, voids are generated in the wiring portions 14a, 20a, 26a, 31ay, 36a, and 41a. Can be prevented. Accordingly, the wirings 26A and 41A can be realized without generating voids.
  • the wirings 20C and 36C can be realized without generating voids.
  • the wiring widths of the wirings 26A and 41A in the power supply wiring region A, the wirings 14B and 31B in the signal wiring region B, and the wirings 20C and 36C in the low resistance wiring region C are minimized, and the chip size is reduced. Can be reduced.
  • the cross-sectional shapes of the second and third wiring portions 20a and 26a constituting the wiring 26A and the second and third wiring portions 36a and 41a constituting the wiring 41A are shown.
  • the taper has a width that increases from the lower surface toward the upper surface. Thereby, it is possible to prevent the second and third wiring portions 20a, 36a, 26a, and 41a from being short-circuited with other wirings.
  • the conductive films 19a, 35a, 25a, and 40a can be accurately embedded in the wiring grooves.
  • the cross-sectional shape of the second wiring part 20c constituting the wiring 20C and the second wiring part 36c constituting the wiring 36C is tapered so that the width increases from the lower surface to the upper surface. To do. Thereby, it is possible to prevent the second wiring portions 20c and 36c from being short-circuited with other wiring. At the same time, the conductive films 19c and 35c can be accurately embedded in the wiring grooves.
  • FIG. 1 when the present invention is applied to form a wiring having a wiring width of, for example, 70 nm or more and a wiring height of, for example, 1 ⁇ m or more (specifically, for example, a global wiring that reduces bonding damage), FIG. This will be described with reference to 11 (a).
  • the interlayer insulating film 50 includes a first wiring portion 54 (the first wiring portion 54 includes a barrier metal film 52 formed on the bottom and side walls of the wiring groove, and a barrier in the wiring groove.
  • the liner insulating film 55 and the interlayer insulating film 56 are sequentially formed on the interlayer insulating film 50 and the first wiring part 54.
  • the liner insulating film 55 and the interlayer insulating film 56 are provided with the second wiring portion 60 (the second wiring portion 60 is formed with a barrier metal film 58 formed on the sidewall of the wiring groove and a barrier metal film 58 in the wiring groove.
  • a liner insulating film 61 and an interlayer insulating film 62 are sequentially formed on the interlayer insulating film 56 and the second wiring portion 60.
  • a barrier metal film 64z is formed on the interlayer insulating film 62 and on the bottom and side walls of the wiring groove 63. Thereafter, a portion of the barrier metal film 64z formed on the bottom surface of the wiring groove 63 is removed. Thereafter, a conductive film 65z is formed on the second wiring portion 60 exposed in the wiring groove 63 and the barrier metal film 64z.
  • portions of the conductive film 65z and the barrier metal film 64z formed outside the wiring trench 63 are removed by CMP. In this manner, a third wiring portion in which the conductive film is embedded is formed in the wiring groove 63 via the barrier metal film.
  • a global wiring having the first wiring portion 54, the second wiring portion 60, and the third wiring portion and having a wiring width of, for example, 70 nm or more and a wiring height of, for example, 1 ⁇ m or more is formed.
  • a barrier metal film 252z is formed on the interlayer insulating film 250 and on the bottom and side walls of the wiring groove 251. Thereafter, a conductive film 253z is formed over the barrier metal film 252z.
  • portions of the conductive film 253z and the barrier metal film 252z formed outside the wiring trench 251 are removed by CMP. In this manner, a global wiring in which the conductive film is embedded is formed in the wiring trench 251 via the barrier metal film.
  • the conductive film 65z required to fill the wiring groove 63 is used. Can be made thinner than the film thickness of the conductive film 253z required to fill the wiring trench 251. Further, the amount of the conductive film 65z formed outside the wiring groove 63 is smaller than the amount of the conductive film 253z formed outside the wiring groove 251 and the amount of the conductive film 65z to be removed by the CMP method. Can be made smaller than the amount of the conductive film 253z to be removed by the CMP method.
  • the number of conductive film formation steps increases, but the thickness of the conductive film to be formed at a time can be reduced. Further, although the number of steps of removing the conductive film by the CMP method increases, the amount of the conductive film to be removed at a time can be reduced.
  • a first wiring portion is formed in the interlayer insulating film.
  • a cap film containing a metal is formed on the surface of the first wiring part (specifically, the first wiring part on which the second wiring part is formed in a later step).
  • a liner insulating film is formed on the interlayer insulating film and the cap film.
  • an interlayer insulating film is formed on the liner insulating film.
  • steps similar to those shown in FIGS. 1C to 3C in the first embodiment are sequentially performed, and the semiconductor device according to the present modification can be manufactured.
  • the first wiring portions 14a to 14c are formed in the interlayer insulating film 10 as shown in FIG. Thereafter, the liner insulating film 15 is formed on the interlayer insulating film 10 and the first wiring portions 14a to 14c. Thereafter, an interlayer insulating film 16 is formed on the liner insulating film 15. Thereafter, as shown in FIG. 1B, wiring grooves 17a and 17c are formed in the liner insulating film 15 and the interlayer insulating film 16 to expose the surfaces of the first wiring portions 14a and 14c.
  • a cap film containing a metal is formed on the surface of the first wiring part after the formation of the first wiring part and before the formation of the liner insulating film.
  • an interlayer insulating film is formed on the liner insulating film, and a wiring groove that exposes the surface of the cap film, not the surface of the first wiring portion, is formed in the liner insulating film and the interlayer insulating film.
  • the semiconductor device according to this modification further includes a cap film that is formed between the first wiring portion and the liner insulating film and covers the surface of the first wiring portion. I have.
  • the cap film includes a metal, and the first wiring part is electrically connected to the second wiring part via the cap film.
  • the first wiring portions 14a and 14c are etched by etching using, for example, a fluorine-containing gas as an etching gas.
  • a fluorine-containing gas as an etching gas.
  • the conductive films 13a and 13c in the first wiring portions 14a and 14c exposed in the wiring grooves 17a and 17c are made of, for example, copper. Therefore, when the conductive films 13a and 13c exposed in the wiring grooves 17a and 17c are etched using a fluorine-containing gas, the copper contained in the conductive films 13a and 13c is sputtered, and the sputtered copper However, there exists a possibility of adhering to the inner wall of a chamber. In general, fluorine atoms easily react with copper.
  • a cap film containing metal is formed on the surface of the first wiring part after the formation of the first wiring part and before the formation of the liner insulating film.
  • the metal contained in the cap film it is preferable to use a metal in which the vapor pressure of the metal fluoride is higher than the vapor pressure of the copper fluoride.
  • the metal contained in the cap film is preferably titanium (Ti), tungsten (W), molybdenum (Mo), hafnium (Hf), zirconium (Zr), or the like.
  • the metal contained in the cap film exposed in the wiring trench is sputtered, and fluorine atoms contained in the fluorine-containing gas are trapped in the sputtered metal, thereby generating a metal fluoride.
  • the metal fluoride since the vapor pressure of the metal fluoride is higher than the vapor pressure of the copper fluoride, the metal fluoride can be exhausted out of the chamber without adhering to the inner wall of the chamber. The rate can be stabilized.
  • a groove for exposing the upper surface of the liner insulating film is formed in the interlayer insulating film by etching using a fluorine-containing gas (first etching), for example.
  • first etching a fluorine-containing gas
  • second etching a rare gas
  • a wiring groove exposing the surface of the first wiring part is formed in the film.
  • a wiring groove 17a that exposes the surfaces of the first wiring portions 14a and 14c to the liner insulating film 15 and the interlayer insulating film 16 by, for example, one etching. , 17c.
  • a groove that exposes the upper surface of the liner insulating film is formed in the interlayer insulating film by the first etching, and then exposed in the groove by, for example, the second etching using a rare gas.
  • the liner insulating film to be removed is removed, and a wiring groove for exposing the surface of the first wiring portion is formed in the liner insulating film and the interlayer insulating film.
  • the wiring grooves 17a and 17c are formed in the chamber (not shown) by etching using, for example, a fluorine-containing gas as an etching gas.
  • a fluorine-containing gas as an etching gas.
  • a groove exposing the upper surface of the liner insulating film is formed in the interlayer insulating film by the first etching in the first chamber. Thereafter, in the second chamber, for example, the liner insulating film exposed in the trench is removed by a second etching using a rare gas, and the surface of the first wiring portion is exposed in the liner insulating film and the interlayer insulating film. A wiring groove to be formed is formed.
  • the rare gas In this way, even when copper contained in the conductive film in the first wiring portion exposed in the wiring groove is sputtered during the second etching, the rare gas generally reacts with copper. Therefore, the rare gas is not trapped by the sputtered copper, so that the etching rate can be stabilized.
  • the liner insulating film, not the first wiring portion, is exposed in the groove during the first etching, copper contained in the conductive film in the first wiring portion is not sputtered. Therefore, even when, for example, a fluorine-containing gas is used as an etching gas, fluorine atoms contained in the fluorine-containing gas are not trapped in the sputtered copper, and therefore, on the inner wall of the first chamber, Copper fluoride does not adhere, and the etching rate can be stabilized.
  • a groove that exposes the upper surface of the liner insulating film is formed in the interlayer insulating film by the first etching, and then the liner insulating film exposed in the groove is removed by the second etching,
  • the wiring groove for exposing the surface of the first wiring portion is formed in the liner insulating film and the interlayer insulating film has been described as a specific example, the present invention is not limited to this.
  • the interlayer insulating film and the liner insulating film exposed in the groove are removed by the second etching, and the liner insulating film and the interlayer insulating film are A wiring groove that exposes the surface of the first wiring portion may be formed. That is, the groove formed by the first etching may be formed so that the surface of the first wiring portion is not exposed.
  • FIGS. 12 (a) to 12 (d) are cross-sectional views of relevant steps showing a method of manufacturing a semiconductor device according to Modification 3 of the first embodiment of the present invention in the order of steps. 12 (a) to (d), the same reference numerals as those shown in FIGS. 1 (a) to 3 (c) are assigned to the same components as those in the first embodiment.
  • the liner insulating film 16 is formed on the interlayer insulating film 16 by etching using a fluorine-containing gas (first etching), for example. Grooves 70a and 70c that expose the upper surface of 15 are formed.
  • a sidewall barrier metal film 71 is formed on the interlayer insulating film 16 and on the bottom and sidewalls of the grooves 70a and 70c by, for example, sputtering. To do.
  • a third chamber (not shown) different from the first and second chambers, for example, by plasma etching (second etching) using a rare gas.
  • a portion of the sidewall barrier metal film 71 formed on the bottom surfaces of the grooves 70a and 70c is removed to form a groove exposing the upper surface of the liner insulating film 15, and then the liner insulating film 15 exposed in the groove is removed.
  • wiring grooves 17a and 17c that expose the surfaces of the first wiring portions 14a and 14c are formed.
  • the side walls of the wiring trenches 17 a and 17 c are covered with a side wall barrier metal film 71 as shown in FIG.
  • a barrier metal film 72 is formed on the side wall barrier metal film 71 and on the bottom and side walls of the wiring grooves 17a and 17c by sputtering. Thereafter, by reverse sputtering, portions of the barrier metal film 72 formed on the bottom surfaces of the wiring grooves 17a and 17c are removed, and the upper surfaces of the first wiring portions 14a and 14c are exposed. Thereafter, a seed film made of, for example, copper (Cu) is formed on the first wiring portions 14a and 14c and the barrier metal film 72 exposed in the wiring grooves 17a and 17c by sputtering. Thereafter, a plating film made of, for example, copper (Cu) or the like is formed on the seed film by plating. In this way, the conductive film 19 is embedded in the wiring grooves 17a and 17c via the barrier metal film 72.
  • Cu copper
  • the portions of the conductive film 19 and the barrier metal film 72 that are formed outside the wiring trenches 17a and 17c are removed by CMP, and the sidewall barrier metal film 71 is subsequently removed. Of these, the portion formed on the interlayer insulating film 16 is removed.
  • the second wiring portion 20a composed of the barrier metal film 72a and the conductive film 19a is formed in the liner insulating film 15 and the interlayer insulating film 16 in the power wiring region A, and the liner insulation in the low resistance wiring region C is formed.
  • a second wiring portion 20c including a barrier metal film 72c and a conductive film 19c is formed on the film 15 and the interlayer insulating film 16.
  • the side surfaces of the second wiring portions 20a and 20c are covered with side wall barrier metal films 71a and 71c.
  • wiring grooves 17a and 17c are formed in the liner insulating film 15 and the interlayer insulating film 16, for example, by one etching. Thereafter, as shown in FIG. 1C, a barrier metal film 18 is formed on the interlayer insulating film 16 and on the bottom and side walls of the wiring grooves 17a and 17c.
  • grooves 70a and 70c for exposing the upper surface of the liner insulating film 15 are formed in the interlayer insulating film 16 by the first etching.
  • a sidewall barrier metal film 71 is formed on the interlayer insulating film 16 and on the bottom and sidewalls of the trenches 70a and 70c.
  • the wiring trenches 17a whose side walls are covered with the side wall barrier metal film 71 are formed on the liner insulating film 15 and the interlayer insulating film 16 by, for example, second etching using a rare gas. 17c is formed.
  • a barrier metal film 72 is formed on the side wall barrier metal film 71 and on the bottom and side walls of the wiring grooves 17a and 17c.
  • the differences in configuration between the first embodiment and this modification are as follows.
  • the semiconductor device according to the present modification is formed between the second wiring portions 20a and 20c and the interlayer insulating film 16 in addition to the same components as those in the first embodiment, and the second wiring portions 20a and 20c Side wall barrier metal films 71a and 71c are further provided to cover the side surfaces.
  • the barrier metal films 72a and 72c in the second wiring portions 20a and 20c are connected to the side wall barrier metal films 71a and 71c.
  • the wiring grooves 17a and 17c are formed in the chamber (not shown) by etching using, for example, a fluorine-containing gas as an etching gas.
  • a fluorine-containing gas as an etching gas.
  • trenches 70a and 70c that expose the upper surface of the liner insulating film 15 are formed by the first etching in the first chamber.
  • wiring grooves 17a and 17c that expose the surfaces of the first wiring portions 14a and 14c are formed in the third chamber by, for example, second etching using a rare gas. To do.
  • the liner insulating film 15 is exposed in the grooves 70a and 70c, not in the first wiring portions 14a and 14c, in the first etching, the conductive films 13a and 13c in the first wiring portions 14a and 14c are exposed.
  • the contained copper is not sputtered. Therefore, even when, for example, a fluorine-containing gas is used as an etching gas, fluorine atoms contained in the fluorine-containing gas are not trapped in the sputtered copper, and therefore, on the inner wall of the first chamber, Copper fluoride does not adhere, and the etching rate can be stabilized.
  • the sidewall barrier metal film 71 is formed in the second chamber by, for example, sputtering, and thereafter,
  • the wiring grooves 17a and 17c that expose the surfaces of the first wiring portions 14a and 14c are formed in the third chamber by, for example, plasma etching using a rare gas, as shown in FIG.
  • the wiring grooves 17a and 17c are formed by plasma etching using a rare gas in a third chamber different from the second chamber in which the sidewall barrier metal film 71 is formed by sputtering.
  • the present invention is not limited to this.
  • a sidewall barrier metal film is formed in the second chamber by, for example, sputtering, and then not in the third chamber.
  • a wiring groove that exposes the surface of the first wiring portion may be formed by, for example, reverse sputtering.
  • the wiring trench may be formed by reverse sputtering instead of plasma etching using a rare gas.
  • the present invention can prevent the generation of voids in the wiring, it is useful for a semiconductor device provided with the wiring.

Abstract

A semiconductor device comprises a first inter-layer insulating film (10) formed on a semiconductor substrate; a first primary wiring part (14c) formed in the first inter-layer insulating film (10); a second inter-layer insulating film (16) formed above the first inter-layer insulating film (10); and a first secondary wiring part (20c) formed in the second inter-layer insulating film (16) and connected to the first primary wiring part (14c).  The first primary wiring part (14c) and first secondary wiring part (20c) constitute a first wiring (20C).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof.
　近年、半導体集積回路の高集積化の進行に伴い、銅（Ｃｕ）を主成分とする配線が採用されている。 In recent years, with the progress of high integration of semiconductor integrated circuits, wiring mainly composed of copper (Cu) has been adopted.
　ここで、Ｃｕを主成分とする配線の形成方法としては、以下に示す方法が提案されている（例えば特許文献１参照）。図１３は、従来の半導体装置の製造方法を示す断面図である。 Here, the following method has been proposed as a method for forming a wiring mainly composed of Cu (see, for example, Patent Document 1). FIG. 13 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
　スパッタ法等により、絶縁膜３００上、並びに配線溝３０１ａ，３０１ｂ，３０１ｃの底面及び側壁に、バリアメタル膜を形成した後、スパッタ法等により、バリアメタル膜上に、Ｃｕを含むシード膜を形成する。その後、めっき法により、シード膜上に、Ｃｕを含むめっき膜を形成する。このようにして、配線溝３０１内に、バリアメタル膜を介して、Ｃｕを含む導電膜を埋め込む。 A barrier metal film is formed on the insulating film 300 and on the bottom and side walls of the wiring grooves 301a, 301b, and 301c by sputtering or the like, and then a seed film containing Cu is formed on the barrier metal film by sputtering or the like. To do. Thereafter, a plating film containing Cu is formed on the seed film by a plating method. In this manner, the conductive film containing Cu is embedded in the wiring trench 301 via the barrier metal film.
　その後、ＣＭＰ法により、絶縁膜３００の表面が露出されるまで、導電膜、及びバリアメタル膜を研磨除去する。このようにして、図１３に示すように、配線溝３０１ａ，３０１ｂ，３０１ｃの底面及び側壁に形成されたバリアメタル膜３０２ａ，３０２ｂ，３０２ｃと、配線溝３０１ａ，３０１ｂ，３０１ｃ内にバリアメタル膜３０２ａ，３０２ｂ，３０２ｃを介して埋め込まれた導電膜３０４ａ，３０４ｂ，３０４ｃとからなる配線３０５ａ，３０５ｂ，３０５ｃを形成する。 Thereafter, the conductive film and the barrier metal film are polished and removed by CMP until the surface of the insulating film 300 is exposed. In this way, as shown in FIG. 13, barrier metal films 302a, 302b, and 302c formed on the bottom and side walls of the wiring grooves 301a, 301b, and 301c, and the barrier metal film 302a in the wiring grooves 301a, 301b, and 301c. , 302b, and 302c, wirings 305a, 305b, and 305c including conductive films 304a, 304b, and 304c embedded therein are formed.
特開２００６－０２４６９８号公報Japanese Patent Laid-Open No. 2006-024698
　しかしながら、従来の半導体装置では、以下に示す問題がある。この問題について、図１４を参照しながら説明する。図１４は、従来の半導体装置の製造方法における問題について示す断面図である。 However, the conventional semiconductor device has the following problems. This problem will be described with reference to FIG. FIG. 14 is a cross-sectional view showing a problem in a conventional method for manufacturing a semiconductor device.
　ここで、従来では、バリアメタル膜及びシード膜の形成方法として、物理的気相成長法（例えばスパッタ法）を用いる。そのため、バリアメタル膜及びシード膜の各々において、絶縁膜上に形成された部分が、配線溝の底面及び側壁に形成された部分に比べて、厚く形成される傾向にある。特に、シード膜において、絶縁膜上に形成された部分は、配線溝の底面及び側壁に形成された部分に比べて、非常に厚く形成され、図１４に示すように、シード膜３０３には、絶縁膜３００上から配線溝３０１ａ，３０１ｂ，３０１ｃ内に向かって突出するように、オーバーハング部３０３ａｘ，３０３ｂｘ，３０３ｃｘが形成される虞がある。 Here, conventionally, a physical vapor deposition method (for example, a sputtering method) is used as a method for forming the barrier metal film and the seed film. Therefore, in each of the barrier metal film and the seed film, the portion formed on the insulating film tends to be formed thicker than the portions formed on the bottom and side walls of the wiring trench. In particular, in the seed film, the portion formed on the insulating film is formed much thicker than the portions formed on the bottom and side walls of the wiring trench, and as shown in FIG. There is a possibility that the overhang portions 303ax, 303bx, and 303cx are formed so as to protrude from the insulating film 300 into the wiring grooves 301a, 301b, and 301c.
　スパッタ法によるシード膜の形成時に、対向するオーバーハング部同士が互いに接触し、配線溝を閉塞した場合、その後に行うめっき膜の形成時に、配線溝内に、めっき膜を埋め込むことができず、配線にボイドが発生する。特に、オーバーハング部３０３ａｘ，３０３ｂｘ，３０３ｃｘのうち、オーバーハング部３０３ｂｘ同士が互いに接触する可能性が高い、即ち、配線溝３０１ａ，３０１ｂ，３０１ｃのうち、最もアスペクト比の高い配線溝３０１ｂが閉塞される可能性が高い。このように、従来では、オーバーハング部による配線溝の閉塞により、配線にボイドが発生するという問題がある。 When the seed film is formed by sputtering, the opposing overhang portions are in contact with each other and the wiring groove is closed.When the plating film is formed after that, the plating film cannot be embedded in the wiring groove, Voids are generated in the wiring. In particular, of the overhang portions 303ax, 303bx, and 303cx, there is a high possibility that the overhang portions 303bx are in contact with each other. There is a high possibility. As described above, conventionally, there is a problem that a void is generated in the wiring due to the blockage of the wiring groove by the overhang portion.
　そこで、この問題の対策として、オーバーハング部同士の接触により、配線溝が閉塞される前に、スパッタ法によるシード膜の形成を中断する方法が提案されている。 Therefore, as a countermeasure for this problem, a method is proposed in which the formation of the seed film by the sputtering method is interrupted before the wiring trench is closed by contact between the overhang portions.
　しかしながら、上記の方法では、以下に示す問題がある。この問題について、図１５を参照しながら説明する。図１５は、従来技術の半導体装置の製造方法における問題について示す断面図である。 However, the above method has the following problems. This problem will be described with reference to FIG. FIG. 15 is a cross-sectional view showing a problem in a conventional method for manufacturing a semiconductor device.
　半導体集積回路の高集積化がさらに進行した場合、従来技術のように、配線溝が閉塞される前に、スパッタ法によるシード膜の形成を中断すると、特に、アスペクト比の高い配線溝において、図１５に示すように、オーバーハング部４０３ｂｘによる配線溝４０１ｂの閉塞は招かないものの、配線溝４０１ｂ内のバリアメタル膜４０２上にシード膜４０３が形成されずシード膜４０３の形成不良を招く。そのため、シード膜上へのめっき膜の形成時に、シード膜がない配線溝内に、めっき膜を精度良く埋め込むことができず、配線にボイドが発生する。 When the integration of semiconductor integrated circuits further progresses, if the formation of the seed film by the sputtering method is interrupted before the wiring trench is closed as in the prior art, the wiring trench having a high aspect ratio is particularly affected. As shown in FIG. 15, the wiring groove 401 b is not blocked by the overhang portion 403 bx, but the seed film 403 is not formed on the barrier metal film 402 in the wiring groove 401 b, resulting in poor formation of the seed film 403. Therefore, when the plating film is formed on the seed film, the plating film cannot be embedded with high precision in the wiring groove without the seed film, and voids are generated in the wiring.
　以上のように、従来では、オーバーハング部による配線溝の閉塞によって、配線にボイドが発生するという問題がある。一方、従来技術では、オーバーハング部による配線溝の閉塞は招かないものの、シード膜の形成不良によって、配線にボイドが発生するという問題がある。 As described above, conventionally, there is a problem that a void is generated in the wiring due to the blockage of the wiring groove by the overhang portion. On the other hand, in the prior art, although the wiring groove is not blocked by the overhang portion, there is a problem that voids are generated in the wiring due to poor formation of the seed film.
　前記に鑑み、本発明の目的は、シード膜の形成不良を招くことなく、オーバーハング部による配線溝の閉塞を防止し、配線にボイドが発生することを防止することである。 In view of the above, an object of the present invention is to prevent a wiring groove from being blocked by an overhang portion and prevent a void from being generated without causing a seed film formation failure.
　前記の目的を達成するために、本発明の一側面に係る半導体装置は、半導体基板上に形成された第１の層間絶縁膜と、第１の層間絶縁膜に形成された第１の第１配線部と、第１の層間絶縁膜上に形成された第２の層間絶縁膜と、第２の層間絶縁膜に形成され、第１の第１配線部と接続する第１の第２配線部とを備え、第１の第１配線部、及び第１の第２配線部からなる第１の配線が構成されていることを特徴とする。 In order to achieve the above object, a semiconductor device according to an aspect of the present invention includes a first interlayer insulating film formed on a semiconductor substrate and a first first insulating film formed on the first interlayer insulating film. A wiring portion, a second interlayer insulating film formed on the first interlayer insulating film, and a first second wiring portion formed on the second interlayer insulating film and connected to the first first wiring portion And a first wiring composed of a first first wiring part and a first second wiring part is configured.
　本発明の一側面に係る半導体装置によると、第１の配線は、第１の第１配線部、及び第１の第２配線部からなり、複数の段階（例えば２段階）に分けて構成される。これにより、第１の配線のアスペクト比が高い場合であっても、各配線部のアスペクト比を低くすることができる。そのため、各配線部にボイドが発生することを防止することができる。従って、ボイドを発生させることなく、第１の配線を実現することができる。 According to the semiconductor device of one aspect of the present invention, the first wiring includes the first first wiring portion and the first second wiring portion, and is divided into a plurality of stages (for example, two stages). The Thereby, even if the aspect ratio of the first wiring is high, the aspect ratio of each wiring portion can be reduced. Therefore, it is possible to prevent the occurrence of voids in each wiring part. Therefore, the first wiring can be realized without generating voids.
　本発明の一側面に係る半導体装置において、第１の層間絶縁膜に形成された第２の第１配線部からなる第２の配線をさらに備え、第２の第１配線部の高さは、第１の第１配線部の高さと略同一であり、第２の配線の配線高さは、第１の配線の配線高さよりも低いことが好ましい。 In the semiconductor device according to one aspect of the present invention, the semiconductor device further includes a second wiring composed of a second first wiring portion formed in the first interlayer insulating film, and the height of the second first wiring portion is: It is preferable that the height of the second wiring is substantially the same as the height of the first first wiring portion, and the wiring height of the second wiring is lower than that of the first wiring.
　本発明の一側面に係る半導体装置において、第２の配線の配線幅は、第１の配線の配線幅と略同一であり、第２の配線の抵抗は、第１の配線の抵抗よりも高いことが好ましい。 In the semiconductor device according to one aspect of the present invention, the wiring width of the second wiring is substantially the same as the wiring width of the first wiring, and the resistance of the second wiring is higher than the resistance of the first wiring. It is preferable.
　本発明の一側面に係る半導体装置において、第２の層間絶縁膜に形成され、第２の第１配線部と接続する第２のビア部をさらに備え、第２のビア部の高さは、第１の第２配線部の高さと略同一であることが好ましい。 In the semiconductor device according to one aspect of the present invention, the semiconductor device further includes a second via portion formed in the second interlayer insulating film and connected to the second first wiring portion, and the height of the second via portion is: It is preferable that the height is substantially the same as the height of the first second wiring portion.
　本発明の一側面に係る半導体装置において、第１の第１配線部は、第１の層間絶縁膜に設けられた配線溝の底面及び側壁に形成されたバリアメタル膜と、該配線溝内に該バリアメタル膜を介して埋め込まれた導電膜とからなり、第１の第２配線部は、第２の層間絶縁膜に設けられた配線溝の側壁に形成されたバリアメタル膜と、該配線溝内に該バリアメタル膜を介して埋め込まれた導電膜とからなり、第１の第２配線部を構成する導電膜は、第１の第１配線部を構成する導電膜に接して形成されていることが好ましい。 In the semiconductor device according to one aspect of the present invention, the first first wiring portion includes a barrier metal film formed on a bottom surface and a side wall of the wiring groove provided in the first interlayer insulating film, and in the wiring groove. The first second wiring portion includes a barrier metal film formed on a side wall of a wiring trench provided in the second interlayer insulating film, and the wiring. The conductive film is embedded through the barrier metal film. The conductive film is formed in contact with the conductive film forming the first first wiring portion, and is formed of a conductive film buried in the trench through the barrier metal film. It is preferable.
　本発明の一側面に係る半導体装置において、第１の第２配線部の断面形状は、その下面幅がその上面幅よりも小さい形状であることが好ましい。 In the semiconductor device according to one aspect of the present invention, it is preferable that the cross-sectional shape of the first second wiring portion is a shape in which the bottom surface width is smaller than the top surface width.
　本発明の一側面に係る半導体装置において、第２の層間絶縁膜上に形成された第３の層間絶縁膜と、第３の層間絶縁膜に形成され、第１の第２配線部と接続するビアと、第３の層間絶縁膜に形成され、ビアと接続する第３の第１配線部と、第３の層間絶縁膜上に形成された第４の層間絶縁膜と、第４の層間絶縁膜に形成され、第３の第１配線部と接続する第３の第２配線部とをさらに備え、第３の第１配線部、及び第３の第２配線部からなる第３の配線が構成されていることが好ましい。 In the semiconductor device according to one aspect of the present invention, the third interlayer insulating film formed on the second interlayer insulating film and the third interlayer insulating film are connected to the first second wiring portion. A via, a third first wiring portion formed in the third interlayer insulating film and connected to the via, a fourth interlayer insulating film formed on the third interlayer insulating film, and a fourth interlayer insulation A third wiring formed on the film and connected to the third first wiring portion; and a third wiring comprising the third first wiring portion and the third second wiring portion. It is preferable to be configured.
　本発明の一側面に係る半導体装置において、第１の層間絶縁膜、及び第２の層間絶縁膜は、ＳｉＯＣ膜であることが好ましい。 In the semiconductor device according to one aspect of the present invention, the first interlayer insulating film and the second interlayer insulating film are preferably SiOC films.
　本発明の一側面に係る半導体装置において、第１の配線のアスペクト比は、０．５以上１．０以下であることが好ましい。 In the semiconductor device according to one aspect of the present invention, the aspect ratio of the first wiring is preferably 0.5 or more and 1.0 or less.
　本発明の一側面に係る半導体装置において、第１の配線の配線幅は、７０ｎｍ以下であることが好ましい。 In the semiconductor device according to one aspect of the present invention, the wiring width of the first wiring is preferably 70 nm or less.
　本発明の一側面に係る半導体装置において、第１の第１配線部と第１の第２配線部との間に形成され、第１の第１配線部の表面を覆うキャップ膜をさらに備え、キャップ膜は、金属を含み、第１の第１配線部は、キャップ膜を介して、第１の第２配線部と電気的に接続していることが好ましい。 The semiconductor device according to one aspect of the present invention further includes a cap film that is formed between the first first wiring portion and the first second wiring portion and covers the surface of the first first wiring portion. The cap film preferably includes a metal, and the first first wiring part is electrically connected to the first second wiring part via the cap film.
　本発明の一側面に係る半導体装置において、金属は、Ｔｉ、Ｗ、Ｍｏ、Ｈｆ又はＺｒであることが好ましい。 In the semiconductor device according to one aspect of the present invention, the metal is preferably Ti, W, Mo, Hf, or Zr.
　前記の目的を達成するために、本発明の一側面に係る半導体装置の製造方法は、半導体基板上に、第１の層間絶縁膜を形成する工程（ａ）と、第１の層間絶縁膜に、第１の第１配線部を形成する工程（ｂ）と、工程（ｂ）の後に、第１の層間絶縁膜上に、第２の層間絶縁膜を形成する工程（ｃ）と、第２の層間絶縁膜に、第１の第１配線部と接続する第１の第２配線部を形成する工程（ｄ）とを備え、工程（ｄ）において、第１の第１配線部、及び第１の第２配線部からなる第１の配線が構成されることを特徴とする。 In order to achieve the above object, a method of manufacturing a semiconductor device according to one aspect of the present invention includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate, and a first interlayer insulating film. A step (b) of forming the first first wiring portion, a step (c) of forming a second interlayer insulating film on the first interlayer insulating film after the step (b), and a second Forming a first second wiring portion connected to the first first wiring portion in the interlayer insulating film, wherein in the step (d), the first first wiring portion, A first wiring composed of one second wiring portion is configured.
　本発明の一側面に係る半導体装置の製造方法によると、第１の配線は、第１の第１配線部、及び第１の第２配線部からなり、複数の段階（例えば２段階）に分けて構成される。これにより、第１の配線のアスペクト比が高い場合であっても、各配線部のアスペクト比を低くすることができる。そのため、各配線部において、シード膜の形成不良を招くことなく、オーバーハング部による各配線溝の閉塞を防止することができるため、各配線部にボイドが発生することを防止することができる。従って、ボイドを発生させることなく、第１の配線を実現することができる。 According to the method of manufacturing a semiconductor device according to one aspect of the present invention, the first wiring includes the first first wiring portion and the first second wiring portion, and is divided into a plurality of stages (for example, two stages). Configured. Thereby, even if the aspect ratio of the first wiring is high, the aspect ratio of each wiring portion can be reduced. For this reason, in each wiring part, it is possible to prevent the formation of the seed film, and the wiring groove can be prevented from being blocked by the overhang part. Therefore, it is possible to prevent the occurrence of voids in each wiring part. Therefore, the first wiring can be realized without generating voids.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｂ）は、第１の層間絶縁膜に、第２の第１配線部を形成する工程をさらに含み、工程（ｂ）において、第２の第１配線部からなる第２の配線が構成されることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, the step (b) further includes a step of forming a second first wiring portion in the first interlayer insulating film. Preferably, the second wiring composed of the two first wiring portions is configured.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｄ）は、第２の層間絶縁膜に、第２の第１配線部と接続する第２のビア部を形成する工程をさらに含むことが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, the step (d) further includes a step of forming a second via portion connected to the second first wiring portion in the second interlayer insulating film. It is preferable.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｂ）は、第１の層間絶縁膜に第１配線溝を形成する工程（ｂ１）と、第１配線溝の底面及び側壁に第１バリアメタル膜を形成する工程（ｂ２）と、工程（ｂ２）の後に、第１配線溝内に第１導電膜を埋め込んで、第１配線溝内に、第１バリアメタル膜を介して第１導電膜が埋め込まれてなる第１の第１配線部を形成する工程（ｂ３）とを含み、工程（ｄ）は、第２の層間絶縁膜に第２配線溝を形成する工程（ｄ１）と、第２配線溝の側壁に第２バリアメタル膜を形成する工程（ｄ２）と、工程（ｄ２）の後に、第２配線溝内に第２導電膜を埋め込んで、第２配線溝内に、第２バリアメタル膜を介して第２導電膜が埋め込まれてなる第１の第２配線部を形成する工程（ｄ３）とを含み、工程（ｄ３）において、第２導電膜は、第１導電膜に接して形成されることが好ましい。 In the method of manufacturing a semiconductor device according to one aspect of the present invention, the step (b) includes a step (b1) of forming a first wiring groove in the first interlayer insulating film, and a step formed on the bottom surface and the side wall of the first wiring groove. After the steps (b2) and (b2) of forming the first barrier metal film, the first conductive film is embedded in the first wiring groove, and the first barrier metal film is interposed through the first barrier metal film. And a step (d3) of forming a second wiring trench in the second interlayer insulating film. The step (d3) includes a step (b3) of forming a first first wiring portion in which one conductive film is embedded. Then, after the step (d2) of forming the second barrier metal film on the side wall of the second wiring trench, and after the step (d2), the second conductive film is embedded in the second wiring trench, And (d3) forming a first second wiring portion in which the second conductive film is embedded via the second barrier metal film. Seen, in the step (d3), the second conductive film is preferably formed in contact with the first conductive film.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｂ）の後で、且つ工程（ｃ）の前に、第１の第１配線部の表面に、金属を含むキャップ膜を形成する工程（ｅ）をさらに備え、工程（ｄ１）は、エッチングガスとしてフッ素を含有するフッ素含有ガスを用いたエッチングにより、キャップ膜の表面を露出させる第２配線溝を形成する工程であることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, a cap film containing a metal is formed on the surface of the first first wiring portion after the step (b) and before the step (c). It is preferable that the method further includes a step (e), and the step (d1) is a step of forming a second wiring groove that exposes the surface of the cap film by etching using a fluorine-containing gas containing fluorine as an etching gas. .
　このようにすると、第２配線溝内に、第１の第１配線部ではなく、キャップ膜が露出するため、第１の第１配線部における第１導電膜に含まれる金属（例えば銅）がスパッタされることはない。そのため、エッチングガスとして、例えばフッ素含有ガスを用いた場合であっても、スパッタされた銅に、フッ素含有ガスに含有されるフッ素原子がトラップされることはないため、チャンバーの内壁に、銅のフッ化物が付着することはなく、エッチングレートを安定化させることができる。 In this case, since the cap film is exposed in the second wiring groove instead of the first first wiring part, the metal (for example, copper) contained in the first conductive film in the first first wiring part is exposed. It is not sputtered. Therefore, even when, for example, a fluorine-containing gas is used as the etching gas, the fluorine atoms contained in the fluorine-containing gas are not trapped in the sputtered copper. Fluoride does not adhere and the etching rate can be stabilized.
　さらに、第２配線溝内に露出するキャップ膜に含まれる金属がスパッタされて、スパッタされた金属に、フッ素含有ガスに含有されるフッ素原子がトラップされて、金属のフッ化物が生成されることがあっても、金属のフッ化物の蒸気圧は、銅のフッ化物の蒸気圧よりも高いため、金属のフッ化物を、チャンバーの内壁に付着させずに、チャンバー外に排気することができるので、エッチングレートを安定化させることができる。 Further, the metal contained in the cap film exposed in the second wiring trench is sputtered, and fluorine atoms contained in the fluorine-containing gas are trapped in the sputtered metal, thereby generating a metal fluoride. Even so, the metal fluoride vapor pressure is higher than the copper fluoride vapor pressure, so the metal fluoride can be exhausted outside the chamber without adhering to the inner wall of the chamber. The etching rate can be stabilized.
　本発明の一側面に係る半導体装置の製造方法において、金属は、Ｔｉ、Ｗ、Ｍｏ、Ｈｆ又はＺｒであることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, the metal is preferably Ti, W, Mo, Hf, or Zr.
　このようにすると、Ｔｉ、Ｗ、Ｍｏ、Ｈｆ又はＺｒのフッ化物の蒸気圧は、Ｃｕのフッ化物の蒸気圧よりも高い。 In this way, the vapor pressure of the fluoride of Ti, W, Mo, Hf or Zr is higher than the vapor pressure of the fluoride of Cu.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｄ１）は、エッチングガスとしてフッ素を含有するフッ素含有ガスを用いた第１のエッチングにより、第２の層間絶縁膜に、溝を形成する工程と、エッチングガスとして希ガスを用いた第２のエッチングにより、溝内に露出する第２の層間絶縁膜を除去し、第２の層間絶縁膜に、第１の第１配線部の表面を露出させる第２配線溝を形成する工程とを含み、溝を形成する工程において、溝内に、第１の第１配線部の表面が露出されることがないように、溝は形成されることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, in step (d1), a groove is formed in the second interlayer insulating film by first etching using a fluorine-containing gas containing fluorine as an etching gas. And the second etching using a rare gas as an etching gas to remove the second interlayer insulating film exposed in the trench, and the surface of the first first wiring portion is formed on the second interlayer insulating film. Forming a second wiring groove that exposes the groove, and in the step of forming the groove, the groove is formed so that the surface of the first first wiring portion is not exposed in the groove. It is preferable.
　このようにすると、第２のエッチング時に、第２配線溝内に露出する第１の第１配線部における第１導電膜に含まれる金属（例えば銅）がスパッタされることがあっても、一般に、希ガスは、銅と反応することがないため、スパッタされた銅に、希ガスがトラップされることはないので、エッチングレートを安定化させることができる。 In this case, even when the metal (for example, copper) included in the first conductive film in the first first wiring portion exposed in the second wiring trench may be sputtered during the second etching, Since the rare gas does not react with copper, the rare gas is not trapped by the sputtered copper, so that the etching rate can be stabilized.
　さらに、第１のエッチング時に、溝内に、第１の第１配線部を露出させないため、第１の第１配線部における第１導電膜に含まれる金属（例えば銅）がスパッタされることはない。そのため、エッチングガスとして、例えばフッ素含有ガスを用いた場合であっても、スパッタされた銅に、フッ素含有ガスに含まれるフッ素原子がトラップされることはないため、第１のエッチングが行われるチャンバーの内壁に、銅のフッ化物が付着することはなく、エッチングレートを安定化させることができる。 Furthermore, during the first etching, the metal (for example, copper) contained in the first conductive film in the first first wiring part is sputtered so that the first first wiring part is not exposed in the groove. Absent. Therefore, even when, for example, a fluorine-containing gas is used as an etching gas, the fluorine atoms contained in the fluorine-containing gas are not trapped in the sputtered copper, so that the chamber in which the first etching is performed is performed. In this case, copper fluoride does not adhere to the inner wall, and the etching rate can be stabilized.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｄ２）は、第２配線溝の底面及び側壁に第２バリアメタル膜を形成した後、第２バリアメタル膜のうち第２配線溝の底面に形成された部分を除去する工程であることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, in the step (d2), after forming the second barrier metal film on the bottom surface and the side wall of the second wiring groove, the second wiring groove in the second barrier metal film is formed. It is preferable that it is the process of removing the part formed in the bottom face.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｄ）の後に、第２の層間絶縁膜上に第３の層間絶縁膜を形成する工程（ｆ）と、第３の層間絶縁膜に、第１の第２配線部と接続するビア、及び該ビアと接続する第３の第１配線部を形成する工程（ｇ）と、工程（ｇ）の後に、第３の層間絶縁膜上に、第４の層間絶縁膜を形成する工程（ｈ）と、第４の層間絶縁膜に、第３の第１配線部と接続する第３の第２配線部を形成する工程（ｉ）とをさらに備え、工程（ｉ）において、第３の第１配線部、及び第３の第２配線部からなる第３の配線が構成されることが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, a step (f) of forming a third interlayer insulating film on the second interlayer insulating film after the step (d), and a third interlayer insulating film A step (g) of forming a via connected to the first second wiring portion and a third first wiring portion connected to the via; and after the step (g), on the third interlayer insulating film A step (h) of forming a fourth interlayer insulating film, a step (i) of forming a third second wiring portion connected to the third first wiring portion in the fourth interlayer insulating film, and In the step (i), it is preferable that a third wiring composed of a third first wiring portion and a third second wiring portion is configured.
　本発明の一側面に係る半導体装置の製造方法において、工程（ｇ）は、第３の層間絶縁膜に、ビア孔及び配線溝を形成する工程（ｇ１）と、ビア孔にビアを形成すると共に、配線溝に第３の第１配線部を形成する工程（ｇ２）とを含むことが好ましい。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, the step (g) includes a step (g1) of forming a via hole and a wiring groove in the third interlayer insulating film, and forming a via in the via hole. And a step (g2) of forming a third first wiring portion in the wiring groove.
　本発明の一側面に係る半導体装置及びその製造方法によると、第１の配線は、第１の第１配線部、及び第１の第２配線部からなり、複数の段階（例えば２段階）に分けて構成される。これにより、第１の配線のアスペクト比が高い場合であっても、各配線部のアスペクト比を低くすることができる。そのため、各配線部において、シード膜の形成不良を招くことなく、オーバーハング部による各配線溝の閉塞を防止することができるため、各配線部にボイドが発生することを防止することができる。従って、ボイドを発生させることなく、第１の配線を実現することができる。 According to the semiconductor device and the manufacturing method thereof according to one aspect of the present invention, the first wiring includes the first first wiring portion and the first second wiring portion, and includes a plurality of stages (for example, two stages). It is configured separately. Thereby, even if the aspect ratio of the first wiring is high, the aspect ratio of each wiring portion can be reduced. For this reason, in each wiring part, it is possible to prevent the formation of the seed film, and the wiring groove can be prevented from being blocked by the overhang part. Therefore, it is possible to prevent the occurrence of voids in each wiring part. Therefore, the first wiring can be realized without generating voids.
図１(a) ～(c) は、本発明の第１の実施形態に係る半導体装置の製造方法を工程順に示す要部工程断面図である。FIGS. 1A to 1C are cross-sectional views of relevant steps showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. 図２(a) ～(c) は、本発明の第１の実施形態に係る半導体装置の製造方法を工程順に示す要部工程断面図である。2 (a) to 2 (c) are cross-sectional views of essential parts showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. 図３(a) ～(c) は、本発明の第１の実施形態に係る半導体装置の製造方法を工程順に示す要部工程断面図である。FIGS. 3A to 3C are cross-sectional views of relevant steps showing the semiconductor device manufacturing method according to the first embodiment of the present invention in the order of steps. 図４(a) 及び(b) は、本発明の第１の実施形態に係る半導体装置の構成を示す図であり、図４(c) 及び(d) は、比較例に係る半導体装置の構成を示す図である。FIGS. 4A and 4B are diagrams showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIGS. 4C and 4D are the configuration of the semiconductor device according to the comparative example. FIG. 図５は、本発明の第１の実施形態に係る半導体装置の構成を示す断面図である。FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. 図６は、本発明の第２の実施形態に係る半導体装置の構成を示す平面図である。FIG. 6 is a plan view showing a configuration of a semiconductor device according to the second embodiment of the present invention. 図７は、本発明の第２の実施形態に係る半導体装置の構成を示す断面図である。FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention. 図８は、本発明の第２の実施形態に係る半導体装置の構成を示す断面図である。FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention. 図９は、本発明の第２の実施形態に係る半導体装置の構成を示す断面図である。FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention. 図１０は、本発明の第２の実施形態に係る半導体装置の構成を示す断面図である。FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention. 図１１(a) は、本発明を適用してグローバル配線を形成する場合の断面図であり、図１１(b) は、本発明を適用せずにグローバル配線を形成する場合の断面図である。FIG. 11A is a cross-sectional view when a global wiring is formed by applying the present invention, and FIG. 11B is a cross-sectional view when a global wiring is formed without applying the present invention. . 図１２(a) ～(d) は、本発明の第１の実施形態の変形例３に係る半導体装置の製造方法を工程順に示す要部工程断面図である。12 (a) to 12 (d) are cross-sectional views of relevant steps showing a method of manufacturing a semiconductor device according to Modification 3 of the first embodiment of the present invention in the order of steps. 図１３は、従来の半導体装置の製造方法を示す断面図である。FIG. 13 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device. 図１４は、従来の半導体装置の製造方法における問題について示す断面図である。FIG. 14 is a cross-sectional view showing a problem in a conventional method for manufacturing a semiconductor device. 図１５は、従来技術の半導体装置の製造方法における問題について示す断面図である。FIG. 15 is a cross-sectional view showing a problem in a conventional method for manufacturing a semiconductor device.
　以下に、本発明の各実施形態について図面を参照しながら説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　（第１の実施形態）
　以下に、本発明の第１の実施形態に係る半導体装置の製造方法について、図１(a) ～図１(c)、図２(a) ～図２(c)、及び図３(a) ～図３(c) を参照しながら説明する。図１(a) ～図３(c) は、本発明の第１の実施形態に係る半導体装置の製造方法を工程順に示す要部工程断面図である。ここで、図１(a) ～図３(c) において、左側の領域を電源配線が形成される電源配線領域Ａとし、中央の領域を信号配線が形成される信号配線領域Ｂとし、右側の領域を低抵抗配線が形成される低抵抗配線領域Ｃとする。なお、「電源配線」とはＬＳＩを動作させる電源から電力（電流）が供給されるため大電流が流れる配線であり、「信号配線」とは信号回路に使用され、微小電流が流れる配線であり、「低抵抗配線」とは論理回路に使用され、速い信号伝播速度を必要とする配線である。 (First embodiment)
In the following, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (c), 2 (a) to 2 (c), and FIG. 3 (a). Description will be made with reference to FIG. FIG. 1A to FIG. 3C are cross-sectional views of relevant parts showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. Here, in FIGS. 1 (a) to 3 (c), the left region is a power wiring region A in which power wiring is formed, the central region is a signal wiring region B in which signal wiring is formed, and the right region is The region is a low resistance wiring region C where a low resistance wiring is formed. "Power wiring" is a wiring through which a large current flows because power (current) is supplied from the power source that operates the LSI. "Signal wiring" is a wiring that is used for a signal circuit and through which a minute current flows. The “low resistance wiring” is a wiring that is used in a logic circuit and requires a high signal propagation speed.
　なお、本実施形態に記載の材料及び数値は、好ましい材料及び数値を記載したに過ぎず、これらに限定されることはない。また、本発明の効果を奏する範囲において、種々の変形及び応用が可能である。 Note that the materials and numerical values described in the present embodiment are merely preferable materials and numerical values, and are not limited thereto. In addition, various modifications and applications are possible within the scope of the effects of the present invention.
　まず、図１(a) に示すように、半導体基板（図示せず）上に層間絶縁膜１０を形成する。その後、公知の技術により、層間絶縁膜１０に、配線溝１１ａ，１１ｂ，１１ｃを形成する。その後、公知の技術により、配線溝１１ａ，１１ｂ，１１ｃの底面及び側壁に、バリアメタル膜１２ａ，１２ｂ，１２ｃを形成した後、公知の技術により、配線溝１１ａ，１１ｂ，１１ｃ内に、例えば銅（Ｃｕ）等からなる導電膜１３ａ，１３ｂ，１３ｃを埋め込む。 First, as shown in FIG. 1A, an interlayer insulating film 10 is formed on a semiconductor substrate (not shown). Thereafter, wiring grooves 11a, 11b, and 11c are formed in the interlayer insulating film 10 by a known technique. Thereafter, barrier metal films 12a, 12b, and 12c are formed on the bottom and side walls of the wiring grooves 11a, 11b, and 11c by a known technique, and then, for example, copper is formed in the wiring grooves 11a, 11b, and 11c by a known technique. The conductive films 13a, 13b and 13c made of (Cu) or the like are embedded.
　このようにして、電源配線領域Ａの層間絶縁膜１０に、バリアメタル膜１２ａと、導電膜１３ａとからなる第１配線部１４ａを形成し、信号配線領域Ｂの層間絶縁膜１０に、バリアメタル膜１２ｂと、導電膜１３ｂとからなる第１配線部１４ｂを形成し、低抵抗配線領域Ｃの層間絶縁膜１０に、バリアメタル膜１２ｃと、導電膜１３ｃとからなる第１配線部１４ｃを形成する。 In this way, the first wiring portion 14a composed of the barrier metal film 12a and the conductive film 13a is formed in the interlayer insulating film 10 in the power supply wiring region A, and the barrier metal is formed in the interlayer insulating film 10 in the signal wiring region B. A first wiring portion 14b composed of the film 12b and the conductive film 13b is formed, and a first wiring portion 14c composed of the barrier metal film 12c and the conductive film 13c is formed in the interlayer insulating film 10 in the low resistance wiring region C. To do.
　次に、層間絶縁膜１０、及び第１配線部１４ａ，１４ｂ，１４ｃの上に、ライナー絶縁膜１５を形成する。その後、ライナー絶縁膜１５上に、層間絶縁膜１６を形成する。 Next, the liner insulating film 15 is formed on the interlayer insulating film 10 and the first wiring portions 14a, 14b, and 14c. Thereafter, an interlayer insulating film 16 is formed on the liner insulating film 15.
　次に、図１(b) に示すように、リソグラフィー技術、及びエッチング技術により、電源配線領域Ａのライナー絶縁膜１５及び層間絶縁膜１６に、配線溝１７ａを形成すると共に、低抵抗配線領域Ｃのライナー絶縁膜１５及び層間絶縁膜１６に、配線溝１７ｃを形成する。このとき、配線溝１７ａ，１７ｃは、その断面形状が、下面から上面に向かって幅が大きくなるテーパー形状となるように形成される。 Next, as shown in FIG. 1B, a wiring groove 17a is formed in the liner insulating film 15 and the interlayer insulating film 16 in the power supply wiring region A by a lithography technique and an etching technique, and the low resistance wiring region C is formed. A wiring groove 17 c is formed in the liner insulating film 15 and the interlayer insulating film 16. At this time, the wiring grooves 17a and 17c are formed so that the cross-sectional shape thereof becomes a tapered shape whose width increases from the lower surface toward the upper surface.
　次に、図１(c) に示すように、スパッタ法により、層間絶縁膜１６上、並びに配線溝１７ａ，１７ｃの底面及び側壁に、バリアメタル膜１８を形成する。その後、逆スパッタ法により、バリアメタル膜１８のうち配線溝１７ａ，１７ｃの底面に形成された部分を除去し、第１配線部１４ａ，１４ｃの上面を露出させる。その後、スパッタ法により、配線溝１７ａ，１７ｃ内に露出する第１配線部１４ａ，１４ｃ、及びバリアメタル膜１８上に、例えば銅（Ｃｕ）等からなるシード膜を形成する。その後、めっき法により、シード膜上に、例えば銅（Ｃｕ）等からなるめっき膜を形成する。このようにして、配線溝１７ａ，１７ｃ内に、バリアメタル膜１８を介して、導電膜１９を埋め込む。ここで、図１(c) において、導電膜１９のうち、シード膜とめっき膜との境界線は、図示が困難なため図示を省略する。 Next, as shown in FIG. 1C, a barrier metal film 18 is formed on the interlayer insulating film 16 and on the bottom and side walls of the wiring grooves 17a and 17c by sputtering. Thereafter, the portion of the barrier metal film 18 formed on the bottom surfaces of the wiring grooves 17a and 17c is removed by reverse sputtering to expose the upper surfaces of the first wiring portions 14a and 14c. Thereafter, a seed film made of, for example, copper (Cu) is formed on the first wiring portions 14a and 14c and the barrier metal film 18 exposed in the wiring grooves 17a and 17c by sputtering. Thereafter, a plating film made of, for example, copper (Cu) or the like is formed on the seed film by plating. In this way, the conductive film 19 is embedded in the wiring grooves 17a and 17c via the barrier metal film 18. Here, in FIG. 1C, the boundary line between the seed film and the plating film in the conductive film 19 is not illustrated because it is difficult to illustrate.
　次に、図２(a) に示すように、ＣＭＰ法により、導電膜１９及びバリアメタル膜１８のうち、配線溝１７ａ，１７ｃ外に形成された部分を除去する。 Next, as shown in FIG. 2A, the portions of the conductive film 19 and the barrier metal film 18 formed outside the wiring grooves 17a and 17c are removed by CMP.
　このようにして、電源配線領域Ａのライナー絶縁膜１５及び層間絶縁膜１６に、バリアメタル膜１８ａと、導電膜１９ａとからなる第２配線部２０ａを形成し、低抵抗配線領域Ｃのライナー絶縁膜１５及び層間絶縁膜１６に、バリアメタル膜１８ｃと、導電膜１９ｃとからなる第２配線部２０ｃを形成する。 In this way, the second wiring portion 20a composed of the barrier metal film 18a and the conductive film 19a is formed in the liner insulating film 15 and the interlayer insulating film 16 in the power supply wiring region A, and the liner insulation in the low resistance wiring region C is formed. A second wiring portion 20 c composed of a barrier metal film 18 c and a conductive film 19 c is formed on the film 15 and the interlayer insulating film 16.
　次に、図２(b) に示すように、層間絶縁膜１６及び第２配線部２０ａ，２０ｃの上に、ライナー絶縁膜２１を形成する。その後、ライナー絶縁膜２１上に、層間絶縁膜２２を形成する。 Next, as shown in FIG. 2B, a liner insulating film 21 is formed on the interlayer insulating film 16 and the second wiring portions 20a and 20c. Thereafter, an interlayer insulating film 22 is formed on the liner insulating film 21.
　次に、図２(c) に示すように、リソグラフィー技術、及びエッチング技術により、電源配線領域Ａのライナー絶縁膜２１及び層間絶縁膜２２に、配線溝２３ａを形成する。このとき、配線溝２３ａは、その断面形状が、下面から上面に向かって幅が大きくなるテーパー形状となるように形成される。 Next, as shown in FIG. 2C, a wiring groove 23a is formed in the liner insulating film 21 and the interlayer insulating film 22 in the power supply wiring region A by lithography and etching techniques. At this time, the wiring groove 23a is formed so that the cross-sectional shape thereof becomes a tapered shape whose width increases from the lower surface toward the upper surface.
　次に、図３(a) に示すように、スパッタ法により、層間絶縁膜２２上、並びに配線溝２３ａの底面及び側壁に、バリアメタル膜２４を形成する。その後、逆スパッタ法により、バリアメタル膜２４のうち、配線溝２３ａの底面に形成された部分を除去し、第２配線部２０ａの上面を露出させる。その後、スパッタ法により、配線溝２３ａ内に露出する第２配線部２０ａ、及びバリアメタル膜２４上に、例えば銅（Ｃｕ）等からなるシード膜を形成する。その後、めっき法により、シード膜上に、例えば銅（Ｃｕ）等からなるめっき膜を形成する。このようにして、配線溝２３ａ内に、バリアメタル膜２４を介して、導電膜２５を埋め込む。ここで、図３(a) において、導電膜２５のうち、シード膜とめっき膜との境界線は、図示が困難なため図示を省略する。 Next, as shown in FIG. 3A, a barrier metal film 24 is formed on the interlayer insulating film 22 and on the bottom and side walls of the wiring groove 23a by sputtering. Thereafter, a portion of the barrier metal film 24 formed on the bottom surface of the wiring groove 23a is removed by reverse sputtering to expose the upper surface of the second wiring portion 20a. Thereafter, a seed film made of, for example, copper (Cu) or the like is formed on the second wiring portion 20a exposed in the wiring groove 23a and the barrier metal film 24 by sputtering. Thereafter, a plating film made of, for example, copper (Cu) or the like is formed on the seed film by plating. In this way, the conductive film 25 is embedded in the wiring groove 23 a via the barrier metal film 24. Here, in FIG. 3A, the boundary line between the seed film and the plating film in the conductive film 25 is not illustrated because it is difficult to illustrate.
　次に、図３(b) に示すように、ＣＭＰ法により、導電膜２５及びバリアメタル膜２４のうち、配線溝２３ａ外に形成された部分を除去する。 Next, as shown in FIG. 3B, a portion of the conductive film 25 and the barrier metal film 24 formed outside the wiring trench 23a is removed by a CMP method.
　このようにして、電源配線領域Ａのライナー絶縁膜２１及び層間絶縁膜２２に、バリアメタル膜２４ａと、導電膜２５ａとからなる第３配線部２６ａを形成する。 In this way, the third wiring portion 26a composed of the barrier metal film 24a and the conductive film 25a is formed in the liner insulating film 21 and the interlayer insulating film 22 in the power supply wiring region A.
　次に、図３(c) に示すように、層間絶縁膜２２及び第３配線部２６ａの上に、ライナー絶縁膜２７を形成する。 Next, as shown in FIG. 3C, a liner insulating film 27 is formed on the interlayer insulating film 22 and the third wiring portion 26a.
　以上のようにして、本実施形態に係る半導体装置を製造することができる。 As described above, the semiconductor device according to this embodiment can be manufactured.
　本実施形態では、図３(c) に示すように、電源配線領域Ａにおいて、第２配線部２０ａの導電膜１９ａは、第１配線部１４ａの導電膜１３ａに接して形成され、第３配線部２６ａの導電膜２５ａは、第２配線部２０ａの導電膜１９ａに接して形成されている。そのため、第１配線部１４ａ、第２配線部２０ａ、及び第３配線部２６ａを合わせて、一つの配線と見なすことができ、電源配線領域Ａには、第１配線部１４ａ、第２配線部２０ａ、及び第３配線部２６ａからなる配線２６Ａが構成されている。 In this embodiment, as shown in FIG. 3C, in the power supply wiring region A, the conductive film 19a of the second wiring portion 20a is formed in contact with the conductive film 13a of the first wiring portion 14a, and the third wiring The conductive film 25a of the part 26a is formed in contact with the conductive film 19a of the second wiring part 20a. Therefore, the first wiring part 14a, the second wiring part 20a, and the third wiring part 26a can be regarded as one wiring, and the first wiring part 14a and the second wiring part are included in the power supply wiring region A. A wiring 26A composed of 20a and the third wiring portion 26a is configured.
　信号配線領域Ｂにおいて、第１配線部１４ｂからなる配線１４Ｂが構成されている。 In the signal wiring region B, a wiring 14B including the first wiring part 14b is configured.
　低抵抗配線領域Ｃにおいて、第２配線部２０ｃの導電膜１９ｃは、第１配線部１４ｃの導電膜１３ｃに接して形成されている。そのため、第１配線部１４ｃ、及び第２配線部２０ｃを合わせて、一つの配線と見なすことができ、低抵抗配線領域Ｃには、第１配線部１４ｃ、及び第２配線部２０ｃからなる配線２０Ｃが構成されている。 In the low resistance wiring region C, the conductive film 19c of the second wiring part 20c is formed in contact with the conductive film 13c of the first wiring part 14c. Therefore, the first wiring portion 14c and the second wiring portion 20c can be regarded as one wiring, and the low resistance wiring region C includes a wiring made up of the first wiring portion 14c and the second wiring portion 20c. 20C is configured.
　以下に、本発明の第１の実施形態に係る半導体装置の構成について、図３(c) を参照しながら説明する。 Hereinafter, the configuration of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG.
　本実施形態に係る半導体装置は、図３(c) に示すように、半導体基板（図示せず）上に順次形成された層間絶縁膜１０、ライナー絶縁膜１５、層間絶縁膜１６、ライナー絶縁膜２１、層間絶縁膜２２、及びライナー絶縁膜２７と、層間絶縁膜１０に形成された第１配線部１４ａ，１４ｂ，１４ｃと、ライナー絶縁膜１５及び層間絶縁膜１６に形成され、第１配線部１４ａ，１４ｃと接続する第２配線部２０ａ，２０ｃと、ライナー絶縁膜２１及び層間絶縁膜２２に形成され、第２配線部２０ａと接続する第３配線部２６ａとを備えている。 As shown in FIG. 3C, the semiconductor device according to this embodiment includes an interlayer insulating film 10, a liner insulating film 15, an interlayer insulating film 16, and a liner insulating film sequentially formed on a semiconductor substrate (not shown). 21, the interlayer insulating film 22, the liner insulating film 27, the first wiring portions 14a, 14b, and 14c formed in the interlayer insulating film 10, the liner insulating film 15 and the interlayer insulating film 16, and the first wiring portion. Second wiring portions 20a and 20c connected to 14a and 14c, and a third wiring portion 26a formed on the liner insulating film 21 and the interlayer insulating film 22 and connected to the second wiring portion 20a are provided.
　既述の通り、電源配線領域Ａには、第１配線部１４ａ、第２配線部２０ａ、及び第３配線部２６ａからなる配線２６Ａが構成されている。信号配線領域Ｂには、第１配線部１４ｂからなる配線１４Ｂが構成されている。低抵抗配線領域Ｃには、第１配線部１４ｃ、及び第２配線部２０ｃからなる配線２０Ｃが構成されている。 As described above, the power supply wiring area A includes the wiring 26A including the first wiring portion 14a, the second wiring portion 20a, and the third wiring portion 26a. In the signal wiring region B, a wiring 14B including the first wiring portion 14b is configured. In the low resistance wiring region C, a wiring 20C including the first wiring part 14c and the second wiring part 20c is configured.
　ここで、本実施形態に係る半導体装置を構成する各構成要素の材料等について、以下に説明する。 Here, materials and the like of each component constituting the semiconductor device according to this embodiment will be described below.
　バリアメタル膜１２ａ，１２ｂ，１２ｃ、１８ａ，１８ｃ、及び２４ａの材料としては、例えば、タンタル（Ｔａ）、窒化タンタル（ＴａＮ）、ルテニウム（Ｒｕ）、又は窒化ルテニウム（ＲｕＮ）を用いることが好ましい。 For example, tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), or ruthenium nitride (RuN) is preferably used as the material of the barrier metal films 12a, 12b, 12c, 18a, 18c, and 24a.
　また、層間絶縁膜１０，１６，２２は、誘電率の低い膜であることが好ましい。例えば、比誘電率が２．２以上４．５以下の膜であることが好ましい。これらの膜の具体例としては、炭素（Ｃ）を含有するＳｉＯＣ膜、及び多孔質ＳｉＯＣ膜等が挙げられる。このような誘電率の低い膜を用いることで、配線間容量を低減することができる。 The interlayer insulating films 10, 16, and 22 are preferably films having a low dielectric constant. For example, a film having a relative dielectric constant of 2.2 to 4.5 is preferable. Specific examples of these films include carbon (C) -containing SiOC films and porous SiOC films. By using such a film having a low dielectric constant, the capacitance between wirings can be reduced.
　また、ライナー絶縁膜１５，２１，２７は、層間絶縁膜１０，１６，２２よりも、誘電率の高い膜であることが好ましい。例えば、比誘電率が４．５以上７．０以下の膜であることが好ましい。これらの膜の具体例としては、ＳｉＣ膜、ＳｉＣＮ膜、及びＳｉＣＯ膜等が挙げられる。このような誘電率の高い膜を用いることで、配線中のＣｕが層間絶縁膜中に熱拡散することを抑制することができる。 Also, the liner insulating films 15, 21, and 27 are preferably films having a higher dielectric constant than the interlayer insulating films 10, 16, and 22. For example, a film having a relative dielectric constant of 4.5 or more and 7.0 or less is preferable. Specific examples of these films include SiC films, SiCN films, and SiCO films. By using such a film having a high dielectric constant, it is possible to suppress thermal diffusion of Cu in the wiring into the interlayer insulating film.
　ここで、電流は、配線の断面に対して垂直な方向に流れるため、断面積の比較的大きい配線（以下、「配線Ａ」という）は、断面積の比較的小さい配線（以下、「配線Ｂ」という）に比べて、抵抗が低い。 Here, since the current flows in a direction perpendicular to the cross section of the wiring, a wiring having a relatively large cross sectional area (hereinafter referred to as “wiring A”) is a wiring having a relatively small cross sectional area (hereinafter referred to as “wiring B”). ”), The resistance is low.
　図３(c) から判るように、低抵抗配線領域Ｃの配線２０Ｃは、信号配線領域Ｂの配線１４Ｂに比べて、断面積が大きく、電源配線領域Ａの配線２６Ａは、低抵抗配線領域Ｃの配線２０Ｃに比べて、断面積が大きい。従って、配線２６Ａ，１４Ｂ，２０Ｃの抵抗は、以下に示す関係を満たす。
配線１４Ｂ ＞ 配線２０Ｃ ＞ 配線２６Ａ
　このように、電源配線領域Ａの配線２６Ａを３段階に分けて構成し、配線２６Ａの断面積を大きくする（配線２６Ａの抵抗を低くする）ことにより、配線２６Ａに電源電流（大電流）を流すことができる。また、低抵抗配線領域Ｃの配線２０Ｃを２段階に分けて構成し、配線２０Ｃの断面積を大きくする（配線２０Ｃの抵抗を低くする）ことにより、配線２０Ｃを低抵抗配線として利用することができる。一方、信号配線領域Ｂの配線１４Ｂは、配線１４Ｂに大電流を流す必要がなく、配線１４Ｂを低抵抗配線として利用する必要もないため、多段階に分けずに構成する。 As can be seen from FIG. 3C, the wiring 20C in the low resistance wiring region C has a larger cross-sectional area than the wiring 14B in the signal wiring region B, and the wiring 26A in the power wiring region A is in the low resistance wiring region C. Compared to the wiring 20C, the cross-sectional area is large. Accordingly, the resistances of the wirings 26A, 14B, and 20C satisfy the relationship shown below.
Wiring 14B> Wiring 20C> Wiring 26A
In this way, the wiring 26A in the power supply wiring region A is divided into three stages, and the cross-sectional area of the wiring 26A is increased (the resistance of the wiring 26A is reduced), whereby a power supply current (large current) is supplied to the wiring 26A. It can flow. Further, the wiring 20C in the low resistance wiring region C is divided into two stages, and the wiring 20C can be used as a low resistance wiring by increasing the cross-sectional area of the wiring 20C (reducing the resistance of the wiring 20C). it can. On the other hand, the wiring 14B in the signal wiring region B does not need to flow a large current through the wiring 14B, and it is not necessary to use the wiring 14B as a low-resistance wiring, and thus is configured without being divided into multiple stages.
　本実施形態によると、電源配線領域Ａの配線２６Ａは、第１配線部１４ａ、第２配線部２０ａ、及び第３配線部２６ａからなり、３段階に分けて構成される。これにより、配線２６Ａのアスペクト比（ここで、「アスペクト比」とは、配線高さ／配線幅をいう）が高い場合であっても、各配線部１４ａ，２０ａ，２６ａのアスペクト比を低くすることができる。そのため、各配線部１４ａ，２０ａ，２６ａにおいて、スパッタ法によるシード膜の形成時に、シード膜の形成不良を招くことなく、オーバーハング部による各配線溝１１ａ，１７ａ，２３ａの閉塞を防止することができるため、各配線部１４ａ，２０ａ，２６ａにボイドが発生することを防止することができる。従って、ボイドを発生させることなく、配線２６Ａを実現することができる。 According to the present embodiment, the wiring 26A in the power supply wiring area A includes the first wiring portion 14a, the second wiring portion 20a, and the third wiring portion 26a, and is configured in three stages. Thereby, even if the aspect ratio of the wiring 26A (here, “aspect ratio” means the wiring height / wiring width) is high, the aspect ratio of each of the wiring portions 14a, 20a, and 26a is lowered. be able to. Therefore, in the wiring portions 14a, 20a, and 26a, when the seed film is formed by the sputtering method, it is possible to prevent the wiring grooves 11a, 17a, and 23a from being blocked by the overhang portion without causing a seed film formation failure. Therefore, it is possible to prevent voids from being generated in the wiring portions 14a, 20a, and 26a. Therefore, the wiring 26A can be realized without generating voids.
　同様に、低抵抗配線領域Ｃの配線２０Ｃは、第１配線部１４ｃ、及び第２配線部２０ｃからなり、２段階に分けて構成される。これにより、配線２０Ｃのアスペクト比が高い場合であっても、各配線部１４ｃ，２０ｃのアスペクト比を低くすることができる。そのため、各配線部１４ｃ，２０ｃにおいて、スパッタ法によるシード膜の形成時に、シード膜の形成不良を招くことなく、オーバーハング部による各配線溝１１ｃ，１７ｃの閉塞を防止することができるため、各配線部１４ｃ，２０ｃにボイドが発生することを防止することができる。従って、ボイドを発生させることなく、配線２０Ｃを実現することができる。 Similarly, the wiring 20C in the low-resistance wiring region C includes a first wiring part 14c and a second wiring part 20c, and is configured in two stages. Thereby, even if the aspect ratio of the wiring 20C is high, the aspect ratio of each of the wiring portions 14c and 20c can be reduced. Therefore, in each of the wiring portions 14c and 20c, when the seed film is formed by the sputtering method, it is possible to prevent the wiring grooves 11c and 17c from being blocked by the overhang portion without causing a seed film formation failure. Generation of voids in the wiring portions 14c and 20c can be prevented. Therefore, the wiring 20C can be realized without generating voids.
　加えて、本実施形態によると、電源配線領域Ａの配線２６Ａ、信号配線領域Ｂの配線１４Ｂ、及び低抵抗配線領域Ｃの配線２０Ｃにおいて、図４(b) に示すように、配線幅Ｗ26A，Ｗ14B，Ｗ20Cを略同一にする一方、図４(a) に示すように、配線高さＨ26A，Ｈ14B，Ｈ20Cを異ならせることにより、相異なる断面積（即ち、相異なる抵抗）の配線２６Ａ，１４Ｂ，２０Ｃを実現する。なお、図４(b) は平面図であって、図４(a) は、図４(b) に示すIVa-IVa線における断面図である。 In addition, according to the present embodiment, in the wiring 26A in the power supply wiring area A, the wiring 14B in the signal wiring area B, and the wiring 20C in the low resistance wiring area C, as shown in FIG. While making W14B and W20C substantially the same, as shown in FIG. 4 (a), the wiring heights H26A, H14B and H20C are made different so that the wirings 26A and 14B having different cross-sectional areas (that is, different resistances). , 20C. 4B is a plan view, and FIG. 4A is a cross-sectional view taken along line IVa-IVa shown in FIG. 4B.
　これに対し、比較例では、電源配線領域Ａの配線１０４ａ、信号配線領域Ｂの配線１０４ｂ、低抵抗配線領域Ｃの配線１０４ｃにおいて、図４(c) に示すように、配線高さＨ104a，Ｈ104b，Ｈ104cを略同一にする一方、図４(d) に示すように、配線幅Ｗ104a，Ｗ104b，Ｗ104cを異ならせることにより、相異なる断面積の配線１０４ａ，１０４ｂ，１０４ｃを実現する。なお、図４(d) は平面図であって、図４(c) は、図４(d) に示すIVc-IVc線における断面図である。 On the other hand, in the comparative example, in the wiring 104a in the power supply wiring area A, the wiring 104b in the signal wiring area B, and the wiring 104c in the low resistance wiring area C, as shown in FIG. , H104c are made substantially the same, while the wiring widths W104a, W104b, W104c are made different as shown in FIG. 4D, thereby realizing the wirings 104a, 104b, 104c having different cross-sectional areas. 4D is a plan view, and FIG. 4C is a cross-sectional view taken along line IVc-IVc shown in FIG. 4D.
　このように、比較例のように配線高さを略同一にし配線幅を異ならせるのではなく、本実施形態のように配線幅を略同一にし配線高さを異ならせることにより、配線幅を最小幅にすることができるため、チップサイズを縮小化することができる。 Thus, instead of making the wiring heights substantially the same and different the wiring widths as in the comparative example, the wiring widths are maximized by making the wiring widths substantially the same and different the wiring heights as in this embodiment. Since the width can be reduced, the chip size can be reduced.
　さらに、本実施形態によると、電源配線領域Ａの配線２６Ａを構成する第２，第３配線部２０ａ，２６ａの断面形状を、下面から上面に向かって幅が大きくなるテーパー形状にする。これにより、例えば、第２配線部２０ａが、図５に示すように、第１配線部１４ｂ寄りに形成されることがあっても、第２配線部２０ａが第１配線部１４ｂとショートすることを防止することができる。 Furthermore, according to the present embodiment, the cross-sectional shapes of the second and third wiring portions 20a and 26a constituting the wiring 26A in the power supply wiring region A are tapered so that the width increases from the lower surface toward the upper surface. Thereby, for example, even if the second wiring portion 20a is formed closer to the first wiring portion 14b as shown in FIG. 5, the second wiring portion 20a is short-circuited with the first wiring portion 14b. Can be prevented.
　同様に、低抵抗配線領域Ｃの配線２０Ｃを構成する第２配線部２０ｃの断面形状を、下面から上面に向かって幅が大きくなるテーパー形状にする。これにより、例えば、第２配線部２０ｃが、図５に示すように、右側（即ち、他の配線部寄り）にずれて形成されることがあっても、第２配線部２０ｃが他の配線部とショートすることを防止することができる。 Similarly, the cross-sectional shape of the second wiring portion 20c constituting the wiring 20C in the low resistance wiring region C is tapered so that the width increases from the lower surface toward the upper surface. Thereby, for example, even if the second wiring portion 20c is formed to be shifted to the right side (that is, closer to the other wiring portion) as shown in FIG. It is possible to prevent a short circuit with the part.
　このように、第２，第３配線部２０ａ，２０ｃ，２６ａの断面形状を、下面から上面に向かって幅が大きくなるテーパー形状にすることにより、第２，第３配線部２０ａ，２０ｃ，２６ａが他の配線部とショートすることを防止することができる。 As described above, the second and third wiring portions 20a, 20c, and 26a are tapered so that the width increases from the lower surface toward the upper surface, thereby forming the second and third wiring portions 20a, 20c, and 26a. Can be prevented from short-circuiting with other wiring portions.
　また、本実施形態によると、第２配線部２０ａ，２０ｃの断面形状を、下面から上面に向かって幅が大きくなるテーパー形状にすることにより、図１(c) に示すように、配線溝１７ａ，１７ｃ内に、導電膜１９を精度良く埋め込むことができる。同様に、第３配線部２６ａの断面形状を、下面から上面に向かって幅が大きくなるテーパー形状にすることにより、図３(a) に示すように、配線溝２３ａ内に、導電膜２５を精度良く埋め込むことができる。 In addition, according to the present embodiment, the cross-sectional shape of the second wiring portions 20a and 20c is tapered so that the width increases from the lower surface toward the upper surface, thereby forming the wiring groove 17a as shown in FIG. , 17c, the conductive film 19 can be embedded with high accuracy. Similarly, by making the cross-sectional shape of the third wiring portion 26a into a tapered shape whose width increases from the lower surface to the upper surface, the conductive film 25 is formed in the wiring groove 23a as shown in FIG. Can be embedded with high accuracy.
　ここで、電源配線領域Ａの配線２６Ａ、及び低抵抗配線領域Ｃの配線２０Ｃのアスペクト比は、０．５以上１．０以下であることが好ましい。アスペクト比が０．５以上１．０以下の配線の場合、従来において、オーバーハング部による配線溝の閉塞によって配線にボイドが発生する可能性が高く、従来技術において、シード膜の形成不良によって配線にボイドが発生する可能性が高いため、本発明を有効に発揮することができる。 Here, the aspect ratio of the wiring 26A in the power supply wiring region A and the wiring 20C in the low resistance wiring region C is preferably 0.5 or more and 1.0 or less. In the case of a wiring having an aspect ratio of 0.5 or more and 1.0 or less, there is a high possibility that voids are generated in the wiring due to the blocking of the wiring groove by the overhang portion. Therefore, the present invention can be effectively exhibited.
　またここで、電源配線領域Ａの配線２６Ａ、及び低抵抗配線領域Ｃの配線２０Ｃの配線幅は、７０ｎｍ以下であることが好ましい。配線幅が７０ｎｍ以下の配線の場合、従来において、オーバーハング部による配線溝の閉塞によって配線にボイドが発生する可能性が高く、従来技術において、シード膜の形成不良によって配線にボイドが発生する可能性が高いため、本発明を有効に発揮することができる。 Here, the wiring width of the wiring 26A in the power supply wiring region A and the wiring 20C in the low resistance wiring region C is preferably 70 nm or less. In the case of a wiring having a wiring width of 70 nm or less, conventionally, there is a high possibility that a void will be generated in the wiring due to the blockage of the wiring groove by the overhang portion, and in the conventional technique, a void may be generated due to a seed film formation failure. Since this property is high, the present invention can be exhibited effectively.
　（第２の実施形態）
　以下に、本発明の第２の実施形態に係る半導体装置について、図６、図７、図８、図９、及び図１０を参照しながら説明する。図６は、本発明の第２の実施形態に係る半導体装置の構成を示す平面図である。図７～図１０は、本発明の第２の実施形態に係る半導体装置の構成を示す断面図であって、具体的には、図７は、図６に示すVII-VII線における断面図であり、図８は、図６に示すVIII-VIII線における断面図であり、図９は、図６に示すIX-IX線における断面図であり、図１０は、図６に示すX-X線における断面図である。ここで、図６～図７において、左側の領域を電源配線が形成される電源配線領域Ａとし、中央の領域を信号配線が形成される信号配線領域Ｂとし、右側の領域を低抵抗配線が形成される低抵抗配線領域Ｃとする。また、図６～図１０において、第１の実施形態における構成要素と同一の構成要素には、図３(c) に示す符号と同一の符号を付す。従って、本実施形態では、第１の実施形態と相違する点について主に説明し、第１の実施形態と共通する点については説明を適宜省略する。 (Second Embodiment)
Hereinafter, a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 6, 7, 8, 9, and 10. FIG. 6 is a plan view showing a configuration of a semiconductor device according to the second embodiment of the present invention. 7 to 10 are sectional views showing the configuration of the semiconductor device according to the second embodiment of the present invention. Specifically, FIG. 7 is a sectional view taken along line VII-VII shown in FIG. 8 is a sectional view taken along line VIII-VIII shown in FIG. 6, FIG. 9 is a sectional view taken along line IX-IX shown in FIG. 6, and FIG. 10 is a sectional view taken along line XX shown in FIG. FIG. 6 to 7, the left region is a power supply wiring region A where power supply wiring is formed, the central region is a signal wiring region B where signal wiring is formed, and the right region is a low resistance wiring. The low resistance wiring region C is formed. 6 to 10, the same reference numerals as those shown in FIG. 3C are given to the same constituent elements as those in the first embodiment. Therefore, in the present embodiment, points that differ from the first embodiment will be mainly described, and descriptions of points that are the same as those in the first embodiment will be omitted as appropriate.
　なお、本実施形態に記載の材料及び数値は、好ましい材料及び数値を記載したに過ぎず、これらに限定されることはない。また、本発明の効果を奏する範囲において、種々の変形及び応用が可能である。 Note that the materials and numerical values described in the present embodiment are merely preferable materials and numerical values, and are not limited thereto. In addition, various modifications and applications are possible within the scope of the effects of the present invention.
　本実施形態に係る半導体装置のVII-VII線における断面構成について、図７を参照しながら説明する。 A cross-sectional configuration of the semiconductor device according to the present embodiment taken along line VII-VII will be described with reference to FIG.
　図７に示すように、本実施形態に係る半導体装置は、第１の実施形態における構成要素に加えて、ライナー絶縁膜２７上に順次形成された層間絶縁膜２８、ライナー絶縁膜３２、層間絶縁膜３３、ライナー絶縁膜３７、及び層間絶縁膜３８をさらに備えている。 As shown in FIG. 7, in addition to the components in the first embodiment, the semiconductor device according to the present embodiment includes an interlayer insulating film 28, a liner insulating film 32, and an interlayer insulating film sequentially formed on the liner insulating film 27. A film 33, a liner insulating film 37, and an interlayer insulating film 38 are further provided.
　本実施形態に係る半導体装置のVIII-VIII線における断面構成について、図８を参照しながら説明する。 The cross-sectional configuration of the semiconductor device according to the present embodiment taken along line VIII-VIII will be described with reference to FIG.
　図７には図示されないが、本実施形態に係る半導体装置は、図８に示すように、ライナー絶縁膜２７及び層間絶縁膜２８に形成されたビア３１ａｘと、層間絶縁膜２８に形成された第１配線部３１ａｙと、ライナー絶縁膜３２及び層間絶縁膜３３に形成された第２配線部３６ａと、ライナー絶縁膜３７及び層間絶縁膜３８に形成された第３配線部４１ａとをさらに備えている。 Although not illustrated in FIG. 7, the semiconductor device according to the present embodiment includes a via 31 ax formed in the liner insulating film 27 and the interlayer insulating film 28 and a first layer formed in the interlayer insulating film 28 as illustrated in FIG. 8. 1 wiring part 31ay, the 2nd wiring part 36a formed in the liner insulating film 32 and the interlayer insulating film 33, and the 3rd wiring part 41a formed in the liner insulating film 37 and the interlayer insulating film 38 are further provided. .
　詳細には、ビア３１ａｘは、ビア孔の底面及び側壁に形成されたバリアメタル膜２９ａｘと、ビア孔内にバリアメタル膜２９ａｘを介して埋め込まれた導電膜３０ａｘとからなる。第１配線部３１ａｙは、配線溝の底面及び側壁に形成されたバリアメタル膜２９ａｙと、配線溝内にバリアメタル膜２９ａｙを介して埋め込まれた導電膜３０ａｙとからなる。ここで、ビア３１ａｘ及び第１配線部３１ａｙは、デュアルダマシン法により形成される。 Specifically, the via 31ax includes a barrier metal film 29ax formed on the bottom and side walls of the via hole, and a conductive film 30ax embedded in the via hole via the barrier metal film 29ax. The first wiring portion 31ay includes a barrier metal film 29ay formed on the bottom and side walls of the wiring groove, and a conductive film 30ay embedded in the wiring groove via the barrier metal film 29ay. Here, the via 31ax and the first wiring portion 31ay are formed by a dual damascene method.
　第２配線部３６ａは、配線溝の側壁に形成されたバリアメタル膜３４ａと、配線溝内にバリアメタル膜３４ａを介して埋め込まれた導電膜３５ａとからなる。第３配線部４１ａは、配線溝の側壁に形成されたバリアメタル膜３９ａと、配線溝内にバリアメタル膜３９ａを介して埋め込まれた導電膜４０ａとからなる。 The second wiring portion 36a includes a barrier metal film 34a formed on the side wall of the wiring groove and a conductive film 35a embedded in the wiring groove via the barrier metal film 34a. The third wiring portion 41a includes a barrier metal film 39a formed on the side wall of the wiring groove, and a conductive film 40a embedded in the wiring groove via the barrier metal film 39a.
　第２配線部３６ａの導電膜３５ａは、第１配線部３１ａｙの導電膜３０ａｙに接して形成され、第３配線部４１ａの導電膜４０ａは、第２配線部３６ａの導電膜３５ａに接して形成され、第１配線部３１ａｙ、第２配線部３６ａ、及び第３配線部４１ａからなる配線４１Ａが構成される。 The conductive film 35a of the second wiring part 36a is formed in contact with the conductive film 30ay of the first wiring part 31ay, and the conductive film 40a of the third wiring part 41a is formed in contact with the conductive film 35a of the second wiring part 36a. Thus, a wiring 41A including the first wiring part 31ay, the second wiring part 36a, and the third wiring part 41a is configured.
　このように、電源配線領域Ａにおいて、配線４１Ａが、ビア３１ａｘを介して、配線２６Ａと接続している。 Thus, in the power supply wiring area A, the wiring 41A is connected to the wiring 26A via the via 31ax.
　本実施形態に係る半導体装置のIX-IX線における断面構成について、図９を参照しながら説明する。 The cross-sectional configuration of the semiconductor device according to the present embodiment taken along the line IX-IX will be described with reference to FIG.
　図７には図示されないが、本実施形態に係る半導体装置は、図９に示すように、ライナー絶縁膜１５及び層間絶縁膜１６に形成された第１ビア部２０ｂと、ライナー絶縁膜２１及び層間絶縁膜２２に形成された第２ビア部２６ｂと、ライナー絶縁膜２７及び層間絶縁膜２８に形成されたビア３１ｂｘと、層間絶縁膜２８に形成された第１配線部３１ｂｙとを備えている。 Although not shown in FIG. 7, the semiconductor device according to the present embodiment includes the first via portion 20b formed in the liner insulating film 15 and the interlayer insulating film 16, the liner insulating film 21 and the interlayer as shown in FIG. A second via portion 26 b formed in the insulating film 22, a via 31 bx formed in the liner insulating film 27 and the interlayer insulating film 28, and a first wiring portion 31 by formed in the interlayer insulating film 28 are provided.
　詳細には、第１ビア部２０ｂは、ビア孔の側壁に形成されたバリアメタル膜１８ｂと、ビア孔内にバリアメタル膜１８ｂを介して埋め込まれた導電膜１９ｂとからなる。第２ビア部２６ｂは、ビア孔の側壁に形成されたバリアメタル膜２４ｂと、ビア孔内にバリアメタル膜２４ｂを介して埋め込まれた導電膜２５ｂとからなる。 Specifically, the first via portion 20b includes a barrier metal film 18b formed on the side wall of the via hole and a conductive film 19b embedded in the via hole via the barrier metal film 18b. The second via portion 26b includes a barrier metal film 24b formed on the sidewall of the via hole and a conductive film 25b embedded in the via hole via the barrier metal film 24b.
　第２ビア部２６ｂの導電膜２５ｂは、第１ビア部２０ｂの導電膜１９ｂに接して形成されている。そのため、第１ビア部２０ｂ、及び第２ビア部２６ｂを合わせて、一つのビアと見なすことができ、信号配線領域Ｂには、第１ビア部２０ｂ、及び第２ビア部２６ｂからなるビア２６Ｖｂが構成される。 The conductive film 25b of the second via portion 26b is formed in contact with the conductive film 19b of the first via portion 20b. Therefore, the first via portion 20b and the second via portion 26b can be regarded as one via, and the signal wiring region B has a via 26Vb composed of the first via portion 20b and the second via portion 26b. Is configured.
　ビア３１ｂｘは、ビア孔の底面及び側壁に形成されたバリアメタル膜２９ｂｘと、ビア孔内にバリアメタル膜２９ｂｘを介して埋め込まれた導電膜３０ｂｘとからなる。第１配線部３１ｂｙは、配線溝の底面及び側壁に形成されたバリアメタル膜２９ｂｙと、配線溝内にバリアメタル膜２９ｂｙを介して埋め込まれた導電膜３０ｂｙとからなり、第１配線部３１ｂｙからなる配線３１Ｂが構成される。ここで、ビア３１ｂｘ及び第１配線部３１ｂｙは、デュアルダマシン法により形成される。 The via 31bx includes a barrier metal film 29bx formed on the bottom and side walls of the via hole and a conductive film 30bx embedded in the via hole via the barrier metal film 29bx. The first wiring part 31by includes a barrier metal film 29by formed on the bottom and side walls of the wiring groove, and a conductive film 30by embedded in the wiring groove via the barrier metal film 29by. A wiring 31B is formed. Here, the via 31bx and the first wiring part 31by are formed by a dual damascene method.
　このように、信号配線領域Ｂにおいて、配線３１Ｂが、ビア３１ｂｘ及びビア２６Ｖｂを順次介して、配線１４Ｂと接続している。 Thus, in the signal wiring region B, the wiring 31B is connected to the wiring 14B via the via 31bx and the via 26Vb in this order.
　本実施形態に係る半導体装置のX-X線における断面構成について、図１０を参照しながら説明する。 The cross-sectional configuration of the semiconductor device according to the present embodiment taken along line XX will be described with reference to FIG.
　図７には図示されないが、本実施形態に係る半導体装置は、図１０に示すように、ライナー絶縁膜２１及び層間絶縁膜２２に形成された第１ビア部２６ｃと、ライナー絶縁膜２７及び層間絶縁膜２８に形成されたビア３１ｃｘと、層間絶縁膜２８に形成された第１配線部３１ｃｙと、ライナー絶縁膜３２及び層間絶縁膜３３に形成された第２配線部３６ｃとを備えている。 Although not shown in FIG. 7, the semiconductor device according to the present embodiment includes a first via portion 26c formed in the liner insulating film 21 and the interlayer insulating film 22, the liner insulating film 27, and the interlayer as shown in FIG. A via 31 cx formed in the insulating film 28, a first wiring part 31 cy formed in the interlayer insulating film 28, and a second wiring part 36 c formed in the liner insulating film 32 and the interlayer insulating film 33 are provided.
　詳細には、第１ビア部２６ｃは、ビア孔の側壁に形成されたバリアメタル膜２４ｃと、ビア孔内にバリアメタル膜２４ｃを介して埋め込まれた導電膜２５ｃとからなり、第１ビア部２６ｃからなるビア２６Ｖｃが構成される。 Specifically, the first via portion 26c includes a barrier metal film 24c formed on the side wall of the via hole and a conductive film 25c embedded in the via hole via the barrier metal film 24c. A via 26Vc composed of 26c is formed.
　ビア３１ｃｘは、ビア孔の底面及び側壁に形成されたバリアメタル膜２９ｃｘと、ビア孔内にバリアメタル膜２９ｃｘを介して埋め込まれた導電膜３０ｃｘとからなる。第１配線部３１ｃｙは、配線溝の底面及び側壁に形成されたバリアメタル膜２９ｃｙと、配線溝内にバリアメタル膜２９ｃｙを介して埋め込まれた導電膜３０ｃｙとからなる。ここで、ビア３１ｃｘ及び第１配線部３１ｃｙは、デュアルダマシン法により形成される。 The via 31cx includes a barrier metal film 29cx formed on the bottom and side walls of the via hole and a conductive film 30cx embedded in the via hole via the barrier metal film 29cx. The first wiring portion 31 cy includes a barrier metal film 29 cy formed on the bottom and side walls of the wiring groove, and a conductive film 30 cy embedded in the wiring groove via the barrier metal film 29 cy. Here, the via 31cx and the first wiring part 31cy are formed by a dual damascene method.
　第２配線部３６ｃは、配線溝の側壁に形成されたバリアメタル膜３４ｃと、配線溝内にバリアメタル膜３４ｃを介して埋め込まれた導電膜３５ｃとからなる。第２配線部３６ｃの導電膜３５ｃは、第１配線部３１ｃｙの導電膜３０ｃｙに接して形成され、第１配線部３１ｃｙ及び第２配線部３６ｃからなる配線３６Ｃが構成される。 The second wiring portion 36c includes a barrier metal film 34c formed on the side wall of the wiring groove, and a conductive film 35c embedded in the wiring groove through the barrier metal film 34c. The conductive film 35c of the second wiring portion 36c is formed in contact with the conductive film 30cy of the first wiring portion 31cy, and a wiring 36C including the first wiring portion 31cy and the second wiring portion 36c is configured.
　このように、低抵抗配線領域Ｃにおいて、配線３６Ｃが、ビア３１ｃｘ及びビア２６Ｖｃを順次介して、配線２０Ｃと接続している。 Thus, in the low resistance wiring region C, the wiring 36C is connected to the wiring 20C through the via 31cx and the via 26Vc in this order.
　本実施形態に係る半導体装置の平面構成について、図６を参照しながら説明する。 The planar configuration of the semiconductor device according to the present embodiment will be described with reference to FIG.
　図６に示すように、電源配線領域Ａには、配線２６Ａ（図７，図８参照）と、配線４１Ａ（図８参照）とが構成されている。信号配線領域Ｂには、配線１４Ｂ（図７，図９参照）と、配線３１Ｂ（図９参照）とが構成されている。低抵抗配線領域Ｃには、配線２０Ｃ（図７，図１０参照）と、配線３６Ｃ（図１０参照）とが構成されている。 As shown in FIG. 6, in the power supply wiring area A, wiring 26A (see FIGS. 7 and 8) and wiring 41A (see FIG. 8) are configured. In the signal wiring region B, a wiring 14B (see FIGS. 7 and 9) and a wiring 31B (see FIG. 9) are configured. In the low resistance wiring region C, a wiring 20C (see FIGS. 7 and 10) and a wiring 36C (see FIG. 10) are configured.
　ここで、低抵抗配線領域Ｃの配線３６Ｃは、信号配線領域Ｂの配線３１Ｂに比べて、断面積が大きく、電源配線領域Ａの配線４１Ａは、低抵抗配線領域Ｃの配線３６Ｃに比べて、断面積が大きい。そのため、配線４１Ａ，３１Ｂ，３６Ｃの抵抗は、以下に示す関係を満たす。
配線３１Ｂ ＞ 配線３６Ｃ ＞ 配線４１Ａ
　ここで、バリアメタル膜１８ｂ、２４ｂ，２４ｃ、２９ａｘ，２９ｂｘ，２９ｃｘ、２９ａｙ，２９ｂｙ，２９ｃｙ、３４ａ，３４ｃ、及び３９ａの材料としては、第１の実施形態と同様に、例えば、タンタル（Ｔａ）、窒化タンタル（ＴａＮ）、ルテニウム（Ｒｕ）、又は窒化ルテニウム（ＲｕＮ）を用いることが好ましい。 Here, the wiring 36C in the low resistance wiring region C has a larger cross-sectional area than the wiring 31B in the signal wiring region B, and the wiring 41A in the power supply wiring region A is compared with the wiring 36C in the low resistance wiring region C. Large cross-sectional area. Therefore, the resistances of the wirings 41A, 31B, and 36C satisfy the relationship shown below.
Wiring 31B> Wiring 36C> Wiring 41A
Here, as the material of the barrier metal films 18b, 24b, 24c, 29ax, 29bx, 29cx, 29ay, 29by, 29cy, 34a, 34c, and 39a, for example, tantalum (Ta), as in the first embodiment. It is preferable to use tantalum nitride (TaN), ruthenium (Ru), or ruthenium nitride (RuN).
　また、導電膜１９ｂ、２５ｂ，２５ｃ、３０ａｘ，３０ｂｘ，３０ｃｘ、３０ａｙ，３０ｂｙ，３０ｃｙ、３５ａ，３５ｃ、及び４０ａの材料としては、第１の実施形態と同様に、例えば、銅（Ｃｕ）を用いる。 Further, as the material of the conductive films 19b, 25b, 25c, 30ax, 30bx, 30cx, 30ay, 30by, 30cy, 35a, 35c, and 40a, for example, copper (Cu) is used as in the first embodiment. .
　また、層間絶縁膜２８，３３，３８は、第１の実施形態と同様に、誘電率の低い膜であることが好ましい。 Also, the interlayer insulating films 28, 33, and 38 are preferably films having a low dielectric constant, as in the first embodiment.
　また、ライナー絶縁膜３２，３７は、第１の実施形態と同様に、誘電率の高い膜であることが好ましい。 Also, the liner insulating films 32 and 37 are preferably films having a high dielectric constant, as in the first embodiment.
　また、電源配線領域Ａの配線４１Ａ、及び低抵抗配線領域Ｃの配線３６Ｃのアスペクト比は、第１の実施形態と同様に、０．５以上１．０以下であることが好ましい。 Further, the aspect ratio of the wiring 41A in the power supply wiring area A and the wiring 36C in the low resistance wiring area C is preferably 0.5 or more and 1.0 or less, as in the first embodiment.
　また、電源配線領域Ａの配線４１Ａ、及び低抵抗配線領域Ｃの配線３６Ｃの配線幅は、第１の実施形態と同様に、７０ｎｍ以下であることが好ましい。 Also, the wiring width of the wiring 41A in the power supply wiring region A and the wiring 36C in the low resistance wiring region C is preferably 70 nm or less, as in the first embodiment.
　本実施形態によると、電源配線領域Ａにおいて、配線２６Ａを構成する各配線部１４ａ，２０ａ，２６ａ、及び配線４１Ａを構成する各配線部３１ａｙ，３６ａ，４１ａの各々において、スパッタ法によるシード膜の形成時に、シード膜の形成不良を招くことなく、オーバーハング部による各配線溝の閉塞を防止することができるため、各配線部１４ａ，２０ａ，２６ａ，３１ａｙ，３６ａ，４１ａにボイドが発生することを防止することができる。従って、ボイドを発生させることなく、配線２６Ａ，４１Ａを実現することができる。 According to the present embodiment, in the power supply wiring region A, the seed film is formed by sputtering in each of the wiring portions 14a, 20a, 26a constituting the wiring 26A and each of the wiring portions 31ay, 36a, 41a constituting the wiring 41A. During the formation, it is possible to prevent the wiring grooves from being blocked by the overhang portion without causing the formation failure of the seed film. Therefore, voids are generated in the wiring portions 14a, 20a, 26a, 31ay, 36a, and 41a. Can be prevented. Accordingly, the wirings 26A and 41A can be realized without generating voids.
　同様に、低抵抗配線領域Ｃにおいて、配線２０Ｃを構成する各配線部１４ｃ，２０ｃ、及び配線３６Ｃを構成する各配線部３１ｃｙ，３６ｃの各々において、スパッタ法によるシード膜の形成時に、シード膜の形成不良を招くことなく、オーバーハング部による各配線溝の閉塞を防止することができるため、各配線部１４ｃ，２０ｃ，３１ｃｙ，３６ｃにボイドが発生することを防止することができる。従って、ボイドを発生させることなく、配線２０Ｃ，３６Ｃを実現することができる。 Similarly, in the low resistance wiring region C, when the seed film is formed by sputtering in each of the wiring parts 14c and 20c constituting the wiring 20C and each of the wiring parts 31cy and 36c constituting the wiring 36C, Since it is possible to prevent each wiring groove from being blocked by the overhang portion without causing formation failure, it is possible to prevent the occurrence of voids in the respective wiring portions 14c, 20c, 31cy, and 36c. Therefore, the wirings 20C and 36C can be realized without generating voids.
　加えて、本実施形態によると、電源配線領域Ａの配線２６Ａ，４１Ａ、信号配線領域Ｂの配線１４Ｂ，３１Ｂ、及び低抵抗配線領域Ｃの配線２０Ｃ，３６Ｃの配線幅を最小幅にし、チップサイズを縮小化することができる。 In addition, according to the present embodiment, the wiring widths of the wirings 26A and 41A in the power supply wiring region A, the wirings 14B and 31B in the signal wiring region B, and the wirings 20C and 36C in the low resistance wiring region C are minimized, and the chip size is reduced. Can be reduced.
　さらに、本実施形態によると、電源配線領域Ａにおいて、配線２６Ａを構成する第２，第３配線部２０ａ，２６ａ、及び配線４１Ａを構成する第２，第３配線部３６ａ，４１ａの断面形状を、下面から上面に向かって幅が大きくなるテーパー形状にする。これにより、第２，第３配線部２０ａ，３６ａ，２６ａ，４１ａが他の配線とショートすることを防止することができる。それと共に、各配線溝内に、各導電膜１９ａ，３５ａ，２５ａ，４０ａを精度良く埋め込むことができる。 Furthermore, according to the present embodiment, in the power supply wiring region A, the cross-sectional shapes of the second and third wiring portions 20a and 26a constituting the wiring 26A and the second and third wiring portions 36a and 41a constituting the wiring 41A are shown. The taper has a width that increases from the lower surface toward the upper surface. Thereby, it is possible to prevent the second and third wiring portions 20a, 36a, 26a, and 41a from being short-circuited with other wirings. At the same time, the conductive films 19a, 35a, 25a, and 40a can be accurately embedded in the wiring grooves.
　同様に、低抵抗配線領域Ｃにおいて、配線２０Ｃを構成する第２配線部２０ｃ、及び配線３６Ｃを構成する第２配線部３６ｃの断面形状を、下面から上面に向かって幅が大きくなるテーパー形状にする。これにより、第２配線部２０ｃ，３６ｃが他の配線とショートすることを防止することができる。それと共に、各配線溝内に、各導電膜１９ｃ，３５ｃを精度良く埋め込むことができる。 Similarly, in the low resistance wiring region C, the cross-sectional shape of the second wiring part 20c constituting the wiring 20C and the second wiring part 36c constituting the wiring 36C is tapered so that the width increases from the lower surface to the upper surface. To do. Thereby, it is possible to prevent the second wiring portions 20c and 36c from being short-circuited with other wiring. At the same time, the conductive films 19c and 35c can be accurately embedded in the wiring grooves.
　ここで、本発明を適用して、配線幅が例えば７０ｎｍ以上で、且つ配線高さが例えば１μｍ以上の配線（具体的には例えば、ボンディングダメージを低減するグローバル配線）を形成する場合について、図１１(a) を参照しながら説明する。 Here, when the present invention is applied to form a wiring having a wiring width of, for example, 70 nm or more and a wiring height of, for example, 1 μm or more (specifically, for example, a global wiring that reduces bonding damage), FIG. This will be described with reference to 11 (a).
　図１１(a) に示すように、層間絶縁膜５０に、第１配線部５４（第１配線部５４は、配線溝の底面及び側壁に形成されたバリアメタル膜５２と、配線溝内にバリアメタル膜５２を介して埋め込まれた導電膜５３とからなる）を形成した後、層間絶縁膜５０及び第１配線部５４上に、ライナー絶縁膜５５、及び層間絶縁膜５６を順次形成する。その後、ライナー絶縁膜５５及び層間絶縁膜５６に、第２配線部６０（第２配線部６０は、配線溝の側壁に形成されたバリアメタル膜５８と、配線溝内にバリアメタル膜５８を介して埋め込まれた導電膜５９とからなる）を形成した後、層間絶縁膜５６及び第２配線部６０上に、ライナー絶縁膜６１、及び層間絶縁膜６２を順次形成する。 As shown in FIG. 11A, the interlayer insulating film 50 includes a first wiring portion 54 (the first wiring portion 54 includes a barrier metal film 52 formed on the bottom and side walls of the wiring groove, and a barrier in the wiring groove. After that, the liner insulating film 55 and the interlayer insulating film 56 are sequentially formed on the interlayer insulating film 50 and the first wiring part 54. Thereafter, the liner insulating film 55 and the interlayer insulating film 56 are provided with the second wiring portion 60 (the second wiring portion 60 is formed with a barrier metal film 58 formed on the sidewall of the wiring groove and a barrier metal film 58 in the wiring groove. Then, a liner insulating film 61 and an interlayer insulating film 62 are sequentially formed on the interlayer insulating film 56 and the second wiring portion 60.
　次に、ライナー絶縁膜６１及び層間絶縁膜６２に、配線溝６３を形成した後、層間絶縁膜６２上、並びに配線溝６３の底面及び側壁に、バリアメタル膜６４ｚを形成する。その後、バリアメタル膜６４ｚのうち、配線溝６３の底面に形成された部分を除去する。その後、配線溝６３内に露出する第２配線部６０、及びバリアメタル膜６４ｚ上に、導電膜６５ｚを形成する。 Next, after forming a wiring groove 63 in the liner insulating film 61 and the interlayer insulating film 62, a barrier metal film 64z is formed on the interlayer insulating film 62 and on the bottom and side walls of the wiring groove 63. Thereafter, a portion of the barrier metal film 64z formed on the bottom surface of the wiring groove 63 is removed. Thereafter, a conductive film 65z is formed on the second wiring portion 60 exposed in the wiring groove 63 and the barrier metal film 64z.
　その後、図示しないが、ＣＭＰ法により、導電膜６５ｚ及びバリアメタル膜６４ｚのうち、配線溝６３外に形成された部分を除去する。このようにして、配線溝６３内に、バリアメタル膜を介して、導電膜が埋め込まれた第３配線部を形成する。 Thereafter, although not shown, portions of the conductive film 65z and the barrier metal film 64z formed outside the wiring trench 63 are removed by CMP. In this manner, a third wiring portion in which the conductive film is embedded is formed in the wiring groove 63 via the barrier metal film.
　このようにして、第１配線部５４、第２配線部６０、及び第３配線部からなり、配線幅が例えば７０ｎｍ以上で、且つ配線高さが例えば１μｍ以上のグローバル配線を形成する。 In this way, a global wiring having the first wiring portion 54, the second wiring portion 60, and the third wiring portion and having a wiring width of, for example, 70 nm or more and a wiring height of, for example, 1 μm or more is formed.
　これに対し、本発明を適用せずに、配線幅が例えば７０ｎｍ以上で、且つ配線高さが例えば１μｍ以上のグローバル配線を形成する場合について、図１１(b) を参照しながら説明する。 On the other hand, a case where a global wiring having a wiring width of, for example, 70 nm or more and a wiring height of, for example, 1 μm or more without forming the present invention is described with reference to FIG.
　図１１(b) に示すように、層間絶縁膜２５０に、配線溝２５１を形成した後、層間絶縁膜２５０上、並びに配線溝２５１の底面及び側壁に、バリアメタル膜２５２ｚを形成する。その後、バリアメタル膜２５２ｚ上に、導電膜２５３ｚを形成する。 As shown in FIG. 11B, after a wiring groove 251 is formed in the interlayer insulating film 250, a barrier metal film 252z is formed on the interlayer insulating film 250 and on the bottom and side walls of the wiring groove 251. Thereafter, a conductive film 253z is formed over the barrier metal film 252z.
　その後、図示しないが、ＣＭＰ法により、導電膜２５３ｚ及びバリアメタル膜２５２ｚのうち、配線溝２５１外に形成された部分を除去する。このようにして、配線溝２５１内に、バリアメタル膜を介して、導電膜が埋め込まれたグローバル配線を形成する。 Thereafter, although not shown, portions of the conductive film 253z and the barrier metal film 252z formed outside the wiring trench 251 are removed by CMP. In this manner, a global wiring in which the conductive film is embedded is formed in the wiring trench 251 via the barrier metal film.
　図１１(a) 及び図１１(b) から判るように、配線溝６３のアスペクト比は、配線溝２５１のアスペクト比よりも低いため、配線溝６３内を埋め込むのに必要とされる導電膜６５ｚの膜厚を、配線溝２５１内を埋め込むのに必要とされる導電膜２５３ｚの膜厚よりも薄くすることができる。また、導電膜６５ｚのうち配線溝６３外に形成された部分量は、導電膜２５３ｚのうち配線溝２５１外に形成された部分量よりも少なく、導電膜６５ｚのうちＣＭＰ法により除去すべき量を、導電膜２５３ｚのうちＣＭＰ法により除去すべき量よりも少なくすることができる。 As can be seen from FIGS. 11A and 11B, since the aspect ratio of the wiring groove 63 is lower than the aspect ratio of the wiring groove 251, the conductive film 65z required to fill the wiring groove 63 is used. Can be made thinner than the film thickness of the conductive film 253z required to fill the wiring trench 251. Further, the amount of the conductive film 65z formed outside the wiring groove 63 is smaller than the amount of the conductive film 253z formed outside the wiring groove 251 and the amount of the conductive film 65z to be removed by the CMP method. Can be made smaller than the amount of the conductive film 253z to be removed by the CMP method.
　このように、本発明を適用してグローバル配線を形成した場合、導電膜の形成工程数は増加するものの、１度に形成すべき導電膜の膜厚を薄くすることができる。また、ＣＭＰ法による導電膜の除去工程数は増加するものの、１度に除去すべき導電膜量を低減することができる。 Thus, when a global wiring is formed by applying the present invention, the number of conductive film formation steps increases, but the thickness of the conductive film to be formed at a time can be reduced. Further, although the number of steps of removing the conductive film by the CMP method increases, the amount of the conductive film to be removed at a time can be reduced.
　＜第１の実施形態の変形例１＞
　以下に、本発明の第１の実施形態の変形例１に係る半導体装置の製造方法について説明する。 <Variation 1 of the first embodiment>
A method for manufacturing a semiconductor device according to Modification 1 of the first embodiment of the present invention will be described below.
　まず、層間絶縁膜に、第１配線部を形成する。その後、第１配線部（具体的には、後工程において、その上に第２配線部が形成される第１配線部）の表面に、金属を含むキャップ膜を形成する。その後、層間絶縁膜及びキャップ膜上に、ライナー絶縁膜を形成する。その後、ライナー絶縁膜上に、層間絶縁膜を形成する。その後、例えばフッ素を含有するフッ素含有ガスを用いたエッチングにより、ライナー絶縁膜及び層間絶縁膜に、キャップ膜の表面を露出させる配線溝を形成する。その後、第１の実施形態における図１(c) ～図３(c) に示す工程と同様の工程を順次行い、本変形例に係る半導体装置を製造することができる。 First, a first wiring portion is formed in the interlayer insulating film. Thereafter, a cap film containing a metal is formed on the surface of the first wiring part (specifically, the first wiring part on which the second wiring part is formed in a later step). Thereafter, a liner insulating film is formed on the interlayer insulating film and the cap film. Thereafter, an interlayer insulating film is formed on the liner insulating film. Thereafter, for example, by etching using a fluorine-containing gas containing fluorine, a wiring groove that exposes the surface of the cap film is formed in the liner insulating film and the interlayer insulating film. Thereafter, steps similar to those shown in FIGS. 1C to 3C in the first embodiment are sequentially performed, and the semiconductor device according to the present modification can be manufactured.
　第１の実施形態と本変形例との製造方法上の相違点は、以下に示す点である。 The differences in the manufacturing method between the first embodiment and this modification are as follows.
　第１の実施形態では、図１(a) に示すように、層間絶縁膜１０に、第１配線部１４ａ～１４ｃを形成する。その後、層間絶縁膜１０及び第１配線部１４ａ～１４ｃ上に、ライナー絶縁膜１５を形成する。その後、ライナー絶縁膜１５上に、層間絶縁膜１６を形成する。その後、図１(b) に示すように、ライナー絶縁膜１５及び層間絶縁膜１６に、第１配線部１４ａ，１４ｃの表面を露出させる配線溝１７ａ，１７ｃを形成する。これに対し、本変形例では、第１配線部の形成の後で、且つライナー絶縁膜の形成の前に、第１配線部の表面に、金属を含むキャップ膜を形成する。その後、ライナー絶縁膜上に、層間絶縁膜を形成し、ライナー絶縁膜及び層間絶縁膜に、第１配線部の表面ではなく、キャップ膜の表面を露出させる配線溝を形成する。 In the first embodiment, the first wiring portions 14a to 14c are formed in the interlayer insulating film 10 as shown in FIG. Thereafter, the liner insulating film 15 is formed on the interlayer insulating film 10 and the first wiring portions 14a to 14c. Thereafter, an interlayer insulating film 16 is formed on the liner insulating film 15. Thereafter, as shown in FIG. 1B, wiring grooves 17a and 17c are formed in the liner insulating film 15 and the interlayer insulating film 16 to expose the surfaces of the first wiring portions 14a and 14c. On the other hand, in this modification, a cap film containing a metal is formed on the surface of the first wiring part after the formation of the first wiring part and before the formation of the liner insulating film. Thereafter, an interlayer insulating film is formed on the liner insulating film, and a wiring groove that exposes the surface of the cap film, not the surface of the first wiring portion, is formed in the liner insulating film and the interlayer insulating film.
　第１の実施形態と本変形例との構成上の相違点は、次に示す点である。本変形例に係る半導体装置は、第１の実施形態と同様の構成要素に加えて、第１配線部とライナー絶縁膜との間に形成され、第１配線部の表面を覆うキャップ膜をさらに備えている。キャップ膜は、金属を含み、第１配線部は、キャップ膜を介して、第２配線部と電気的に接続している。 The differences in configuration between the first embodiment and this modification are as follows. In addition to the same components as in the first embodiment, the semiconductor device according to this modification further includes a cap film that is formed between the first wiring portion and the liner insulating film and covers the surface of the first wiring portion. I have. The cap film includes a metal, and the first wiring part is electrically connected to the second wiring part via the cap film.
　ここで、第１の実施形態における図１(b) に示す工程において、チャンバー（図示せず）内において、エッチングガスとして、例えばフッ素含有ガスを用いたエッチングにより、第１配線部１４ａ，１４ｃの表面を露出させる配線溝１７ａ，１７ｃを形成した場合、以下に示す懸念がある。 Here, in the step shown in FIG. 1B in the first embodiment, in the chamber (not shown), the first wiring portions 14a and 14c are etched by etching using, for example, a fluorine-containing gas as an etching gas. When the wiring grooves 17a and 17c that expose the surface are formed, there is a concern shown below.
　配線溝１７ａ，１７ｃ内に露出する第１配線部１４ａ，１４ｃにおける導電膜１３ａ，１３ｃは、例えば銅からなる。そのため、配線溝１７ａ，１７ｃ内に露出する導電膜１３ａ，１３ｃに対し、フッ素含有ガスを用いたエッチングが施された場合、導電膜１３ａ，１３ｃに含まれる銅がスパッタされて、スパッタされた銅が、チャンバーの内壁に付着する虞がある。一般に、フッ素原子は、銅と反応し易い。そのため、チャンバーの内壁に付着した銅に、フッ素含有ガスに含有されるフッ素原子がトラップされて、銅のフッ化物が生成されて、チャンバーの内壁に、銅のフッ化物が付着する虞がある。そのため、チャンバー内に供給されたフッ素原子が消費されて減少するため、エッチングレートが安定しないという懸念がある。 The conductive films 13a and 13c in the first wiring portions 14a and 14c exposed in the wiring grooves 17a and 17c are made of, for example, copper. Therefore, when the conductive films 13a and 13c exposed in the wiring grooves 17a and 17c are etched using a fluorine-containing gas, the copper contained in the conductive films 13a and 13c is sputtered, and the sputtered copper However, there exists a possibility of adhering to the inner wall of a chamber. In general, fluorine atoms easily react with copper. Therefore, there is a possibility that fluorine atoms contained in the fluorine-containing gas are trapped in the copper adhering to the inner wall of the chamber, and copper fluoride is generated, and the copper fluoride adheres to the inner wall of the chamber. Therefore, there is a concern that the etching rate is not stable because fluorine atoms supplied into the chamber are consumed and reduced.
　そこで、本変形例では、第１配線部の形成の後で、且つライナー絶縁膜の形成の前に、第１配線部の表面に、金属を含むキャップ膜を形成する。キャップ膜に含まれる金属として、金属のフッ化物の蒸気圧が、銅のフッ化物の蒸気圧よりも高くなる金属を用いることが好ましい。具体的には例えば、キャップ膜に含まれる金属は、チタン（Ｔｉ）、タングステン（Ｗ）、モリブデン（Ｍｏ）、ハフニウム（Ｈｆ）又はジルコニウム（Ｚｒ）等であることが好ましい。 Therefore, in this modification, a cap film containing metal is formed on the surface of the first wiring part after the formation of the first wiring part and before the formation of the liner insulating film. As the metal contained in the cap film, it is preferable to use a metal in which the vapor pressure of the metal fluoride is higher than the vapor pressure of the copper fluoride. Specifically, for example, the metal contained in the cap film is preferably titanium (Ti), tungsten (W), molybdenum (Mo), hafnium (Hf), zirconium (Zr), or the like.
　このようにすると、配線溝内に、第１配線部ではなく、キャップ膜が露出するため、第１配線部における導電膜に含まれる銅がスパッタされることはない。そのため、エッチングガスとして、例えばフッ素含有ガスを用いた場合であっても、スパッタされた銅に、フッ素含有ガスに含有されるフッ素原子がトラップされることはないため、チャンバーの内壁に、銅のフッ化物が付着することはなく、エッチングレートを安定化させることができる。 In this case, not the first wiring part but the cap film is exposed in the wiring groove, so that copper contained in the conductive film in the first wiring part is not sputtered. Therefore, even when, for example, a fluorine-containing gas is used as the etching gas, the fluorine atoms contained in the fluorine-containing gas are not trapped in the sputtered copper. Fluoride does not adhere and the etching rate can be stabilized.
　さらに、配線溝内に露出するキャップ膜に含まれる金属がスパッタされて、スパッタされた金属に、フッ素含有ガスに含有されるフッ素原子がトラップされて、金属のフッ化物が生成されることがあっても、金属のフッ化物の蒸気圧は、銅のフッ化物の蒸気圧よりも高いため、金属のフッ化物を、チャンバーの内壁に付着させずに、チャンバー外に排気することができるので、エッチングレートを安定化させることができる。 In addition, the metal contained in the cap film exposed in the wiring trench is sputtered, and fluorine atoms contained in the fluorine-containing gas are trapped in the sputtered metal, thereby generating a metal fluoride. However, since the vapor pressure of the metal fluoride is higher than the vapor pressure of the copper fluoride, the metal fluoride can be exhausted out of the chamber without adhering to the inner wall of the chamber. The rate can be stabilized.
　＜第１の実施形態の変形例２＞
　以下に、本発明の第１の実施形態の変形例２に係る半導体装置の製造方法について説明する。 <Modification 2 of the first embodiment>
A method for manufacturing a semiconductor device according to Modification 2 of the first embodiment of the present invention will be described below.
　まず、第１の実施形態における図１(a) に示す工程と同様の工程を行い、図１(a) に示す構成と同様の構成を得る。次に、第１のチャンバー内において、例えばフッ素含有ガスを用いたエッチング（１回目のエッチング）により、層間絶縁膜に、ライナー絶縁膜の上面を露出させる溝を形成する。その後、第１のチャンバーとは異なる第２のチャンバー内において、例えば希ガスを用いたプラズマエッチング（２回目のエッチング）により、溝内に露出するライナー絶縁膜を除去し、ライナー絶縁膜及び層間絶縁膜に、第１配線部の表面を露出させる配線溝を形成する。その後、第１の実施形態における図１(c) ～図３(c) に示す工程と同様の工程を順次行い、本変形例に係る半導体装置を製造することができる。 First, the same process as that shown in FIG. 1A in the first embodiment is performed to obtain the same configuration as that shown in FIG. 1A. Next, in the first chamber, a groove for exposing the upper surface of the liner insulating film is formed in the interlayer insulating film by etching using a fluorine-containing gas (first etching), for example. Thereafter, in a second chamber different from the first chamber, the liner insulating film exposed in the groove is removed by, for example, plasma etching using a rare gas (second etching), and the liner insulating film and the interlayer insulating film are removed. A wiring groove exposing the surface of the first wiring part is formed in the film. Thereafter, steps similar to those shown in FIGS. 1C to 3C in the first embodiment are sequentially performed, and the semiconductor device according to this modification can be manufactured.
　第１の実施形態と本変形例との製造方法上の相違点は、以下に示す点である。 The differences in the manufacturing method between the first embodiment and this modification are as follows.
　第１の実施形態では、図１(b) に示すように、例えば１回のエッチングにより、ライナー絶縁膜１５及び層間絶縁膜１６に、第１配線部１４ａ，１４ｃの表面を露出させる配線溝１７ａ，１７ｃを形成する。 In the first embodiment, as shown in FIG. 1B, a wiring groove 17a that exposes the surfaces of the first wiring portions 14a and 14c to the liner insulating film 15 and the interlayer insulating film 16 by, for example, one etching. , 17c.
　これに対し、本変形例では、１回目のエッチングにより、層間絶縁膜に、ライナー絶縁膜の上面を露出させる溝を形成した後、例えば希ガスを用いた２回目のエッチングにより、溝内に露出するライナー絶縁膜を除去し、ライナー絶縁膜及び層間絶縁膜に、第１配線部の表面を露出させる配線溝を形成する。 On the other hand, in this modified example, a groove that exposes the upper surface of the liner insulating film is formed in the interlayer insulating film by the first etching, and then exposed in the groove by, for example, the second etching using a rare gas. The liner insulating film to be removed is removed, and a wiring groove for exposing the surface of the first wiring portion is formed in the liner insulating film and the interlayer insulating film.
　ここで、第１の実施形態における図１(b) に示す工程において、チャンバー（図示せず）内において、エッチングガスとして、例えばフッ素含有ガスを用いたエッチングにより、配線溝１７ａ，１７ｃを形成した場合、既述の通り、エッチングレートが安定しないという懸念がある。 Here, in the step shown in FIG. 1B in the first embodiment, the wiring grooves 17a and 17c are formed in the chamber (not shown) by etching using, for example, a fluorine-containing gas as an etching gas. In this case, as described above, there is a concern that the etching rate is not stable.
　そこで、本変形例では、第１のチャンバー内において、１回目のエッチングにより、層間絶縁膜に、ライナー絶縁膜の上面を露出させる溝を形成する。その後、第２のチャンバー内において、例えば希ガスを用いた２回目のエッチングにより、溝内に露出するライナー絶縁膜を除去し、ライナー絶縁膜及び層間絶縁膜に、第１配線部の表面を露出させる配線溝を形成する。 Therefore, in this modification, a groove exposing the upper surface of the liner insulating film is formed in the interlayer insulating film by the first etching in the first chamber. Thereafter, in the second chamber, for example, the liner insulating film exposed in the trench is removed by a second etching using a rare gas, and the surface of the first wiring portion is exposed in the liner insulating film and the interlayer insulating film. A wiring groove to be formed is formed.
　このようにすると、２回目のエッチング時に、配線溝内に露出する第１配線部における導電膜に含まれる銅がスパッタされることがあっても、一般に、希ガスは、銅と反応することがないため、スパッタされた銅に、希ガスがトラップされることはないので、エッチングレートを安定化させることができる。 In this way, even when copper contained in the conductive film in the first wiring portion exposed in the wiring groove is sputtered during the second etching, the rare gas generally reacts with copper. Therefore, the rare gas is not trapped by the sputtered copper, so that the etching rate can be stabilized.
　さらに、１回目のエッチング時に、溝内に、第１配線部ではなく、ライナー絶縁膜が露出するため、第１配線部における導電膜に含まれる銅がスパッタされることはない。そのため、エッチングガスとして、例えばフッ素含有ガスを用いた場合であっても、スパッタされた銅に、フッ素含有ガスに含まれるフッ素原子がトラップされることはないため、第１のチャンバーの内壁に、銅のフッ化物が付着することはなく、エッチングレートを安定化させることができる。 Furthermore, since the liner insulating film, not the first wiring portion, is exposed in the groove during the first etching, copper contained in the conductive film in the first wiring portion is not sputtered. Therefore, even when, for example, a fluorine-containing gas is used as an etching gas, fluorine atoms contained in the fluorine-containing gas are not trapped in the sputtered copper, and therefore, on the inner wall of the first chamber, Copper fluoride does not adhere, and the etching rate can be stabilized.
　なお、本変形例では、１回目のエッチングにより、層間絶縁膜に、ライナー絶縁膜の上面を露出させる溝を形成した後、２回目のエッチングにより、溝内に露出するライナー絶縁膜を除去し、ライナー絶縁膜及び層間絶縁膜に、第１配線部の表面を露出させる配線溝を形成する場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。 In this modification, a groove that exposes the upper surface of the liner insulating film is formed in the interlayer insulating film by the first etching, and then the liner insulating film exposed in the groove is removed by the second etching, Although the case where the wiring groove for exposing the surface of the first wiring portion is formed in the liner insulating film and the interlayer insulating film has been described as a specific example, the present invention is not limited to this.
　例えば、１回目のエッチングにより、層間絶縁膜に、溝を形成した後、２回目のエッチングにより、溝内に露出する層間絶縁膜及びライナー絶縁膜を除去し、ライナー絶縁膜及び層間絶縁膜に、第１配線部の表面を露出させる配線溝を形成してもよい。即ち、１回目のエッチングにより形成される溝は、第１配線部の表面が露出されることがないように形成されればよい。 For example, after forming a groove in the interlayer insulating film by the first etching, the interlayer insulating film and the liner insulating film exposed in the groove are removed by the second etching, and the liner insulating film and the interlayer insulating film are A wiring groove that exposes the surface of the first wiring portion may be formed. That is, the groove formed by the first etching may be formed so that the surface of the first wiring portion is not exposed.
　＜第１の実施形態の変形例３＞
　以下に、本発明の第１の実施形態の変形例３に係る半導体装置の製造方法について、図１２(a) ～(d) を参照しながら説明する。図１２(a) ～(d) は、本発明の第１の実施形態の変形例３に係る半導体装置の製造方法を工程順に示す要部工程断面図である。図１２(a) ～(d) において、第１の実施形態における構成要素と同一の構成要素には、図１(a) ～図３(c) に示す符号と同一の符号を付す。 <Modification 3 of the first embodiment>
A method for manufacturing a semiconductor device according to Modification 3 of the first embodiment of the present invention will be described below with reference to FIGS. 12 (a) to 12 (d). 12 (a) to 12 (d) are cross-sectional views of relevant steps showing a method of manufacturing a semiconductor device according to Modification 3 of the first embodiment of the present invention in the order of steps. 12 (a) to (d), the same reference numerals as those shown in FIGS. 1 (a) to 3 (c) are assigned to the same components as those in the first embodiment.
　まず、第１の実施形態における図１(a) に示す工程と同様の工程を行い、図１(a) に示す構成と同様の構成を得る。 First, a process similar to the process shown in FIG. 1A in the first embodiment is performed to obtain the same configuration as that shown in FIG.
　次に、図１２(a) に示すように、第１のチャンバー（図示せず）内において、例えばフッ素含有ガスを用いたエッチング（１回目のエッチング）により、層間絶縁膜１６に、ライナー絶縁膜１５の上面を露出させる溝７０ａ，７０ｃを形成する。 Next, as shown in FIG. 12A, in the first chamber (not shown), the liner insulating film 16 is formed on the interlayer insulating film 16 by etching using a fluorine-containing gas (first etching), for example. Grooves 70a and 70c that expose the upper surface of 15 are formed.
　その後、第１のチャンバーとは異なる第２のチャンバー（図示せず）内において、例えばスパッタ法により、層間絶縁膜１６上、並びに溝７０ａ，７０ｃの底面及び側壁に、側壁バリアメタル膜７１を形成する。 Thereafter, in a second chamber (not shown) different from the first chamber, a sidewall barrier metal film 71 is formed on the interlayer insulating film 16 and on the bottom and sidewalls of the grooves 70a and 70c by, for example, sputtering. To do.
　次に、図１２(b) に示すように、第１，第２のチャンバーとは異なる第３のチャンバー（図示せず）内において、例えば希ガスを用いたプラズマエッチング（２回目のエッチング）により、側壁バリアメタル膜７１のうち溝７０ａ，７０ｃの底面に形成された部分を除去し、ライナー絶縁膜１５の上面を露出させる溝を形成し、引き続き、溝内に露出するライナー絶縁膜１５を除去し、第１配線部１４ａ，１４ｃの表面を露出させる配線溝１７ａ，１７ｃを形成する。配線溝１７ａ，１７ｃは、図１２(b) に示すように、その側壁が、側壁バリアメタル膜７１で覆われている。 Next, as shown in FIG. 12B, in a third chamber (not shown) different from the first and second chambers, for example, by plasma etching (second etching) using a rare gas. Then, a portion of the sidewall barrier metal film 71 formed on the bottom surfaces of the grooves 70a and 70c is removed to form a groove exposing the upper surface of the liner insulating film 15, and then the liner insulating film 15 exposed in the groove is removed. Then, wiring grooves 17a and 17c that expose the surfaces of the first wiring portions 14a and 14c are formed. The side walls of the wiring trenches 17 a and 17 c are covered with a side wall barrier metal film 71 as shown in FIG.
　次に、図１２(c) に示すように、スパッタ法により、側壁バリアメタル膜７１上、並びに配線溝１７ａ，１７ｃの底面及び側壁に、バリアメタル膜７２を形成する。その後、逆スパッタ法により、バリアメタル膜７２のうち配線溝１７ａ，１７ｃの底面に形成された部分を除去し、第１配線部１４ａ，１４ｃの上面を露出させる。その後、スパッタ法により、配線溝１７ａ，１７ｃ内に露出する第１配線部１４ａ，１４ｃ、及びバリアメタル膜７２上に、例えば銅（Ｃｕ）等からなるシード膜を形成する。その後、めっき法により、シード膜上に、例えば銅（Ｃｕ）等からなるめっき膜を形成する。このようにして、配線溝１７ａ，１７ｃ内に、バリアメタル膜７２を介して、導電膜１９を埋め込む。 Next, as shown in FIG. 12C, a barrier metal film 72 is formed on the side wall barrier metal film 71 and on the bottom and side walls of the wiring grooves 17a and 17c by sputtering. Thereafter, by reverse sputtering, portions of the barrier metal film 72 formed on the bottom surfaces of the wiring grooves 17a and 17c are removed, and the upper surfaces of the first wiring portions 14a and 14c are exposed. Thereafter, a seed film made of, for example, copper (Cu) is formed on the first wiring portions 14a and 14c and the barrier metal film 72 exposed in the wiring grooves 17a and 17c by sputtering. Thereafter, a plating film made of, for example, copper (Cu) or the like is formed on the seed film by plating. In this way, the conductive film 19 is embedded in the wiring grooves 17a and 17c via the barrier metal film 72.
　次に、図１２(d) に示すように、ＣＭＰ法により、導電膜１９及びバリアメタル膜７２のうち、配線溝１７ａ，１７ｃ外に形成された部分を除去し、引き続き、側壁バリアメタル膜７１のうち、層間絶縁膜１６上に形成された部分を除去する。 Next, as shown in FIG. 12D, the portions of the conductive film 19 and the barrier metal film 72 that are formed outside the wiring trenches 17a and 17c are removed by CMP, and the sidewall barrier metal film 71 is subsequently removed. Of these, the portion formed on the interlayer insulating film 16 is removed.
　このようにして、電源配線領域Ａのライナー絶縁膜１５及び層間絶縁膜１６に、バリアメタル膜７２ａと、導電膜１９ａとからなる第２配線部２０ａを形成し、低抵抗配線領域Ｃのライナー絶縁膜１５及び層間絶縁膜１６に、バリアメタル膜７２ｃと、導電膜１９ｃとからなる第２配線部２０ｃを形成する。第２配線部２０ａ，２０ｃは、図１２(d) に示すように、その側面が、側壁バリアメタル膜７１ａ，７１ｃで覆われている。 In this way, the second wiring portion 20a composed of the barrier metal film 72a and the conductive film 19a is formed in the liner insulating film 15 and the interlayer insulating film 16 in the power wiring region A, and the liner insulation in the low resistance wiring region C is formed. On the film 15 and the interlayer insulating film 16, a second wiring portion 20c including a barrier metal film 72c and a conductive film 19c is formed. As shown in FIG. 12D, the side surfaces of the second wiring portions 20a and 20c are covered with side wall barrier metal films 71a and 71c.
　その後、第１の実施形態における図２(b) ～図３(c) に示す工程と同様の工程を順次行い、本変形例に係る半導体装置を製造することができる。 Thereafter, the same processes as those shown in FIGS. 2B to 3C in the first embodiment are sequentially performed, and the semiconductor device according to this modification can be manufactured.
　第１の実施形態と本変形例との製造方法上の相違点は、以下に示す点である。 The differences in the manufacturing method between the first embodiment and this modification are as follows.
　第１の実施形態では、図１(b) に示すように、例えば１回のエッチングにより、ライナー絶縁膜１５及び層間絶縁膜１６に、配線溝１７ａ，１７ｃを形成する。その後、図１(c) に示すように、層間絶縁膜１６上、並びに配線溝１７ａ，１７ｃの底面及び側壁に、バリアメタル膜１８を形成する。 In the first embodiment, as shown in FIG. 1B, wiring grooves 17a and 17c are formed in the liner insulating film 15 and the interlayer insulating film 16, for example, by one etching. Thereafter, as shown in FIG. 1C, a barrier metal film 18 is formed on the interlayer insulating film 16 and on the bottom and side walls of the wiring grooves 17a and 17c.
　これに対し、本変形例では、図１２(a) に示すように、１回目のエッチングにより、層間絶縁膜１６に、ライナー絶縁膜１５の上面を露出させる溝７０ａ，７０ｃを形成する。その後、層間絶縁膜１６上、並びに溝７０ａ，７０ｃの底面及び側壁に、側壁バリアメタル膜７１を形成する。その後、図１２(b) に示すように、例えば希ガスを用いた２回目のエッチングにより、ライナー絶縁膜１５及び層間絶縁膜１６に、側壁が側壁バリアメタル膜７１で覆われた配線溝１７ａ，１７ｃを形成する。その後、図１２(c) に示すように、側壁バリアメタル膜７１上、並びに配線溝１７ａ，１７ｃの底面及び側壁に、バリアメタル膜７２を形成する。 On the other hand, in this modification, as shown in FIG. 12A, grooves 70a and 70c for exposing the upper surface of the liner insulating film 15 are formed in the interlayer insulating film 16 by the first etching. Thereafter, a sidewall barrier metal film 71 is formed on the interlayer insulating film 16 and on the bottom and sidewalls of the trenches 70a and 70c. Thereafter, as shown in FIG. 12B, the wiring trenches 17a whose side walls are covered with the side wall barrier metal film 71 are formed on the liner insulating film 15 and the interlayer insulating film 16 by, for example, second etching using a rare gas. 17c is formed. Thereafter, as shown in FIG. 12C, a barrier metal film 72 is formed on the side wall barrier metal film 71 and on the bottom and side walls of the wiring grooves 17a and 17c.
　第１の実施形態と本変形例との構成上の相違点は、次に示す点である。本変形例に係る半導体装置は、第１の実施形態と同様の構成要素に加えて、第２配線部２０ａ，２０ｃと層間絶縁膜１６との間に形成され、第２配線部２０ａ，２０ｃの側面を覆う側壁バリアメタル膜７１ａ，７１ｃをさらに備えている。第２配線部２０ａ，２０ｃにおけるバリアメタル膜７２ａ，７２ｃは、側壁バリアメタル膜７１ａ，７１ｃと接続している。 The differences in configuration between the first embodiment and this modification are as follows. The semiconductor device according to the present modification is formed between the second wiring portions 20a and 20c and the interlayer insulating film 16 in addition to the same components as those in the first embodiment, and the second wiring portions 20a and 20c Side wall barrier metal films 71a and 71c are further provided to cover the side surfaces. The barrier metal films 72a and 72c in the second wiring portions 20a and 20c are connected to the side wall barrier metal films 71a and 71c.
　ここで、第１の実施形態における図１(b) に示す工程において、チャンバー（図示せず）内において、エッチングガスとして、例えばフッ素含有ガスを用いたエッチングにより、配線溝１７ａ，１７ｃを形成した場合、既述の通り、エッチングレートが安定しないという懸念がある。 Here, in the step shown in FIG. 1B in the first embodiment, the wiring grooves 17a and 17c are formed in the chamber (not shown) by etching using, for example, a fluorine-containing gas as an etching gas. In this case, as described above, there is a concern that the etching rate is not stable.
　そこで、本変形例では、図１２(a) に示すように、第１のチャンバー内において、１回目のエッチングにより、ライナー絶縁膜１５の上面を露出させる溝７０ａ，７０ｃを形成する。その後、図１２(b) に示すように、第３のチャンバー内において、例えば希ガスを用いた２回目のエッチングにより、第１配線部１４ａ，１４ｃの表面を露出させる配線溝１７ａ，１７ｃを形成する。 Therefore, in this modification, as shown in FIG. 12A, trenches 70a and 70c that expose the upper surface of the liner insulating film 15 are formed by the first etching in the first chamber. Thereafter, as shown in FIG. 12B, wiring grooves 17a and 17c that expose the surfaces of the first wiring portions 14a and 14c are formed in the third chamber by, for example, second etching using a rare gas. To do.
　このようにすると、２回目のエッチング時に、配線溝１７ａ，１７ｃ内に露出する第１配線部１４ａ，１４ｃにおける導電膜１３ａ，１３ｃに含まれる銅がスパッタされることがあっても、一般に、希ガスは、銅と反応することがないため、スパッタされた銅に、希ガスがトラップされることはないので、エッチングレートを安定化させることができる。 In this manner, even when copper contained in the conductive films 13a and 13c in the first wiring portions 14a and 14c exposed in the wiring grooves 17a and 17c is sputtered at the time of the second etching, generally, it is rare. Since the gas does not react with copper, no rare gas is trapped in the sputtered copper, so that the etching rate can be stabilized.
　さらに、１回目のエッチング時に、溝７０ａ，７０ｃ内に、第１配線部１４ａ，１４ｃでなはく、ライナー絶縁膜１５が露出するため、第１配線部１４ａ，１４ｃにおける導電膜１３ａ，１３ｃに含まれる銅がスパッタされることはない。そのため、エッチングガスとして、例えばフッ素含有ガスを用いた場合であっても、スパッタされた銅に、フッ素含有ガスに含まれるフッ素原子がトラップされることはないため、第１のチャンバーの内壁に、銅のフッ化物が付着することはなく、エッチングレートを安定化させることができる。 Furthermore, since the liner insulating film 15 is exposed in the grooves 70a and 70c, not in the first wiring portions 14a and 14c, in the first etching, the conductive films 13a and 13c in the first wiring portions 14a and 14c are exposed. The contained copper is not sputtered. Therefore, even when, for example, a fluorine-containing gas is used as an etching gas, fluorine atoms contained in the fluorine-containing gas are not trapped in the sputtered copper, and therefore, on the inner wall of the first chamber, Copper fluoride does not adhere, and the etching rate can be stabilized.
　なお、本変形例では、図１２(a) に示すように、溝７０ａ，７０ｃを形成した後、第２のチャンバー内において、例えばスパッタ法により、側壁バリアメタル膜７１を形成し、その後、図１２(b) に示すように、第３のチャンバー内において、例えば希ガスを用いたプラズマエッチングにより、第１配線部１４ａ，１４ｃの表面を露出させる配線溝１７ａ，１７ｃを形成する場合（言い換えれば、スパッタ法による側壁バリアメタル膜７１の形成が行われる第２のチャンバーとは異なる第３のチャンバー内において、希ガスを用いたプラズマエッチングにより、配線溝１７ａ，１７ｃを形成する場合）を具体例に挙げて説明したが、本発明はこれに限定されるものではない。 In this modified example, as shown in FIG. 12A, after forming the grooves 70a and 70c, the sidewall barrier metal film 71 is formed in the second chamber by, for example, sputtering, and thereafter, When the wiring grooves 17a and 17c that expose the surfaces of the first wiring portions 14a and 14c are formed in the third chamber by, for example, plasma etching using a rare gas, as shown in FIG. Specific example of the case where the wiring grooves 17a and 17c are formed by plasma etching using a rare gas in a third chamber different from the second chamber in which the sidewall barrier metal film 71 is formed by sputtering. However, the present invention is not limited to this.
　例えば、図１２(a) に示す工程と同様に、溝を形成した後、第２のチャンバー内において、例えばスパッタ法により、側壁バリアメタル膜を形成し、その後、第３のチャンバー内ではなく、第２のチャンバー内において、例えば逆スパッタ法により、第１配線部の表面を露出させる配線溝を形成してもよい。言い換えれば、スパッタ法による側壁バリアメタル膜の形成が行われるチャンバーと同一のチャンバー内において、希ガスを用いたプラズマエッチングではなく、逆スパッタ法により、配線溝を形成してもよい。 For example, as in the step shown in FIG. 12A, after forming the groove, a sidewall barrier metal film is formed in the second chamber by, for example, sputtering, and then not in the third chamber. In the second chamber, a wiring groove that exposes the surface of the first wiring portion may be formed by, for example, reverse sputtering. In other words, in the same chamber as the chamber in which the sidewall barrier metal film is formed by sputtering, the wiring trench may be formed by reverse sputtering instead of plasma etching using a rare gas.
　本発明は、配線にボイドが発生することを防止できるため、配線を備えた半導体装置に有用である。 Since the present invention can prevent the generation of voids in the wiring, it is useful for a semiconductor device provided with the wiring.
　Ａ　電源配線領域
　Ｂ　信号配線領域
　Ｃ　低抵抗配線領域
　１０　層間絶縁膜
　１１ａ，１１ｂ，１１ｃ　配線溝
　１２ａ，１２ｂ，１２ｃ　バリアメタル膜
　１３ａ，１３ｂ，１３ｃ　導電膜
　１４ａ，１４ｂ，１４ｃ　第１配線部
　１４Ｂ　信号配線領域の配線
　１５　ライナー絶縁膜
　１６　層間絶縁膜
　１７ａ，１７ｃ　配線溝
　１８，１８ａ，１８ｂ，１８ｃ　バリアメタル膜
　１９，１９ａ，１９ｂ，１９ｃ　導電膜
　２０ａ，２０ｃ　第２配線部
　２０ｂ　第１ビア部
　２０Ｃ　低抵抗配線領域の配線
　２１　ライナー絶縁膜
　２２　層間絶縁膜
　２３ａ　配線溝
　２４，２４ａ，２４ｂ，２４ｃ　バリアメタル膜
　２５，２５ａ，２５ｂ，２５ｃ　導電膜
　２６ａ　第３配線部
　２６ｂ　第２ビア部
　２６ｃ　第１ビア部
　２６Ａ　電源配線領域の配線
　２６Ｖｂ　信号配線領域のビア
　２６Ｖｃ　低抵抗配線領域のビア
　２７　ライナー絶縁膜
　２８　層間絶縁膜
　２９ａｘ，２９ｂｘ，２９ｃｘ　バリアメタル膜
　２９ａｙ，２９ｂｙ，２９ｃｙ　バリアメタル膜
　３０ａｘ，３０ｂｘ，３０ｃｘ　導電膜
　３０ａｙ，３０ｂｙ，３０ｃｙ　導電膜
　３１ａｘ，３１ｂｘ，３１ｃｘ　ビア
　３１ａｙ，３１ｂｙ，３１ｃｙ　第１配線部
　３１Ｂ　信号配線領域の配線
　３２　ライナー絶縁膜
　３３　層間絶縁膜
　３４ａ，３４ｃ　バリアメタル膜
　３５ａ，３５ｃ　導電膜
　３６ａ，３６ｃ　第２配線部
　３６Ｃ　低抵抗配線領域の配線
　３７　ライナー絶縁膜
　３８　層間絶縁膜
　３９ａ　バリアメタル膜
　４０ａ　導電膜
　４１ａ　第３配線部
　４１Ａ　電源配線領域の配線
　５０　層間絶縁膜
　５２　バリアメタル膜
　５３　導電膜
　５４　第１配線部
　５５　ライナー絶縁膜
　５６　層間絶縁膜
　５８　バリアメタル膜
　５９　導電膜
　６０　第２配線部
　６１　ライナー絶縁膜
　６２　層間絶縁膜
　６３　配線溝
　６４ｚ　バリアメタル膜
　６５ｚ　導電膜
　７０ａ，７０ｃ　溝
　７１，７１ａ，７１ｃ　側壁バリアメタル膜
　７２，７２ａ，７２ｃ　バリアメタル膜
　１０４ａ，１０４１，１０４ｃ　配線
　２５０　層間絶縁膜
　２５１　配線溝
　２５２ｚ　バリアメタル膜
　２５３ｚ　導電膜 A power supply wiring region B signal wiring region C low resistance wiring region 10 interlayer insulating film 11a, 11b, 11c wiring groove 12a, 12b, 12c barrier metal film 13a, 13b, 13c conductive film 14a, 14b, 14c first wiring part 14B signal Wiring in wiring region 15 Liner insulating film 16 Interlayer insulating film 17a, 17c Wiring groove 18, 18a, 18b, 18c Barrier metal film 19, 19a, 19b, 19c Conductive film 20a, 20c Second wiring part 20b First via part 20C Low Resistance wiring region wiring 21 liner insulating film 22 interlayer insulating film 23a wiring groove 24, 24a, 24b, 24c barrier metal film 25, 25a, 25b, 25c conductive film 26a third wiring part 26b second via part 26c first via part 26A Power supply wiring area wiring 26Vb Signal wiring area via 26Vc Low resistance Anti-wiring region via 27 Liner insulating film 28 Interlayer insulating film 29ax, 29bx, 29cx Barrier metal film 29ay, 29by, 29cy Barrier metal film 30ax, 30bx, 30cx Conductive film 30ay, 30by, 30cy Conductive film 31ax, 31bx, 31cx Via 31ay , 31by, 31cy First wiring portion 31B Signal wiring region wiring 32 Liner insulating film 33 Interlayer insulating film 34a, 34c Barrier metal film 35a, 35c Conductive film 36a, 36c Second wiring portion 36C Low resistance wiring region wiring 37 Liner insulation Film 38 Interlayer insulating film 39a Barrier metal film 40a Conductive film 41a Third wiring portion 41A Power wiring region wiring 50 Interlayer insulating film 52 Barrier metal film 53 Conductive film 54 First wiring portion 55 Liner insulating film 56 Interlayer insulating film 58 Barrier film Film 59 conductive film 60 second wiring part 61 liner insulating film 62 interlayer insulating film 63 wiring groove 64z barrier metal film 65z conductive film 70a, 70c groove 71, 71a, 71c sidewall barrier metal film 72, 72a, 72c barrier metal film 104a , 1041, 104c wiring 250 interlayer insulating film 251 wiring trench 252z barrier metal film 253z conductive film

Claims (22)

  1. 　半導体基板上に形成された第１の層間絶縁膜と、
    　前記第１の層間絶縁膜に形成された第１の第１配線部と、
    　前記第１の層間絶縁膜上に形成された第２の層間絶縁膜と、
    　前記第２の層間絶縁膜に形成され、前記第１の第１配線部と接続する第１の第２配線部とを備え、
    　前記第１の第１配線部、及び前記第１の第２配線部からなる第１の配線が構成されていることを特徴とする半導体装置。     A first interlayer insulating film formed on the semiconductor substrate;
    A first first wiring portion formed in the first interlayer insulating film;
    A second interlayer insulating film formed on the first interlayer insulating film;
    A first second wiring portion formed on the second interlayer insulating film and connected to the first first wiring portion;
    A semiconductor device comprising a first wiring composed of the first first wiring portion and the first second wiring portion.
  2. 　前記第１の層間絶縁膜に形成された第２の第１配線部からなる第２の配線をさらに備え、
    　前記第２の第１配線部の高さは、前記第１の第１配線部の高さと略同一であり、
    　前記第２の配線の配線高さは、前記第１の配線の配線高さよりも低いことを特徴とする請求項１に記載の半導体装置。     A second wiring comprising a second first wiring portion formed in the first interlayer insulating film;
    The height of the second first wiring portion is substantially the same as the height of the first first wiring portion,
    The semiconductor device according to claim 1, wherein a wiring height of the second wiring is lower than a wiring height of the first wiring.
  3. 　前記第２の配線の配線幅は、前記第１の配線の配線幅と略同一であり、
    　前記第２の配線の抵抗は、前記第１の配線の抵抗よりも高いことを特徴とする請求項２に記載の半導体装置。     The wiring width of the second wiring is substantially the same as the wiring width of the first wiring,
    The semiconductor device according to claim 2, wherein a resistance of the second wiring is higher than a resistance of the first wiring.
  4. 　前記第２の層間絶縁膜に形成され、前記第２の第１配線部と接続する第２のビア部をさらに備え、
    　前記第２のビア部の高さは、前記第１の第２配線部の高さと略同一であることを特徴とする請求項２又は３に記載の半導体装置。     A second via portion formed in the second interlayer insulating film and connected to the second first wiring portion;
    4. The semiconductor device according to claim 2, wherein a height of the second via portion is substantially the same as a height of the first second wiring portion. 5.
  5. 　前記第１の第１配線部は、前記第１の層間絶縁膜に設けられた配線溝の底面及び側壁に形成されたバリアメタル膜と、該配線溝内に該バリアメタル膜を介して埋め込まれた導電膜とからなり、
    　前記第１の第２配線部は、前記第２の層間絶縁膜に設けられた配線溝の側壁に形成されたバリアメタル膜と、該配線溝内に該バリアメタル膜を介して埋め込まれた導電膜とからなり、
    　前記第１の第２配線部を構成する導電膜は、前記第１の第１配線部を構成する導電膜に接して形成されていることを特徴とする請求項１～４のうちいずれか１項に記載の半導体装置。     The first first wiring portion is buried in a bottom surface and a side wall of a wiring groove provided in the first interlayer insulating film, and embedded in the wiring groove via the barrier metal film. A conductive film,
    The first second wiring portion includes a barrier metal film formed on a side wall of a wiring groove provided in the second interlayer insulating film, and a conductive material buried in the wiring groove via the barrier metal film. Consisting of a membrane,
    The conductive film constituting the first second wiring portion is formed in contact with the conductive film constituting the first first wiring portion. The semiconductor device according to item.
  6. 　前記第１の第２配線部の断面形状は、その下面幅がその上面幅よりも小さい形状であることを特徴とする請求項１～５のうちいずれか１項に記載の半導体装置。 6. The semiconductor device according to claim 1, wherein a cross-sectional shape of the first second wiring portion has a lower surface width smaller than an upper surface width.
  7. 　前記第２の層間絶縁膜上に形成された第３の層間絶縁膜と、
    　前記第３の層間絶縁膜に形成され、前記第１の第２配線部と接続するビアと、
    　前記第３の層間絶縁膜に形成され、前記ビアと接続する第３の第１配線部と、
    　前記第３の層間絶縁膜上に形成された第４の層間絶縁膜と、
    　前記第４の層間絶縁膜に形成され、前記第３の第１配線部と接続する第３の第２配線部とをさらに備え、
    　前記第３の第１配線部、及び前記第３の第２配線部からなる第３の配線が構成されていることを特徴とする請求項１～６のうちいずれか１項に記載の半導体装置。     A third interlayer insulating film formed on the second interlayer insulating film;
    A via formed in the third interlayer insulating film and connected to the first second wiring portion;
    A third first wiring portion formed in the third interlayer insulating film and connected to the via;
    A fourth interlayer insulating film formed on the third interlayer insulating film;
    A third second wiring portion formed on the fourth interlayer insulating film and connected to the third first wiring portion;
    The semiconductor device according to any one of claims 1 to 6, wherein a third wiring including the third first wiring portion and the third second wiring portion is configured. .
  8. 　前記第１の層間絶縁膜、及び前記第２の層間絶縁膜は、ＳｉＯＣ膜であることを特徴とする請求項１～７のうちいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 7, wherein the first interlayer insulating film and the second interlayer insulating film are SiOC films.
  9. 　前記第１の配線のアスペクト比は、０．５以上１．０以下であることを特徴とする請求項１～８のうちいずれか１項に記載の半導体装置。 9. The semiconductor device according to claim 1, wherein an aspect ratio of the first wiring is 0.5 or more and 1.0 or less.
  10. 　前記第１の配線の配線幅は、７０ｎｍ以下であることを特徴とする請求項１～９のうちいずれか１項に記載の半導体装置。 10. The semiconductor device according to claim 1, wherein a wiring width of the first wiring is 70 nm or less.
  11. 　前記第１の第１配線部と前記第１の第２配線部との間に形成され、前記第１の第１配線部の表面を覆うキャップ膜をさらに備え、
    　前記キャップ膜は、金属を含み、
    　前記第１の第１配線部は、前記キャップ膜を介して、前記第１の第２配線部と電気的に接続していることを特徴とする請求項１～１０のうちいずれか１項に記載の半導体装置。     A cap film formed between the first first wiring portion and the first second wiring portion and covering a surface of the first first wiring portion;
    The cap film includes a metal,
    The first first wiring part is electrically connected to the first second wiring part via the cap film, according to any one of claims 1 to 10. The semiconductor device described.
  12. 　前記金属は、Ｔｉ、Ｗ、Ｍｏ、Ｈｆ又はＺｒであることを特徴とする請求項１１に記載の半導体装置。 12. The semiconductor device according to claim 11, wherein the metal is Ti, W, Mo, Hf, or Zr.
  13. 　半導体基板上に、第１の層間絶縁膜を形成する工程（ａ）と、
    　前記第１の層間絶縁膜に、第１の第１配線部を形成する工程（ｂ）と、
    　前記工程（ｂ）の後に、前記第１の層間絶縁膜上に、第２の層間絶縁膜を形成する工程（ｃ）と、
    　前記第２の層間絶縁膜に、前記第１の第１配線部と接続する第１の第２配線部を形成する工程（ｄ）とを備え、
    　前記工程（ｄ）において、前記第１の第１配線部、及び前記第１の第２配線部からなる第１の配線が構成されることを特徴とする半導体装置の製造方法。     A step (a) of forming a first interlayer insulating film on the semiconductor substrate;
    Forming a first first wiring portion in the first interlayer insulating film (b);
    A step (c) of forming a second interlayer insulating film on the first interlayer insulating film after the step (b);
    Forming a first second wiring portion connected to the first first wiring portion on the second interlayer insulating film (d),
    In the step (d), a first wiring composed of the first first wiring portion and the first second wiring portion is configured.
  14. 　前記工程（ｂ）は、前記第１の層間絶縁膜に、第２の第１配線部を形成する工程をさらに含み、
    　前記工程（ｂ）において、前記第２の第１配線部からなる第２の配線が構成されることを特徴とする請求項１３に記載の半導体装置の製造方法。     The step (b) further includes a step of forming a second first wiring portion in the first interlayer insulating film,
    14. The method of manufacturing a semiconductor device according to claim 13, wherein in the step (b), a second wiring composed of the second first wiring portion is formed.
  15. 　前記工程（ｄ）は、前記第２の層間絶縁膜に、前記第２の第１配線部と接続する第２のビア部を形成する工程をさらに含むことを特徴とする請求項１４に記載の半導体装置の製造方法。 The step (d) further includes a step of forming a second via portion connected to the second first wiring portion in the second interlayer insulating film. A method for manufacturing a semiconductor device.
  16. 　前記工程（ｂ）は、
    　　前記第１の層間絶縁膜に第１配線溝を形成する工程（ｂ１）と、
    　　前記第１配線溝の底面及び側壁に第１バリアメタル膜を形成する工程（ｂ２）と、
    　　前記工程（ｂ２）の後に、前記第１配線溝内に第１導電膜を埋め込んで、前記第１配線溝内に、前記第１バリアメタル膜を介して前記第１導電膜が埋め込まれてなる前記第１の第１配線部を形成する工程（ｂ３）とを含み、
    　前記工程（ｄ）は、
    　　前記第２の層間絶縁膜に第２配線溝を形成する工程（ｄ１）と、
    　　前記第２配線溝の側壁に第２バリアメタル膜を形成する工程（ｄ２）と、
    　　前記工程（ｄ２）の後に、前記第２配線溝内に第２導電膜を埋め込んで、前記第２配線溝内に、前記第２バリアメタル膜を介して前記第２導電膜が埋め込まれてなる前記第１の第２配線部を形成する工程（ｄ３）とを含み、
    　前記工程（ｄ３）において、前記第２導電膜は、前記第１導電膜に接して形成されることを特徴とする請求項１３～１５のうちいずれか１項に記載の半導体装置の製造方法。     The step (b)
    Forming a first wiring groove in the first interlayer insulating film (b1);
    A step (b2) of forming a first barrier metal film on the bottom and side walls of the first wiring trench;
    After the step (b2), a first conductive film is embedded in the first wiring groove, and the first conductive film is embedded in the first wiring groove via the first barrier metal film. Forming the first first wiring portion (b3),
    The step (d)
    Forming a second wiring trench in the second interlayer insulating film (d1);
    Forming a second barrier metal film on the side wall of the second wiring trench (d2);
    After the step (d2), a second conductive film is embedded in the second wiring groove, and the second conductive film is embedded in the second wiring groove via the second barrier metal film. Forming the first second wiring portion (d3),
    The method of manufacturing a semiconductor device according to any one of claims 13 to 15, wherein, in the step (d3), the second conductive film is formed in contact with the first conductive film.
  17. 　前記工程（ｂ）の後で、且つ前記工程（ｃ）の前に、前記第１の第１配線部の表面に、金属を含むキャップ膜を形成する工程（ｅ）をさらに備え、
    　前記工程（ｄ１）は、エッチングガスとしてフッ素を含有するフッ素含有ガスを用いたエッチングにより、前記キャップ膜の表面を露出させる前記第２配線溝を形成する工程であることを特徴とする請求項１６に記載の半導体装置の製造方法。     A step (e) of forming a cap film containing a metal on the surface of the first first wiring portion after the step (b) and before the step (c);
    The step (d1) is a step of forming the second wiring groove exposing the surface of the cap film by etching using a fluorine-containing gas containing fluorine as an etching gas. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.
  18. 　前記金属は、Ｔｉ、Ｗ、Ｍｏ、Ｈｆ又はＺｒであることを特徴とする請求項１７に記載の半導体装置の製造方法。　 18. The method of manufacturing a semiconductor device according to claim 17, wherein the metal is Ti, W, Mo, Hf, or Zr. *
  19. 　前記工程（ｄ１）は、
    　エッチングガスとしてフッ素を含有するフッ素含有ガスを用いた第１のエッチングにより、前記第２の層間絶縁膜に、溝を形成する工程と、
    　エッチングガスとして希ガスを用いた第２のエッチングにより、前記溝内に露出する前記第２の層間絶縁膜を除去し、前記第２の層間絶縁膜に、前記第１の第１配線部の表面を露出させる前記第２配線溝を形成する工程とを含み、
    　前記溝を形成する工程において、前記溝内に、前記第１の第１配線部の表面が露出されることがないように、前記溝は形成されることを特徴とする請求項１６に記載の半導体装置の製造方法。     The step (d1)
    Forming a groove in the second interlayer insulating film by first etching using a fluorine-containing gas containing fluorine as an etching gas;
    The second interlayer insulating film exposed in the trench is removed by second etching using a rare gas as an etching gas, and the surface of the first first wiring portion is formed on the second interlayer insulating film. Forming the second wiring groove to expose
    The groove is formed so that the surface of the first first wiring part is not exposed in the groove in the step of forming the groove. A method for manufacturing a semiconductor device.
  20. 　前記工程（ｄ２）は、前記第２配線溝の底面及び側壁に前記第２バリアメタル膜を形成した後、前記第２バリアメタル膜のうち前記第２配線溝の底面に形成された部分を除去する工程であることを特徴とする請求項１６に記載の半導体装置の製造方法。 In the step (d2), after the second barrier metal film is formed on the bottom and side walls of the second wiring groove, a portion of the second barrier metal film formed on the bottom of the second wiring groove is removed. The method of manufacturing a semiconductor device according to claim 16, wherein
  21. 　前記工程（ｄ）の後に、前記第２の層間絶縁膜上に第３の層間絶縁膜を形成する工程（ｆ）と、
    　前記第３の層間絶縁膜に、前記第１の第２配線部と接続するビア、及び該ビアと接続する第３の第１配線部を形成する工程（ｇ）と、
    　前記工程（ｇ）の後に、前記第３の層間絶縁膜上に、第４の層間絶縁膜を形成する工程（ｈ）と、
    　前記第４の層間絶縁膜に、前記第３の第１配線部と接続する第３の第２配線部を形成する工程（ｉ）とをさらに備え、
    　前記工程（ｉ）において、前記第３の第１配線部、及び前記第３の第２配線部からなる第３の配線が構成されることを特徴とする請求項１３～２０のうちいずれか１項に半導体装置の製造方法。     A step (f) of forming a third interlayer insulating film on the second interlayer insulating film after the step (d);
    Forming a via connected to the first second wiring part and a third first wiring part connected to the via in the third interlayer insulating film (g);
    A step (h) of forming a fourth interlayer insulating film on the third interlayer insulating film after the step (g);
    Forming a third second wiring portion connected to the third first wiring portion on the fourth interlayer insulating film; and (i),
    21. The method according to claim 13, wherein in the step (i), a third wiring including the third first wiring portion and the third second wiring portion is configured. A method for manufacturing a semiconductor device.
  22. 　前記工程（ｇ）は、
    　前記第３の層間絶縁膜に、ビア孔及び配線溝を形成する工程（ｇ１）と、
    　前記ビア孔に前記ビアを形成すると共に、前記配線溝に前記第３の第１配線部を形成する工程（ｇ２）とを含むことを特徴とする請求項２１に記載の半導体装置の製造方法。     The step (g)
    Forming a via hole and a wiring groove in the third interlayer insulating film (g1);
    The method for manufacturing a semiconductor device according to claim 21, further comprising a step (g2) of forming the via in the via hole and forming the third first wiring portion in the wiring groove.
PCT/JP2009/004685 2008-10-22 2009-09-17 Semiconductor device and method for making same WO2010047038A1 (en)

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