JP2007173511A - Method for fabricating a semiconductor device - Google Patents

Method for fabricating a semiconductor device Download PDF

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JP2007173511A
JP2007173511A JP2005369066A JP2005369066A JP2007173511A JP 2007173511 A JP2007173511 A JP 2007173511A JP 2005369066 A JP2005369066 A JP 2005369066A JP 2005369066 A JP2005369066 A JP 2005369066A JP 2007173511 A JP2007173511 A JP 2007173511A
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film
insulating film
wiring
metal
forming
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Ryuichi Kanemura
龍一 金村
Yasushi Motobe
靖 本部
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Sony Corp
ソニー株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for fabricating a semiconductor device which suppresses an RC delay. <P>SOLUTION: This semiconductor fabrication method comprises a step for forming a dual damascene aperture 8 composed of a wiring groove 8a and a connection hole 8b on an interlayer insulating film 7 created on a substrate; a step for forming a metal film 21 made of Mn on the interlayer insulating film 7 covering the inner wall of the dual damascene aperture 8; a step for performing thermal treatment to cause metal contained in the metal film 21 to react to constituents of the interlayer insulating film 7, so that a self-forming barrier film 11 made of Mn compounds can be formed on an interface between the metal film 21 and the interlayer insulating film 7; a step for selectively removing a portion not reacting in the metal film 21; and a step for embedding a conductive layer containing Cu in the dual damascene aperture 8, so that an upper layer wiring 12 and a via 13 can be formed on the wiring groove 8a and the connection hole 8b, respectively. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置の製造方法に関し、さらに詳しくは、配線またはヴィアと層間絶縁膜との間に自己形成バリア膜が設けられたダマシン構造を有する半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a damascene structure in which a self-formed barrier film is provided between a wiring or a via and an interlayer insulating film.
半導体装置の微細化、高集積化に伴い、配線の時定数に起因する電気信号の遅れが深刻な問題となる。このため、多層配線工程で用いられる導電層は、アルミニウム(Al)系合金の配線に代わり、銅(Cu)配線が導入されるようになっている。CuはAlなど従来の多層配線構造に使われていた金属材料と違って、ドライエッチングによるパターニングが困難であるため、層間絶縁膜に配線溝を形成しておき、Cuを埋め込むことにより配線パターンを形成するダマシン法が一般に使われている。特に、層間絶縁膜に接続孔と配線溝を形成しておき、Cuの埋め込みを同時に行うデュアルダマシン法は、工程数の削減に有効である(例えば、特許文献1参照)。   With the miniaturization and high integration of semiconductor devices, delays in electrical signals due to wiring time constants become a serious problem. For this reason, copper (Cu) wiring is introduced into the conductive layer used in the multilayer wiring process instead of aluminum (Al) alloy wiring. Unlike metal materials used for conventional multilayer wiring structures such as Al, Cu is difficult to pattern by dry etching. Therefore, a wiring groove is formed in the interlayer insulating film, and the wiring pattern is formed by embedding Cu. The forming damascene method is generally used. In particular, a dual damascene method in which a connection hole and a wiring groove are formed in an interlayer insulating film and Cu is buried at the same time is effective in reducing the number of processes (for example, see Patent Document 1).
Cuダマシン配線の形成においては、通常、タンタル(Ta)、もしくはタンタル窒化膜(TaN)等のバリア膜をスパッタリング法によりダマシン開口部に成膜する。続いて、シード層となる薄いCu層をバリアメタル成膜と同一装置にてスパッタリング法により形成後、電解めっき法によりCuの埋め込みを行い、化学機械研磨(Chemical Mechanical Polishing(CMP))法により不要部分のCuとバリア膜を除去する方法が主流となっている。しかし、配線ピッチの微細化に伴い、バリア膜の段差被覆性に限界が見え始めており、Cuの埋め込み難易度が上がっている事、配線の総体積に占めるバリア膜の割合が増加し、配線抵抗が上昇している事、等の理由により、45nm世代以降のメタライゼーションにおいては、バリア膜の薄膜化及び段差被覆性の改善、さらにはめっきによるCuの埋め込み性能向上に関する研究が盛んに報告されている。   In forming the Cu damascene wiring, a barrier film such as tantalum (Ta) or tantalum nitride film (TaN) is usually formed in the damascene opening by sputtering. Subsequently, after forming a thin Cu layer as a seed layer by sputtering using the same apparatus as the barrier metal film formation, Cu is embedded by electrolytic plating and unnecessary by chemical mechanical polishing (CMP). A method of removing a portion of Cu and the barrier film has become the mainstream. However, as the wiring pitch becomes finer, the barrier coverage of the barrier film has started to reach its limit, the difficulty of embedding Cu has increased, the ratio of the barrier film to the total wiring volume has increased, and the wiring resistance has increased. In the metallization after the 45 nm generation, research on thinning the barrier film, improving the step coverage, and further improving the Cu embedding performance by plating has been actively reported. Yes.
近年、Cu配線のメタライゼーションに対する新しいアプローチとして、自己形成バリアと呼ばれる新技術が提案されている(例えば、非特許文献1参照)。この方法では、従来のバリア膜の成膜を行わず、ダマシン開口部に直接マンガン(Mn)を含有したCuをスパッタリング法により成膜し、その後の熱処理によりMnを拡散させ、層間絶縁膜表面にMn化合物を自己形成させることにより、コンフォーマルで3nm以下の薄膜バリア形成を可能とし、その後のめっき埋め込み難易度の低減も期待できる。   In recent years, a new technique called a self-forming barrier has been proposed as a new approach to metallization of Cu wiring (see, for example, Non-Patent Document 1). In this method, a conventional barrier film is not formed, but Cu containing manganese (Mn) is directly formed in a damascene opening by a sputtering method, and Mn is diffused by a subsequent heat treatment to form an interlayer insulating film surface. By self-forming the Mn compound, it is possible to form a thin film barrier of 3 nm or less conformally, and it can be expected that the subsequent difficulty of embedding plating will be reduced.
上記自己形成バリアプロセスについて、図10を用いて説明する。まず、図10(a)に示すように、図示しない基板に堆積された下地絶縁膜1上に、炭素含有酸化シリコン(SiOC)膜からなる層間絶縁膜2が形成され、この層間絶縁膜2に形成された配線溝3にバリア膜4を介してCuを埋め込んだ下層配線5が形成されている。また、下層配線5上および層間絶縁膜2上には、Cuの酸化防止膜6として、例えば炭化シリコン膜(SiC)が設けられている。   The self-forming barrier process will be described with reference to FIG. First, as shown in FIG. 10A, an interlayer insulating film 2 made of a carbon-containing silicon oxide (SiOC) film is formed on a base insulating film 1 deposited on a substrate (not shown). A lower layer wiring 5 in which Cu is embedded in the formed wiring trench 3 via a barrier film 4 is formed. Further, a silicon carbide film (SiC), for example, is provided as an anti-oxidation film 6 of Cu on the lower wiring 5 and the interlayer insulating film 2.
そして、酸化防止膜6上に、炭素含有酸化シリコン(SiOC)膜からなる低誘電材料層7aと酸化シリコン(SiO2)膜からなるハードマスク層7bとを順次積層してなる層間絶縁膜7を形成する。次いで、本構造の層間絶縁膜7に配線溝8aとこの配線溝8aの底部に連通する接続孔8bとからなるデュアルダマシン開口部8を形成する。その後、接続孔8b底部の酸化防止膜6を除去して、下層配線5を露出させる。 Then, an interlayer insulating film 7 formed by sequentially laminating a low dielectric material layer 7 a made of a carbon-containing silicon oxide (SiOC) film and a hard mask layer 7 b made of a silicon oxide (SiO 2 ) film on the antioxidant film 6. Form. Next, a dual damascene opening 8 composed of a wiring groove 8a and a connection hole 8b communicating with the bottom of the wiring groove 8a is formed in the interlayer insulating film 7 of this structure. Thereafter, the antioxidant film 6 at the bottom of the connection hole 8b is removed, and the lower layer wiring 5 is exposed.
次に、図10(b)に示すように、通常の指向性スパッタリング法により、上記デュアルダマシン開口部8の内壁を覆う状態で、ハードマスク層7b上に、1wt%のMnを含むCuMn合金膜からなるシード層9’を成膜する。   Next, as shown in FIG. 10B, a CuMn alloy film containing 1 wt% of Mn on the hard mask layer 7b in a state of covering the inner wall of the dual damascene opening 8 by a normal directional sputtering method. A seed layer 9 ′ made of is formed.
続いて、図10(c)に示すように、電解めっき法により、配線溝8aと接続孔8bとからなるデュアルダマシン開口部8を埋め込む状態で、シード層9’上に純Cuからなる導電膜10を形成する。   Subsequently, as shown in FIG. 10 (c), a conductive film made of pure Cu on the seed layer 9 ′ in a state where the dual damascene opening 8 made of the wiring groove 8a and the connection hole 8b is embedded by electrolytic plating. 10 is formed.
次に、図11(d)に示すように、窒素(N2)雰囲気下にて250℃〜400℃の熱処理を行うことにより、シード層9’中に含まれるMnを層間絶縁膜7の構成成分と反応させて、シード層9’と層間絶縁膜7との界面に、2nm〜3nmのMn化合物からなる自己形成バリア膜11を形成する。この際、導電膜10(前記図10(c)参照)中へのMn拡散も生じるため、導電膜10は、微量にMnを含んだCu膜からなる導電膜10’に変化する。また、このMn拡散にともない、シード層9’中のMn濃度は低下するが、ある程度のMnはシード層9’中に残存した状態となる。 Next, as shown in FIG. 11 (d), heat treatment at 250 ° C. to 400 ° C. is performed in a nitrogen (N 2 ) atmosphere, so that Mn contained in the seed layer 9 ′ is changed into the structure of the interlayer insulating film 7. By reacting with the components, a self-formed barrier film 11 made of a Mn compound of 2 nm to 3 nm is formed at the interface between the seed layer 9 ′ and the interlayer insulating film 7. At this time, since Mn diffusion also occurs in the conductive film 10 (see FIG. 10C), the conductive film 10 changes to a conductive film 10 ′ made of a Cu film containing a small amount of Mn. As the Mn diffuses, the Mn concentration in the seed layer 9 ′ decreases, but a certain amount of Mn remains in the seed layer 9 ′.
この後、図11(e)に示すように、化学機械研磨(Chemical Mechanical Polishing(CMP))法により、配線パターンとして不要な部分の導電膜10’(前記図11(d)参照)および自己形成バリア膜11を除去することで、上記配線溝8aに上層配線12’を形成するとともに、接続孔8bにヴィア13’を形成する。なお、ヴィア13’と下層配線5との界面には、上記自己形成バリア膜11は形成されないため、Cu(合金)同士の接合界面が形成される。また、下層配線5上と同様に、酸化防止膜14として、例えばSiC膜を上層配線12’上およびハードマスク層7b上に形成する。以上説明した図10(a)〜図11(e)の工程を繰り返すことで、デュアルダマシン構造の多層配線構造を形成する。   Thereafter, as shown in FIG. 11 (e), a part of the conductive film 10 ′ (see FIG. 11 (d)) unnecessary for the wiring pattern and self-forming is formed by a chemical mechanical polishing (CMP) method. By removing the barrier film 11, an upper layer wiring 12 'is formed in the wiring groove 8a, and a via 13' is formed in the connection hole 8b. Note that since the self-formed barrier film 11 is not formed at the interface between the via 13 ′ and the lower wiring 5, a bonding interface between Cu (alloy) is formed. Further, similarly to the lower layer wiring 5, as the antioxidant film 14, for example, a SiC film is formed on the upper layer wiring 12 'and the hard mask layer 7b. By repeating the steps of FIGS. 10A to 11E described above, a multilayer wiring structure having a dual damascene structure is formed.
上述したような製造方法により形成された多層配線構造においては、通常のTaからなるバリア膜を用いた埋め込みプロセスに比べて、薄膜化された自己形成バリア膜11が形成され、下層配線5とヴィア13’の界面にバリア膜が介在することが防止される。   In the multilayer wiring structure formed by the manufacturing method as described above, the thinned self-formed barrier film 11 is formed as compared with the embedding process using the barrier film made of ordinary Ta, and the lower wiring 5 and the via are formed. The barrier film is prevented from intervening at the interface 13 '.
特開平11−045887号公報Japanese Patent Laid-Open No. 11-045887
しかし、上述したような製造方法では、上層配線12’およびヴィア13’には、微量にMnが拡散されており、シード層9’中にもMnが残存するため、上層配線12’およびヴィア13’が純Cuで構成されている場合よりも比抵抗の上昇が起こり、十分に配線抵抗を下げられないという問題がある。これは、残存したMnによるCuの結晶格子ひずみの発生や結晶粒界への偏析に起因するものと考えられる。上記製造方法においては、上層配線12’のシート抵抗に換算して、純Cu配線に対し、約15%の上昇が認められた。従って、極薄膜の自己形成バリア膜11の形成を行っても、配線抵抗の低減には繋がらず、結果としてRC遅延(配線遅延)に代表されるデバイス性能の向上には効果が無いことになる。   However, in the manufacturing method as described above, since a very small amount of Mn is diffused in the upper layer wiring 12 ′ and the via 13 ′ and Mn remains in the seed layer 9 ′, the upper layer wiring 12 ′ and the via 13 are also present. There is a problem in that the specific resistance increases more than when 'is made of pure Cu, and the wiring resistance cannot be lowered sufficiently. This is thought to be due to the occurrence of crystal lattice distortion of Cu due to the remaining Mn and segregation to the grain boundaries. In the above manufacturing method, an increase of about 15% with respect to the pure Cu wiring was recognized in terms of the sheet resistance of the upper layer wiring 12 '. Therefore, even if the ultrathin self-formed barrier film 11 is formed, the wiring resistance is not reduced, and as a result, there is no effect in improving the device performance represented by RC delay (wiring delay). .
以上のことから、本発明の目的は、自己形成バリア膜を適用したダマシン配線の形成において、RC遅延が抑制された多層配線構造を有する半導体装置の製造方法を提供することにある。   In view of the above, an object of the present invention is to provide a method of manufacturing a semiconductor device having a multilayer wiring structure in which RC delay is suppressed in the formation of a damascene wiring to which a self-formed barrier film is applied.
上記目的を達成するために、本発明の半導体装置の製造方法は、基板上の絶縁膜に設けられた凹部に銅を含む導電層を埋め込む半導体装置の製造方法において、次のような工程を順次行うことを特徴としている。まず、第1工程では、基板上に設けられた絶縁膜に、基板に達する凹部を形成する工程を行う。次に、第2工程では、凹部の内壁を覆う状態で、銅以外の金属からなる金属膜を形成する工程を行う。次いで、第3工程では、熱処理を行い、金属膜中の金属を絶縁膜の構成成分と反応させて、金属膜と絶縁膜との界面に、導電層からの銅の拡散を防止する金属化合物からなるバリア膜を形成する工程を行う。続いて、第4工程では、金属膜の未反応部分を選択的に除去する工程を行う。その後、第5工程では、未反応部分が除去された凹部に、導電層を埋め込む工程を行う。   In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes the following steps sequentially in a method for manufacturing a semiconductor device in which a conductive layer containing copper is embedded in a recess provided in an insulating film on a substrate. It is characterized by doing. First, in the first step, a step of forming a recess reaching the substrate in an insulating film provided on the substrate is performed. Next, in the second step, a step of forming a metal film made of a metal other than copper is performed while covering the inner wall of the recess. Next, in the third step, heat treatment is performed to react the metal in the metal film with the constituent components of the insulating film, and from the metal compound that prevents the diffusion of copper from the conductive layer at the interface between the metal film and the insulating film. A step of forming a barrier film is performed. Subsequently, in the fourth step, a step of selectively removing an unreacted portion of the metal film is performed. Thereafter, in the fifth step, a step of embedding a conductive layer in the recess from which the unreacted portion has been removed is performed.
このような半導体装置の製造方法によれば、凹部の内壁を覆う状態で金属膜を形成し、金属膜中の金属を絶縁膜の構成成分と反応させて、金属化合物からなるバリア膜を形成した後、上記金属膜の未反応部分を除去することから、凹部内に埋め込まれる導電層が配線またはヴィアである場合には、銅を含む導電層中に未反応の銅以外の金属が残存することによる配線抵抗の上昇が抑制される。   According to such a method of manufacturing a semiconductor device, a metal film is formed so as to cover the inner wall of the recess, and a metal in the metal film is reacted with a component of the insulating film to form a barrier film made of a metal compound. After that, since the unreacted portion of the metal film is removed, when the conductive layer embedded in the recess is a wiring or a via, a metal other than unreacted copper remains in the conductive layer containing copper. An increase in wiring resistance due to is suppressed.
以上説明したように、本発明の半導体装置の製造方法によれば、配線抵抗の上昇が抑制されるため、RC遅延が抑制される。したがって、高性能且つ、高信頼性の多層配線を有した半導体装置を製造することができる。   As described above, according to the method for manufacturing a semiconductor device of the present invention, since an increase in wiring resistance is suppressed, RC delay is suppressed. Therefore, a semiconductor device having a multilayer wiring with high performance and high reliability can be manufactured.
以下、本発明の実施の形態を図面に基づいて詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(第1実施形態)
本実施形態例は、本発明にかかる半導体装置の製造方法の実施形態の一例であり、デュアルダマシン構造の形成に係わる。以下、図1〜図4の製造工程断面図を用いて本発明の第1実施形態を説明する。なお、背景技術と同様の構成には、同一の番号を付して説明することとする。
(First embodiment)
The present embodiment is an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention, and relates to the formation of a dual damascene structure. The first embodiment of the present invention will be described below with reference to the cross-sectional views of the manufacturing steps shown in FIGS. In addition, the same number is attached | subjected and demonstrated to the structure similar to background art.
図1(a)に示すように、図示しない基板に堆積された下地絶縁膜1上に、層間絶縁膜2が形成され、この層間絶縁膜2に形成された配線溝3にバリア膜4を介してCuを埋め込んだ下層配線5が形成されている。上記層間絶縁膜2には、一例として炭素含有酸化シリコン(SiOC)膜が用いられている。また、下層配線5上および層間絶縁膜2上には、例えば炭化シリコン膜(SiC)からなるCuの酸化防止膜6が設けられている。この酸化防止膜6は、下層配線5からのCuの拡散を防止する拡散防止膜または酸化防止膜6上に形成する層間絶縁膜に接続孔を形成するためのエッチングストッパー膜としても機能する。   As shown in FIG. 1A, an interlayer insulating film 2 is formed on a base insulating film 1 deposited on a substrate (not shown), and a wiring film 3 formed in the interlayer insulating film 2 is interposed through a barrier film 4. Thus, the lower wiring 5 in which Cu is embedded is formed. For example, a carbon-containing silicon oxide (SiOC) film is used for the interlayer insulating film 2. On the lower wiring 5 and the interlayer insulating film 2, a Cu antioxidant film 6 made of, for example, a silicon carbide film (SiC) is provided. This antioxidant film 6 also functions as a diffusion preventing film for preventing the diffusion of Cu from the lower wiring 5 or an etching stopper film for forming a connection hole in an interlayer insulating film formed on the antioxidant film 6.
そして、上記酸化防止膜6上に、無機の低誘電材料であるSiOC膜からなる低誘電材料層7aと酸化シリコン(SiO2)膜からなるハードマスク層7bとを順次積層してなる層間絶縁膜7を形成する。次いで、本構造の層間絶縁膜7に、配線溝8aとこの配線溝8aの底部に連通する接続孔8bとからなるデュアルダマシン開口部8を形成する。続いて、接続孔8bの底部の上記酸化防止膜6を除去し、接続孔8bの底部に下層配線5の表面を露出させる。なお、デュアルダマシン開口部8は、請求項の凹部に相当する。その後、必要に応じて、各種プラズマ処理を行うことで、デュアルダマシン開口部8の側壁を均一化してもよい。 An interlayer insulating film is formed by sequentially laminating a low dielectric material layer 7a made of a SiOC film, which is an inorganic low dielectric material, and a hard mask layer 7b made of a silicon oxide (SiO 2 ) film on the antioxidant film 6. 7 is formed. Next, a dual damascene opening 8 composed of a wiring groove 8a and a connection hole 8b communicating with the bottom of the wiring groove 8a is formed in the interlayer insulating film 7 of this structure. Subsequently, the antioxidant film 6 at the bottom of the connection hole 8b is removed, and the surface of the lower wiring 5 is exposed at the bottom of the connection hole 8b. The dual damascene opening 8 corresponds to a recess in the claims. Thereafter, the sidewalls of the dual damascene opening 8 may be made uniform by performing various plasma treatments as necessary.
次に、図1(b)に示すように、通常の指向性スパッタリング法により、上記デュアルダマシン開口部8の内壁を覆う状態で、ハードマスク層7b上に、例えばMnからなる金属膜21を形成する。ここでは、スパッタチャンバーに純Mnのターゲットを取り付け、5nm〜20nmのMn膜を堆積させる。   Next, as shown in FIG. 1B, a metal film 21 made of, for example, Mn is formed on the hard mask layer 7b by a normal directional sputtering method so as to cover the inner wall of the dual damascene opening 8. To do. Here, a target of pure Mn is attached to the sputtering chamber, and a 5 nm to 20 nm Mn film is deposited.
続いて、図1(c)に示すように、N2雰囲気下にて250℃〜400℃の熱処理を行うことにより、金属膜21中のMnと層間絶縁膜7の構成成分とを反応させて、金属膜21と層間絶縁膜7との界面に、2nm〜3nmのMn化合物からなる自己形成バリア膜11を形成する。この自己形成バリア膜11は、後工程で配線溝8aおよび接続孔8bに形成されるCuからなる上層配線およびヴィアから層間絶縁膜7へのCuの拡散を防止する。 Subsequently, as shown in FIG. 1C, heat treatment at 250 ° C. to 400 ° C. is performed in an N 2 atmosphere to react Mn in the metal film 21 with the constituent components of the interlayer insulating film 7. Then, a self-formed barrier film 11 made of a Mn compound of 2 nm to 3 nm is formed at the interface between the metal film 21 and the interlayer insulating film 7. This self-formed barrier film 11 prevents the diffusion of Cu from the upper layer wiring and via formed in the wiring groove 8a and the connection hole 8b in a later process to the interlayer insulating film 7.
ここでは、層間絶縁膜7が、SiOC膜からなる低誘電材料層7aとSiO2膜からなるハードマスク層7bとで構成されているため、この自己形成バリア膜11は、例えばシリコン含有Mn酸化物(MnSixy)、またはMn酸化物(Mnxy)等のMn化合物で構成される。また、接続孔8bの底部には、上記自己形成バリア膜11は形成されずに、上記熱処理により、接続孔8b底部を覆う金属膜21からこの金属膜21に接する下層配線5の表面側にMnが拡散された状態となる(領域A)。 Here, since the interlayer insulating film 7 is composed of the low dielectric material layer 7a made of SiOC film and the hard mask layer 7b made of SiO 2 film, the self-formed barrier film 11 is made of, for example, a silicon-containing Mn oxide. (MnSi x O y ) or a Mn compound such as Mn oxide (Mn x O y ). Further, the self-forming barrier film 11 is not formed at the bottom of the connection hole 8b, and Mn is formed on the surface side of the lower layer wiring 5 in contact with the metal film 21 from the metal film 21 covering the bottom of the connection hole 8b by the heat treatment. Is diffused (region A).
その後、図1(d)に示すように、Mnからなる金属膜21(前記図1(c)参照)の未反応部分を選択的に除去する。これにより、デュアルダマシン開口部8の内壁に自己形成バリア膜11が露出される。ここでは、ウェットエッチングにより、自己形成バリア膜11および下層配線5に対して、上記金属膜21の未反応部分を選択的に除去することとする。この際、接続孔8b底部に露出されたCuからなる下層配線5の表面がエッチングされない条件で行うことが好ましい。   Thereafter, as shown in FIG. 1D, unreacted portions of the metal film 21 made of Mn (see FIG. 1C) are selectively removed. As a result, the self-formed barrier film 11 is exposed on the inner wall of the dual damascene opening 8. Here, the unreacted portion of the metal film 21 is selectively removed from the self-formed barrier film 11 and the lower wiring 5 by wet etching. At this time, it is preferable to carry out under the condition that the surface of the lower layer wiring 5 made of Cu exposed at the bottom of the connection hole 8b is not etched.
ここで、図2のMnのエリンガム図(例えば、「Atlas of Eh-pH diagram Intercomparison of thermodynamic database」p.146-147参照)に示すように、無電界状態において、Mn膜は中性から酸性の広範囲の薬液に対して溶解性がある。一方、図3のCuのエリンガム図(例えば、「ECS Proceedings」,2000年,Vol.99-36,p.582-592参照)に示すように、無電界状態において、Cu膜は中性からアルカリ性側で酸化される。   Here, as shown in the Ellingham diagram of Mn in FIG. 2 (see, for example, “Atlas of Eh-pH diagram Intercomparison of thermodynamic database” p.146-147), the Mn film is neutral to acidic in an electric field state. It is soluble in a wide range of chemicals. On the other hand, as shown in the Ellingham diagram of Cu in FIG. 3 (see, for example, “ECS Proceedings”, 2000, Vol. 99-36, p. 582-592), the Cu film is neutral to alkaline in the absence of an electric field. Oxidized on the side.
したがって、再び図1(d)に示すように、中性〜酸性の薬液処理により、金属膜21の未反応部分を除去することで、下層配線5の表面をエッチングせずに、金属膜21の未反応部分を選択的に除去することが可能となる。ここでは、上記金属膜21の表面にpH5程度の二酸化炭素(CO2)水を供給して約3分間の流水処理を行うこととする。また、上記処理以外に、pH7以下のフッ化アンモン系の有機洗浄処理や、酸性のフッ酸処理を行うことによっても、下層配線5の表面エッチングを防止しつつ、金属膜21の未反応部分を選択的に除去することが可能である。 Therefore, as shown in FIG. 1D again, the unreacted portion of the metal film 21 is removed by neutral to acidic chemical treatment, so that the surface of the lower layer wiring 5 is not etched and the metal film 21 is not etched. It becomes possible to selectively remove the unreacted portion. Here, carbon dioxide (CO 2 ) water having a pH of about 5 is supplied to the surface of the metal film 21 to perform running water treatment for about 3 minutes. In addition to the above treatment, an ammonium fluoride organic cleaning treatment having a pH of 7 or less or an acidic hydrofluoric acid treatment can also be used to prevent unreacted portions of the metal film 21 while preventing surface etching of the lower wiring 5. It can be selectively removed.
次いで、図4(e)に示すように、通常の指向性スパッタリング法により、自己形成バリア膜11が露出されたデュアルダマシン開口部8の内壁を覆う状態で、自己形成バリア膜11上に、例えば純Cuからなるシード層9を成膜する。   Next, as shown in FIG. 4E, on the self-forming barrier film 11 in a state of covering the inner wall of the dual damascene opening 8 where the self-forming barrier film 11 is exposed by a normal directional sputtering method, for example, A seed layer 9 made of pure Cu is formed.
続いて、図4(f)に示すように、電解めっき法により、デュアルダマシン開口部8を埋め込む状態で、シード層9(前記図4(e)参照)上に、例えば純Cuからなる導電膜10を形成する。なお、ここでは、シード層9と導電膜10を純Cuで構成し、後述するように上層配線とヴィアとが純Cuで構成される例について説明するが、上記シード層9と導電膜10とはCuを主成分として含む膜であればよく、例えば比抵抗の上昇が少ないCuAg合金を用いてもよい。   Subsequently, as shown in FIG. 4F, a conductive film made of, for example, pure Cu is formed on the seed layer 9 (see FIG. 4E) in a state where the dual damascene opening 8 is embedded by electrolytic plating. 10 is formed. Here, an example in which the seed layer 9 and the conductive film 10 are made of pure Cu and the upper wiring and the via are made of pure Cu as described later will be described. However, the seed layer 9 and the conductive film 10 May be a film containing Cu as a main component. For example, a CuAg alloy with a small increase in specific resistance may be used.
その後、図4(g)に示すように、必要に応じてN2雰囲気下にて、150℃〜400℃の熱処理を行い、導電膜10(前記図4(f)参照)を構成するCu膜の結晶状態と膜ストレスを安定化させる。続いて、CMP法により、配線パターンとして不要な部分の導電膜10および自己形成バリア膜11を除去することで、上記配線溝8aに上層配線12を形成するとともに、接続孔8bにヴィア13を形成する。次いで、上層配線12上およびハードマスク層7b上に、例えばSiC膜からなる酸化防止膜14を形成する。 Thereafter, as shown in FIG. 4G, heat treatment at 150 ° C. to 400 ° C. is performed in an N 2 atmosphere as necessary to form a Cu film constituting the conductive film 10 (see FIG. 4F). Stabilizes the crystalline state and film stress. Subsequently, unnecessary portions of the conductive film 10 and the self-formed barrier film 11 as a wiring pattern are removed by CMP to form the upper layer wiring 12 in the wiring groove 8a and the via 13 in the connection hole 8b. To do. Next, an antioxidant film 14 made of, for example, a SiC film is formed on the upper layer wiring 12 and the hard mask layer 7b.
この後の工程は、図1(a)〜図4(g)を用いて説明した工程を繰り返して行うことで、デュアルダマシン構造の多層配線構造を形成する。   Subsequent steps are performed by repeating the steps described with reference to FIGS. 1A to 4G, thereby forming a dual damascene multilayer wiring structure.
このような半導体装置の製造方法によれば、デュアルダマシン開口部8の内壁を覆う状態で、金属膜21を形成し、金属膜21中のMnを層間絶縁膜7の構成成分と反応させてMn化合物からなる自己形成バリア膜11を形成した後、上記金属膜21の未反応部分(Mn)を除去することから、Cuからなる上層配線12およびまたはヴィア13にMnが残存することによる配線抵抗の上昇が抑制される。これにより、RC遅延を抑制することができる。また、薄膜化された自己形成バリア膜11が形成されるとともに、下層配線5とヴィア13との間にバリア膜が介在しない点は、従来技術と同様であるため、低抵抗で、且つ良好な埋め込み特性を有し、高性能、高信頼性の多層配線構造を有した半導体装置を製造することができる。   According to such a method for manufacturing a semiconductor device, the metal film 21 is formed in a state in which the inner wall of the dual damascene opening 8 is covered, and Mn in the metal film 21 is reacted with the constituent components of the interlayer insulating film 7 to form Mn. After forming the self-forming barrier film 11 made of a compound, the unreacted portion (Mn) of the metal film 21 is removed, so that the wiring resistance due to Mn remaining in the upper wiring 12 and / or the via 13 made of Cu. The rise is suppressed. Thereby, RC delay can be suppressed. Further, since the thinned self-formed barrier film 11 is formed and the barrier film is not interposed between the lower layer wiring 5 and the via 13, it is the same as in the prior art, so that the resistance is low and the resistance is good. A semiconductor device having embedded characteristics and a high-performance, high-reliability multilayer wiring structure can be manufactured.
なお、本実施形態では層間絶縁膜7がSiOC膜からなる低誘電材料層7aとSiO2膜からなるハードマスク層7bとの積層膜で構成された例について説明したが、本発明はこれに限定されず、層間絶縁膜7の構成材料は自己形成バリア膜11を形成可能であれば、デバイス要求性能によって選択すればよい。層間絶縁膜7の構成材料としては、無機系材料として、上述したSiO2膜、SiOC膜の他に、無機系の低誘電材料膜であるフッ素含有酸化シリコン(SiOF)膜、有機系の低誘電材料膜として、ポリアリールエーテル(PAE)膜、P−ベンゾシクロブテン(P−BCB)膜等を用いてもよい。または、これらを多孔質化した膜を用いてもよい。上述した膜は、単層で用いても積層してもよく、例えば、無機系の低誘電材料膜と有機系の低誘電材料膜とを積層させてハイブリッド構造としてもよい。 In the present embodiment, an example in which the interlayer insulating film 7 is composed of a laminated film of a low dielectric material layer 7a made of an SiOC film and a hard mask layer 7b made of an SiO 2 film has been described, but the present invention is not limited to this. If the self-forming barrier film 11 can be formed, the constituent material of the interlayer insulating film 7 may be selected according to the device required performance. As the constituent material of the interlayer insulating film 7, as an inorganic material, in addition to the above-described SiO 2 film and SiOC film, a fluorine-containing silicon oxide (SiOF) film which is an inorganic low dielectric material film, an organic low dielectric constant As the material film, a polyaryl ether (PAE) film, a P-benzocyclobutene (P-BCB) film, or the like may be used. Alternatively, a film obtained by making these porous may be used. The above-described film may be used as a single layer or may be stacked. For example, an inorganic low dielectric material film and an organic low dielectric material film may be stacked to form a hybrid structure.
また、本実施形態では、金属膜21として、Mn膜を成膜する例について説明したが、本発明はこれに限定されるものではなく、デュアルダマシン開口部8の側壁を構成する絶縁膜と反応してCuの拡散を防止するバリア膜を形成可能な金属で構成されていればよい。このような金属材料としては、Mn以外に例えばアルミニウム(Al)、チタン(Ti)を例示することができる。上記金属膜21にAl膜を用いた場合には、自己形成バリア膜11として、例えばシリコン含有Al酸化物(AlSixy)またはAl酸化物(Alxy)が形成され、上記金属膜21にTi膜を用いた場合には、自己形成バリア膜11として、例えばシリコン含有Ti酸化物(TiSixy)またはTi酸化物(Tixy)が形成される。また、上記金属膜21として、絶縁膜と反応してバリア膜を形成可能な金属を組み合わせた合金膜を用いることも可能である。 In the present embodiment, an example in which a Mn film is formed as the metal film 21 has been described. However, the present invention is not limited to this, and reacts with the insulating film that forms the sidewall of the dual damascene opening 8. Thus, it is only necessary to be made of a metal capable of forming a barrier film for preventing diffusion of Cu. Examples of such metal materials include aluminum (Al) and titanium (Ti) in addition to Mn. When an Al film is used for the metal film 21, for example, silicon-containing Al oxide (AlSi x O y ) or Al oxide (Al x O y ) is formed as the self-forming barrier film 11, and the metal film When a Ti film is used for 21, for example, silicon-containing Ti oxide (TiSi x O y ) or Ti oxide (Ti x O y ) is formed as the self-forming barrier film 11. Further, as the metal film 21, an alloy film combined with metals capable of forming a barrier film by reacting with the insulating film can be used.
さらに、本実施形態では、自己形成バリア膜11を構成するMn化合物として、シリコン含有Mn酸化物(MnSixy)またはMn酸化物(Mnxy)を例示したが、層間絶縁膜7が、例えば有機系絶縁膜等の炭素を含む絶縁膜である場合には、自己形成バリア膜11を構成するMn化合物としてMn炭化物(Mnxy)が形成される場合もある。なお、金属膜21として、上述したAl膜またはTi膜を用いた場合には、Al炭化物(Alxy)またはチタン炭化物(Tixy)が形成される場合もある。 Further, in the present embodiment, the silicon-containing Mn oxide (MnSi x O y ) or Mn oxide (Mn x O y ) is exemplified as the Mn compound constituting the self-forming barrier film 11. For example, in the case of an insulating film containing carbon such as an organic insulating film, Mn carbide (Mn x C y ) may be formed as the Mn compound constituting the self-forming barrier film 11. When the above-described Al film or Ti film is used as the metal film 21, Al carbide (Al x C y ) or titanium carbide (Ti x C y ) may be formed.
(第2実施形態)
次に、本発明の半導体装置の製造方法に係る第2の実施の形態を図5〜図7の製造工程断面図を用いて説明する。なお、第1実施形態と同様の構成には、同一の番号を付して説明する。ここでは、層間絶縁膜に多孔質(ポーラス)構造の低誘電材料(low-k材料)を適用した例について説明する。
(Second Embodiment)
Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described using the manufacturing process sectional views of FIGS. In addition, the same number is attached | subjected and demonstrated to the structure similar to 1st Embodiment. Here, an example in which a low dielectric material (low-k material) having a porous structure is applied to the interlayer insulating film will be described.
図5(a)に示すように、基板(図示せず)に堆積された下地絶縁膜1上に、例えばPAE膜からなる有機絶縁層2a’と例えばSiO2膜からなるハードマスク層2b’とを順次積層してなる層間絶縁膜2’が形成されている。そして、この層間絶縁膜2’に形成された配線溝3にはバリア膜4を介して、Cuからなる下層配線5が形成されている。また、下層配線5上およびハードマスク層2b’上には、例えばSiC膜からなる酸化防止膜6が35nmの膜厚で設けられている。 As shown in FIG. 5A, an organic insulating layer 2a ′ made of, for example, a PAE film and a hard mask layer 2b ′ made of, for example, a SiO 2 film are formed on a base insulating film 1 deposited on a substrate (not shown). Is formed in order. A lower layer wiring 5 made of Cu is formed in the wiring groove 3 formed in the interlayer insulating film 2 ′ via a barrier film 4. On the lower wiring 5 and the hard mask layer 2b ′, an antioxidant film 6 made of, for example, a SiC film is provided with a thickness of 35 nm.
まず、酸化防止膜6上に、例えば多孔質(ポーラス)構造の低誘電材料層を含む層間絶縁膜7’を形成する。層間絶縁膜7’としては、例えば多孔質構造のSiOC膜(ポーラスSiOC膜)からなる無機絶縁層7a’と、多孔質構造のPAE膜(ポーラスPAE膜)からなる有機絶縁層7b’およびSiO2膜からなるハードマスク層7c’とを順次積層することとする。 First, an interlayer insulating film 7 ′ including a low dielectric material layer having a porous structure, for example, is formed on the antioxidant film 6. As the interlayer insulating film 7 ′, for example, an inorganic insulating layer 7a ′ made of a porous SiOC film (porous SiOC film), an organic insulating layer 7b ′ made of a porous PAE film (porous PAE film), and SiO 2 are used. A hard mask layer 7c ′ made of a film is sequentially laminated.
ここで、ポーラスSiOC膜からなる無機絶縁層7a’は、塗布およびキュアにより形成する。このポーラスSiOC膜は、例えば触媒化学社製のNCS(Nano Clustorering Silica)を塗布し、N2雰囲気下で300℃〜400℃のキュアを施すことにより形成することができる。このポーラスSiOC膜の比誘電率は2.3前後、平均ポアサイズは3nm以下である。また、ポーラスSiOC膜として、JSR社のLKDシリーズやその他のポーラスMSQ(MSQ:メチルシルセスキオキサン)膜を用いることもできる。また、平行平板型プラズマCVD法にて、メチルシラン系ガスと必要に応じてポアジェンソースを使って成膜してもよい。さらには、電子ビームキュアや紫外線キュアを施してSiOC膜の結合を整えることも可能である。 Here, the inorganic insulating layer 7a ′ made of a porous SiOC film is formed by coating and curing. This porous SiOC film can be formed, for example, by applying NCS (Nano Clustorering Silica) manufactured by Catalytic Chemical Co., Ltd. and curing at 300 ° C. to 400 ° C. in an N 2 atmosphere. This porous SiOC film has a relative dielectric constant of around 2.3 and an average pore size of 3 nm or less. Further, as the porous SiOC film, an LKD series manufactured by JSR or other porous MSQ (MSQ: methylsilsesquioxane) film can be used. Alternatively, the film may be formed by a parallel plate type plasma CVD method using a methylsilane-based gas and, if necessary, a pore source. Furthermore, the bonding of the SiOC film can be adjusted by performing electron beam curing or ultraviolet curing.
また、ポーラスPAE膜からなる有機絶縁層7b’は、前駆体をスピンコート法により塗布した後、300℃〜400℃程度の熱処理を行って形成する。ポーラスPAE膜は、例えばダウケミカル(Dow Chemical)社製のPorous SiLK-Yをスピンコート法により堆積した後、300℃〜400℃程度の熱処理を行って形成することができる。このポーラスPAE膜の比誘電率は2.3、平均ポアサイズは数nm程度である。   The organic insulating layer 7b 'made of a porous PAE film is formed by applying a precursor by a spin coating method and then performing a heat treatment at about 300 ° C to 400 ° C. The porous PAE film can be formed, for example, by depositing Porous SiLK-Y manufactured by Dow Chemical Co., Ltd. by spin coating, and then performing a heat treatment at about 300 ° C. to 400 ° C. This porous PAE film has a relative dielectric constant of 2.3 and an average pore size of about several nm.
次に、本構造の層間絶縁膜7’に配線溝8aと接続孔8bとからなるデュアルダマシン開口部8を形成する。ここで、ハードマスク層7c’および有機絶縁層7b’には配線溝8aが形成され、無機絶縁層7a’には接続孔8bを形成することとする。ここで、本実施形態では、後述するように、デュアルダマシン開口部8の内壁を覆う状態で保護絶縁膜を形成することから、配線溝8aと接続孔8bを保護絶縁膜が形成される分、広く開口する。その後、接続孔8bの底部の酸化防止膜6を除去し、下層配線5を露出させる。   Next, a dual damascene opening 8 composed of a wiring groove 8a and a connection hole 8b is formed in the interlayer insulating film 7 'of this structure. Here, wiring grooves 8a are formed in the hard mask layer 7c 'and the organic insulating layer 7b', and connection holes 8b are formed in the inorganic insulating layer 7a '. Here, in the present embodiment, as will be described later, since the protective insulating film is formed so as to cover the inner wall of the dual damascene opening 8, the wiring groove 8a and the connection hole 8b are formed by the protective insulating film. Open wide. Thereafter, the antioxidant film 6 at the bottom of the connection hole 8b is removed, and the lower wiring 5 is exposed.
このデュアルダマシン開口部8の形成方法としては、最初に接続孔8bを開口し、その後に配線溝8aを開口する方法を用いることができる。また、上記層間絶縁膜7’上に形成した積層ハードマスク(図示省略)に配線溝パターンを形成した後、上記層間絶縁膜7’に接続孔8bを途中まで開口し、その後、上記積層ハードマスクを用いて配線溝8aと接続孔8bとを完全に開口する製造方法を用いてもよい。この詳細な形成方法は、例えば特開2004−63859号公報に開示されている。   As a method of forming the dual damascene opening 8, a method of opening the connection hole 8b first and then opening the wiring groove 8a can be used. Further, after forming a wiring groove pattern in a laminated hard mask (not shown) formed on the interlayer insulating film 7 ′, a connection hole 8b is opened partway in the interlayer insulating film 7 ′, and then the laminated hard mask is formed. A manufacturing method in which the wiring groove 8a and the connection hole 8b are completely opened using the above may be used. This detailed forming method is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-63859.
次に、図5(b)に示すように、上記デュアルダマシン開口部8の内壁を覆う状態で、ハードマスク層7c’上に、例えばSiO2膜からなる保護絶縁膜22を形成する。この保護絶縁膜22は、多孔質膜のように粗な膜ではなく、緻密に形成された膜で形成されることが好ましい。これにより、デュアルダマシン開口部8の内壁を構成する多孔質構造の無機絶縁層7a’と有機絶縁層7b’とが保護絶縁膜22で覆われることから、後工程でデュアルダマシン開口部8の内壁に形成する自己形成バリア膜の密着性不良が防止され、無機絶縁層7a’や有機絶縁層7b’からの脱ガスが抑制される。 Next, as shown in FIG. 5B, a protective insulating film 22 made of, for example, a SiO 2 film is formed on the hard mask layer 7 c ′ so as to cover the inner wall of the dual damascene opening 8. The protective insulating film 22 is preferably formed of a dense film rather than a rough film like a porous film. Thereby, the inorganic insulating layer 7a ′ and the organic insulating layer 7b ′ having a porous structure constituting the inner wall of the dual damascene opening 8 are covered with the protective insulating film 22, so that the inner wall of the dual damascene opening 8 is formed in a later step. Adhesive failure of the self-formed barrier film formed on the substrate is prevented, and degassing from the inorganic insulating layer 7a ′ and the organic insulating layer 7b ′ is suppressed.
保護絶縁膜22の成膜方法は一例として、平行平板型プラズマCVD(Chemical Vapor Deposition)装置を用い、シリコン源にはTEOS(Tetraethyl orthosilicate Tetraethoxysilane)ガスを用い、酸化剤として一酸化二窒素(N2O)ガスを用いる。また、成膜条件としては、基板温度を300℃〜400℃に設定し、プラズマパワーを150W〜350W、成膜雰囲気の圧力を100Pa〜1000Pa程度に設定する。上記成膜条件で、膜厚20nmのSiO2膜を成膜した結果、比誘電率は4前後であった。 For example, the protective insulating film 22 is formed by using a parallel plate plasma CVD (Chemical Vapor Deposition) apparatus, using TEOS (Tetraethyl orthosilicate Tetraethoxysilane) gas as a silicon source, and dinitrogen monoxide (N 2 ) as an oxidant. O) Gas is used. As film formation conditions, the substrate temperature is set to 300 ° C. to 400 ° C., the plasma power is set to 150 W to 350 W, and the pressure of the film formation atmosphere is set to about 100 Pa to 1000 Pa. As a result of forming a 20 nm thick SiO 2 film under the above film forming conditions, the relative dielectric constant was about 4.
なお、ここでは、保護絶縁膜22をSiO2膜で形成することとするが、SiO2膜に拘わらず、非多孔質構造の絶縁膜であればよく、例えば窒化シリコン(SiN)膜、窒素含有炭化シリコン(SiCN)膜、窒素含有酸化シリコン(SiON)膜、炭素含有酸化シリコン(SiOC)膜、P−ベンゾシクロブテン(P−BCB)、メタン(CH4)系等の有機絶縁膜を用いることも可能である。 Here, although the forming the protective insulating film 22 of SiO 2 film, regardless of the SiO 2 film may be a dielectric film of a non-porous structure, for example, silicon nitride (SiN) film, a nitrogen-containing Use a silicon carbide (SiCN) film, a nitrogen-containing silicon oxide (SiON) film, a carbon-containing silicon oxide (SiOC) film, a P-benzocyclobutene (P-BCB), an organic insulating film such as methane (CH 4 ). Is also possible.
続いて、図5(c)に示すように、接続孔8b底部の保護絶縁膜22を選択的に開口させる。この方法としては、例えばタンタル(Ta)ターゲットが設置された指向性のマグネトロンスパッタリング装置を用いて、基板バイアスを1000W、ターゲットDCパワーを5kWに設定し、アルゴン(Ar)100%雰囲気として、26.7mPaの成膜圧力にて、Taの成膜量とエッチング量との比率が、いわゆるベタ膜上でプラスマイナスゼロとなるように設定して所定時間の放電処理を施す。これにより、配線溝8a底部上およびハードマスク層7c’上ならびに側壁部では保護絶縁膜22が残存した状態を保ちながら、アスペクト比が高い接続孔8b底部では、バイアスエッチングの成分が大きくなることにより、保護絶縁膜22を選択的に貫通させることが出来る。この際、下層配線5の表面は掘り込まれた状態となる。   Subsequently, as shown in FIG. 5C, the protective insulating film 22 at the bottom of the connection hole 8b is selectively opened. As this method, for example, using a directional magnetron sputtering apparatus in which a tantalum (Ta) target is installed, a substrate bias is set to 1000 W, a target DC power is set to 5 kW, and an argon (Ar) 100% atmosphere is used. At a film forming pressure of 7 mPa, a discharge process for a predetermined time is performed by setting the ratio of the Ta film forming amount and the etching amount to be plus or minus zero on a so-called solid film. As a result, the bias etching component becomes large at the bottom of the connection hole 8b having a high aspect ratio while the protective insulating film 22 remains on the bottom of the wiring trench 8a, the hard mask layer 7c ′, and the side wall. The protective insulating film 22 can be selectively penetrated. At this time, the surface of the lower layer wiring 5 is dug.
この後の工程は、第1実施形態と同様に行うこととする。すなわち、図6(d)に示すように、通常の指向性スパッタリング法により、上記デュアルダマシン開口部8の内壁を覆う状態で、保護絶縁膜22上に、例えばMnからなる金属膜21を5nm〜20nmの膜厚で形成する。   The subsequent steps are performed in the same manner as in the first embodiment. That is, as shown in FIG. 6D, a metal film 21 made of, for example, Mn is formed on the protective insulating film 22 in a state of covering the inner wall of the dual damascene opening 8 by a normal directional sputtering method. It is formed with a film thickness of 20 nm.
続いて、図6(e)に示すように、N2雰囲気下にて250℃〜400℃の熱処理を行うことにより、金属膜21中のMnと保護絶縁膜22の構成成分とを反応させて、金属膜21と保護絶縁膜22との界面に、2nm〜3nmのMn化合物からなる自己形成バリア膜11を形成する。ここでは、保護絶縁膜22がSiO2膜で構成されることから、自己形成バリア膜11は、例えばMnシリコン酸化物(MnSixy)またはMn酸化物(MnOz)等のMn化合物で構成される。また、接続孔8bの底部には自己形成バリア膜11は形成されずに、上記熱処理により、接続孔8b底部を覆う金属膜21からこの金属膜21に接する下層配線5の表面側にMnが拡散された状態となる(領域A)。 Subsequently, as shown in FIG. 6E, heat treatment at 250 ° C. to 400 ° C. is performed in an N 2 atmosphere to react Mn in the metal film 21 with the constituent components of the protective insulating film 22. Then, the self-formed barrier film 11 made of a 2 nm to 3 nm Mn compound is formed at the interface between the metal film 21 and the protective insulating film 22. Here, since the protective insulating film 22 is composed of a SiO 2 film, the self-forming barrier film 11 is composed of a Mn compound such as Mn silicon oxide (MnSi x O y ) or Mn oxide (MnO z ). Is done. Further, the self-formed barrier film 11 is not formed at the bottom of the connection hole 8b, and Mn diffuses from the metal film 21 covering the bottom of the connection hole 8b to the surface side of the lower wiring 5 in contact with the metal film 21 by the heat treatment. (Region A).
その後、図6(f)に示すように、Mnからなる金属膜21(前記6(e)参照)の未反応部分を選択的に除去する。これにより、デュアルダマシン開口部8の内壁には、自己形成バリア膜11が露出された状態となる。   Thereafter, as shown in FIG. 6F, unreacted portions of the metal film 21 made of Mn (see 6 (e) above) are selectively removed. As a result, the self-formed barrier film 11 is exposed on the inner wall of the dual damascene opening 8.
次いで、図7(g)に示すように、上記デュアルダマシン開口部8の内壁を覆う状態で、自己形成バリア膜11上に、純Cuからなるシード層(図示省略)を成膜する。続いて、電解めっき法により、デュアルダマシン開口部8を埋め込む状態で、シード層上に純Cuからなる導電膜10を形成する。その後、必要に応じてN2雰囲気下にて、150℃〜400℃の熱処理を行い、導電膜10を構成するCu膜の結晶状態と膜ストレスを安定化させる。 Next, as shown in FIG. 7G, a seed layer (not shown) made of pure Cu is formed on the self-forming barrier film 11 so as to cover the inner wall of the dual damascene opening 8. Subsequently, a conductive film 10 made of pure Cu is formed on the seed layer by electrolytic plating while filling the dual damascene opening 8. Thereafter, a heat treatment at 150 ° C. to 400 ° C. is performed in an N 2 atmosphere as necessary to stabilize the crystal state and film stress of the Cu film constituting the conductive film 10.
続いて、図7(h)に示すように、CMP法により、配線パターンとして不要な部分の導電膜10(前記図7(g)参照)および自己形成バリア膜11を除去することで、上記配線溝8aに上層配線12を形成するとともに、接続孔8bにヴィア13を形成する。次いで、上層配線12上に、例えばSiC膜からなる酸化防止膜14を形成する。この後の工程は、上記図5(a)〜図7(h)を用いて説明した工程を繰り返すことで、デュアルダマシン構造の多層配線構造が形成される。   Subsequently, as shown in FIG. 7 (h), the conductive film 10 (see FIG. 7 (g)) and the self-formed barrier film 11 which are not necessary as a wiring pattern are removed by CMP to remove the wiring. The upper layer wiring 12 is formed in the groove 8a, and the via 13 is formed in the connection hole 8b. Next, an antioxidant film 14 made of, for example, a SiC film is formed on the upper layer wiring 12. In the subsequent steps, the multi-layer wiring structure having the dual damascene structure is formed by repeating the steps described with reference to FIGS. 5A to 7H.
このような半導体装置の製造方法であっても、デュアルダマシン開口部8の内壁を覆う状態で、金属膜21を形成し、金属膜21中のMnを保護絶縁膜22の構成成分と反応させて自己形成バリア膜11を形成した後、上記金属膜21の未反応部分を除去することから、第1実施形態と同様の効果を奏することができる。   Even in such a method for manufacturing a semiconductor device, the metal film 21 is formed in a state of covering the inner wall of the dual damascene opening 8, and Mn in the metal film 21 is reacted with the constituent components of the protective insulating film 22. Since the unreacted portion of the metal film 21 is removed after the self-forming barrier film 11 is formed, the same effect as in the first embodiment can be obtained.
また、本実施形態の半導体装置の製造方法によれば、デュアルダマシン開口部8の内壁を覆う状態で、保護絶縁膜22を形成することから、自己形成バリア膜11の密着性不良が無くなり、多孔質構造の無機絶縁層7a’や有機絶縁層7b’からの脱ガスが抑制される。これにより、脱ガスによる自己形成バリア膜11や上層配線12およびヴィア13の変質さらにはこれらに起因する導通不良、耐圧不良、信頼性不良等の不具合を抑制することができる。よって、高性能、高歩留まり、高信頼性の多層配線構造を提供することができる。   In addition, according to the method for manufacturing a semiconductor device of this embodiment, the protective insulating film 22 is formed in a state of covering the inner wall of the dual damascene opening 8, so that the self-forming barrier film 11 has no poor adhesion and is porous. Degassing from the inorganic insulating layer 7a ′ and the organic insulating layer 7b ′ having a quality structure is suppressed. As a result, the deterioration of the self-formed barrier film 11 and the upper layer wiring 12 and the via 13 due to degassing, and defects such as conduction failure, breakdown voltage failure, and reliability failure due to these can be suppressed. Therefore, it is possible to provide a multilayer wiring structure with high performance, high yield, and high reliability.
(第3実施形態)
次に、本発明の半導体装置の製造方法に係る第3の実施の形態を図8〜図9の製造工程断面図を用いて説明する。なお、第1実施形態と同様の構成には、同一の番号を付して説明する。また、以下の図8(a)〜図8(d)に示す工程は、第1実施形態で図1(a)〜図1(d)を用いて説明した工程と同様に行うこととする。
(Third embodiment)
Next, a third embodiment of the method for manufacturing a semiconductor device according to the present invention will be described using the manufacturing process sectional views of FIGS. In addition, the same number is attached | subjected and demonstrated to the structure similar to 1st Embodiment. Further, the following steps shown in FIGS. 8A to 8D are performed in the same manner as the steps described with reference to FIGS. 1A to 1D in the first embodiment.
図8(a)に示すように、酸化防止膜6上に、SiOC膜からなる低誘電材料層7aとSiO2層からなるハードマスク層7bを順次積層してなる層間絶縁膜7を形成し、配線溝8aと接続孔8bとからなるデュアルダマシン開口部8を形成する。 As shown in FIG. 8A, an interlayer insulating film 7 formed by sequentially laminating a low dielectric material layer 7a made of an SiOC film and a hard mask layer 7b made of an SiO 2 layer is formed on the antioxidant film 6. A dual damascene opening 8 composed of the wiring groove 8a and the connection hole 8b is formed.
次いで、図8(b)に示すように、デュアルダマシン開口部8の内壁を覆う状態で、ハードマスク層7b上に、Mnからなる金属膜21を形成し、図8(c)に示すように、N2雰囲気下にて熱処理を行うことにより、金属膜21中のMnと層間絶縁膜7の構成成分とを反応させて、金属膜21と層間絶縁膜7との界面に、2nm〜3nmのMn化合物からなる自己形成バリア膜11を形成する。その後、図8(d)に示すように、Mnからなる金属膜21(前記図8(c)参照)の未反応部分を選択的に除去する。これにより、デュアルダマシン開口部8の内壁に、自己形成バリア膜11が露出された状態となる。 Next, as shown in FIG. 8B, a metal film 21 made of Mn is formed on the hard mask layer 7b so as to cover the inner wall of the dual damascene opening 8, as shown in FIG. 8C. By performing a heat treatment in an N 2 atmosphere, the Mn in the metal film 21 reacts with the constituent components of the interlayer insulating film 7 so that the interface between the metal film 21 and the interlayer insulating film 7 has a thickness of 2 nm to 3 nm. A self-forming barrier film 11 made of a Mn compound is formed. Thereafter, as shown in FIG. 8D, the unreacted portion of the metal film 21 made of Mn (see FIG. 8C) is selectively removed. As a result, the self-formed barrier film 11 is exposed on the inner wall of the dual damascene opening 8.
次に、図9(e)に示すように、例えば指向性スパッタリング法により、自己形成バリア膜11が露出された形成されたデュアルダマシン開口部8の内壁を覆う状態で、ハードマスク層7b上に、1wt%のMnを含むCuMn合金膜からなるシード層9’を形成する。   Next, as shown in FIG. 9E, on the hard mask layer 7b in a state of covering the inner wall of the formed dual damascene opening 8 where the self-formed barrier film 11 is exposed, for example, by directional sputtering. A seed layer 9 ′ made of a CuMn alloy film containing 1 wt% Mn is formed.
次いで、図9(f)に示すように、電解めっき法により、デュアルダマシン開口部8を埋め込む状態で、シード層9’上に例えばCuからなる導電膜10を形成する。その後、必要に応じて、N2雰囲気下にて150℃〜400℃の熱処理を行い、導電膜10を構成するCu膜の結晶状態と膜ストレスを安定化させる。 Next, as shown in FIG. 9 (f), a conductive film 10 made of, for example, Cu is formed on the seed layer 9 ′ in a state where the dual damascene opening 8 is embedded by electrolytic plating. Thereafter, if necessary, heat treatment is performed at 150 ° C. to 400 ° C. in an N 2 atmosphere to stabilize the crystal state and film stress of the Cu film constituting the conductive film 10.
続いて、図9(g)に示すように、CMP法により、配線パターンとして不要な部分の導電膜10(前記図9(f)参照)および自己形成バリア膜11を除去することで、上記配線溝8aに上層配線12を形成するとともに、接続孔8bにヴィア13を形成する。   Subsequently, as shown in FIG. 9G, by removing the unnecessary portions of the conductive film 10 (see FIG. 9F) and the self-formed barrier film 11 as a wiring pattern by the CMP method, The upper layer wiring 12 is formed in the groove 8a, and the via 13 is formed in the connection hole 8b.
次いで、例えばCVD法により、上層配線12上およびハードマスク層7b上に、上層の層間絶縁膜15として、例えばSiOC膜を形成する。この際、成膜時の熱により、シード層9’中のMnと層間絶縁膜15の構成材料とが反応して、上層配線12と層間絶縁膜15との界面にMn化合物からなる自己形成バリア膜16を形成する。また、成膜時の熱による自己形成バリア膜16の形成が不十分である場合には、必要に応じて、250℃〜400℃の熱処理を行うことで、シード層9’中のMnと層間絶縁膜15の構成材料との反応を確実にしてもよい。   Next, an SiOC film, for example, is formed as the upper interlayer insulating film 15 on the upper wiring 12 and the hard mask layer 7b by, for example, the CVD method. At this time, Mn in the seed layer 9 ′ reacts with the constituent material of the interlayer insulating film 15 due to heat during film formation, and a self-forming barrier made of a Mn compound is formed at the interface between the upper wiring 12 and the interlayer insulating film 15. A film 16 is formed. In addition, when the formation of the self-forming barrier film 16 by heat at the time of film formation is insufficient, heat treatment at 250 ° C. to 400 ° C. is performed as necessary, so that Mn in the seed layer 9 ′ and the interlayer The reaction with the constituent material of the insulating film 15 may be ensured.
このような半導体装置の製造方法によれば、シード層9’がCuMn合金膜で構成されるため、上層配線12およびヴィア13に微量のMnが残留し、第1実施形態および第2実施形態と比較して、配線抵抗は高くなる。しかし、上層配線12と上層の層間絶縁膜15との界面にMn化合物からなる自己形成バリア膜16を形成することで、上層配線12の酸化および上層配線12からの層間絶縁膜15へのCuの拡散が防止されるため、比較的比誘電率の高い酸化防止膜14(前記図4(g)参照)の形成を省略することができる。これにより、第1実施形態の半導体装置と比較して配線間容量を低減することができ、RC遅延を抑制することができる。   According to such a method of manufacturing a semiconductor device, since the seed layer 9 ′ is composed of a CuMn alloy film, a small amount of Mn remains in the upper wiring 12 and the via 13, and the first embodiment and the second embodiment are the same. In comparison, the wiring resistance is increased. However, by forming a self-formed barrier film 16 made of a Mn compound at the interface between the upper wiring 12 and the upper interlayer insulating film 15, oxidation of the upper wiring 12 and Cu from the upper wiring 12 to the interlayer insulating film 15 are performed. Since diffusion is prevented, the formation of the antioxidant film 14 (see FIG. 4G) having a relatively high relative dielectric constant can be omitted. Thereby, compared with the semiconductor device of 1st Embodiment, the capacity | capacitance between wiring can be reduced and RC delay can be suppressed.
また、上述した第1実施形態から第3実施形態の半導体装置の製造方法では、デュアルダマシン構造を有する半導体装置の製造方法を例にとり説明したが、配線とヴィアとをそれぞれ別工程で形成するシングルダマシン構造を有する半導体装置の製造方法に適用してもよく、例えば、上記下層配線5と層間絶縁膜2との間のバリア膜4を形成する際にも本発明は適用可能である。   In the semiconductor device manufacturing method according to the first to third embodiments described above, a method for manufacturing a semiconductor device having a dual damascene structure has been described as an example. However, a single method for forming wirings and vias in separate processes is described. The present invention may be applied to a method for manufacturing a semiconductor device having a damascene structure. For example, the present invention can be applied to the formation of the barrier film 4 between the lower wiring 5 and the interlayer insulating film 2.
本発明の半導体装置の製造方法に係る第1実施形態を説明するための製造工程断面図(その1)である。FIG. 6 is a manufacturing process cross-sectional view (No. 1) for describing the first embodiment of the semiconductor device manufacturing method of the present invention; Mnのエリンガム図である。It is an Ellingham figure of Mn. Cuのエリンガム図である。It is an Ellingham figure of Cu. 本発明の半導体装置の製造方法に係る第1実施形態を説明するための製造工程断面図(その2)である。FIG. 6 is a manufacturing process sectional view (No. 2) for describing the first embodiment of the manufacturing method of the semiconductor device of the invention; 本発明の半導体装置の製造方法に係る第2実施形態を説明するための製造工程断面図(その1)である。It is manufacturing process sectional drawing (the 1) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法に係る第2実施形態を説明するための製造工程断面図(その2)である。It is manufacturing process sectional drawing (the 2) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法に係る第2実施形態を説明するための製造工程断面図(その3)である。It is manufacturing process sectional drawing (the 3) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法に係る第3実施形態を説明するための製造工程断面図(その1)である。It is manufacturing process sectional drawing for demonstrating 3rd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention (the 1). 本発明の半導体装置の製造方法に係る第3実施形態を説明するための製造工程断面図(その2)である。It is manufacturing process sectional drawing (the 2) for demonstrating 3rd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. 従来の半導体装置の製造方法を説明するための製造工程断面図(その1)である。It is manufacturing process sectional drawing (the 1) for demonstrating the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を説明するための製造工程断面図(その2)である。It is manufacturing process sectional drawing (the 2) for demonstrating the manufacturing method of the conventional semiconductor device.
符号の説明Explanation of symbols
5…下層配線、7,7’…層間絶縁膜、8…デュアルダマシン開口部、12…上層配線、13…ヴィア、21…金属膜、22…保護絶縁膜   5 ... Lower layer wiring, 7, 7 '... Interlayer insulating film, 8 ... Dual damascene opening, 12 ... Upper layer wiring, 13 ... Via, 21 ... Metal film, 22 ... Protective insulating film

Claims (3)

  1. 基板上の絶縁膜に設けられた凹部に銅を含む導電層を埋め込む半導体装置の製造方法において、
    前記基板上に設けられた前記絶縁膜に、前記基板に達する前記凹部を形成する第1工程と、
    前記凹部の内壁を覆う状態で、銅以外の金属からなる金属膜を形成する第2工程と、
    熱処理を行い、前記金属膜中の前記金属を前記絶縁膜の構成成分と反応させて、前記金属膜と前記絶縁膜との界面に、前記導電層からの銅の拡散を防止する金属化合物からなるバリア膜を形成する第3工程と、
    前記金属膜の未反応部分を選択的に除去する第4工程と、
    前記未反応部分が除去された前記凹部に、前記導電層を埋め込む第5工程とを有する
    ことを特徴とする半導体装置の製造方法。
    In a method for manufacturing a semiconductor device in which a conductive layer containing copper is embedded in a recess provided in an insulating film on a substrate,
    A first step of forming the recess reaching the substrate in the insulating film provided on the substrate;
    A second step of forming a metal film made of a metal other than copper in a state of covering the inner wall of the recess;
    A metal compound that prevents heat diffusion of the copper from the conductive layer at the interface between the metal film and the insulating film by reacting the metal in the metal film with a component of the insulating film by performing a heat treatment. A third step of forming a barrier film;
    A fourth step of selectively removing unreacted portions of the metal film;
    And a fifth step of embedding the conductive layer in the recess from which the unreacted portion has been removed. A method for manufacturing a semiconductor device, comprising:
  2. 請求項1記載の半導体装置の製造方法において、
    前記絶縁膜が多孔質膜を含んでおり、
    前記第1工程と前記第2工程との間に、
    前記凹部の底部を除く当該凹部の内壁を覆う状態で、保護絶縁膜を形成する工程を行い、
    前記第3工程では、熱処理を行い、前記金属膜中の前記金属を前記保護絶縁膜の構成成分と反応させて、前記金属膜と前記保護絶縁膜との界面に、前記バリア膜を形成する
    ことを特徴とする半導体装置の製造方法。
    In the manufacturing method of the semiconductor device according to claim 1,
    The insulating film includes a porous film;
    Between the first step and the second step,
    In a state of covering the inner wall of the concave portion excluding the bottom of the concave portion, performing a step of forming a protective insulating film,
    In the third step, heat treatment is performed to react the metal in the metal film with a component of the protective insulating film, thereby forming the barrier film at the interface between the metal film and the protective insulating film. A method of manufacturing a semiconductor device.
  3. 請求項1記載の半導体装置の製造方法において、
    前記第4工程と前記第5工程の間に、
    前記凹部の内壁を覆う状態で、銅と銅以外の金属とからなる合金膜を形成する工程を行い、
    前記第5工程の後に、前記導電層上および前記絶縁膜上に、上層絶縁膜を形成し、熱処理を行うことで、前記合金膜中の銅以外の前記金属と前記上層絶縁膜の構成成分とを反応させて、前記導電層と前記上層絶縁膜との界面に、当該導電層からの銅の拡散を防止する金属化合物からなるバリア膜を形成する
    ことを特徴とする半導体装置の製造方法。
    In the manufacturing method of the semiconductor device according to claim 1,
    Between the fourth step and the fifth step,
    In a state of covering the inner wall of the recess, performing a process of forming an alloy film made of copper and a metal other than copper,
    After the fifth step, an upper insulating film is formed on the conductive layer and the insulating film, and heat treatment is performed, so that the metal other than copper in the alloy film and the components of the upper insulating film are To form a barrier film made of a metal compound that prevents diffusion of copper from the conductive layer at the interface between the conductive layer and the upper insulating film.
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