JP2008010534A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily form a wiring having an air gap structure not depending on dense/coarse performance of a wiring without adding a complicated/long-time process. <P>SOLUTION: A semiconductor device 1 is provided with cavities 20 formed by removing a first insulating film formed on a substrate; a second insulating film 13 positioned over the cavity 20 and formed on the first insulating film; and a wiring 17 formed via a barrier film 15 so as to reach the substrate from the wiring trench 14 formed on the second insulating film 13. The semiconductor device 1 is provided with a slit 18 continuing to the cavity 20 on the side wall of the wiring 17. The slit 18 reaching the first insulating film is formed on the side wall of the wiring 17 in a process of removing excessive materials of the second insulating film 13, and the first insulating film is removed from the slit 18 to form the cavity 20 on the region where the film is removed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a trench wiring structure in which a cavity is provided in a lower part of a wiring, and a manufacturing method thereof.

  Along with the miniaturization of wiring due to high integration of LSIs, signal delay time has increased due to an increase in inter-wiring capacitance. In recent years, fine multilayers using low dielectric constant films (low-k films) have become a problem. Wiring is essential. As a material for the low dielectric constant film, not only fluorine-containing silicon oxide (FSG) having a relative dielectric constant of about 3.5, which has been relatively proven in the past, but also an organic silicon polymer represented by polyaryl ether (PAE) And a low dielectric constant film having a relative dielectric constant of about 2.7 such as an inorganic material typified by hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). Furthermore, an interlayer insulating film having a lower dielectric constant is required for LSI wiring of the 45 nm generation and later. In recent years, the low dielectric constant film is made porous so that the relative dielectric constant is 2. Attempts have been made to introduce about 2 materials.

  A so-called air gap wiring is attracting attention as a configuration for further reducing the capacitance as compared with the wiring using the low dielectric constant film as described above. The air gap wiring is a wiring structure in which an air or vacuum cavity region is formed in an interlayer insulating film portion. For example, a wiring using aluminum (Al) can be formed by the following method.

  After forming the aluminum wiring, a dummy insulating film to be removed later is embedded between the aluminum wirings, and planarized by chemical mechanical polishing (CMP) or the like until the aluminum wiring is exposed. Subsequently, the aspect is further reduced by etch back, and then a dummy insulating film and an insulating film to be a bridge film are stacked on the wiring, and then the dummy insulating film is removed by utilizing some reaction. A method is adopted in which a space formed by removing the dummy insulating film is used as an air gap (see, for example, Patent Document 1).

  For copper (Cu) wiring, for example, air gap wiring is formed by the following method. After Cu wiring is formed on a dual damascene structure using a dummy insulating film to be removed later, the dummy insulating film between the wirings is removed by etch back, and then an insulating film is formed under conditions with poor coverage. As a result, an air gap wiring having a void region such as a void can be formed between the wiring layers (see, for example, Non-Patent Document 1).

  In any method, since a vacuum region with a dielectric constant (k) = 1 is provided, dramatic capacity reduction can be achieved. However, a dummy insulating film is formed, and an insulating film with poor coverage is formed. Compared with the wiring formation process that does not have an air gap structure, such as a subsequent process and a flattening process, a process that is complicated and has a long TAT (Turn Around Time) is added, resulting in an increase in manufacturing cost. Occurs. Furthermore, it is difficult to control the coverage of the insulating film when forming the air gap structure. Specifically, since there is generally a difference in density between wiring structures, an air gap structure is likely to be formed in a relatively dense area because pinch-off is likely due to a decrease in coverage, but insulation is provided in a relatively sparse area. Since the film is formed conformally, it is very difficult to form an air gap structure.

Japanese Patent No. 8-306775 “Dual Damascene Process for Air-Gap Cu Interconnects Using Conventional CVD Films as Sacrificial Layers” IEEE IITC (International Interconnect Technology Conference) 2005 p.174-176 2005

  The problem to be solved is that it is very difficult to form an air gap structure because an insulating film is formed conformally in a relatively sparse wiring structure region. The formation process is complicated and TAT is long.

  It is an object of the present invention to easily form a wiring having an air gap structure that does not depend on wiring density without adding complicated and long-time processes.

  A semiconductor device of the present invention includes a cavity formed by removing a first insulating film formed on a substrate, a second insulating film formed on the first insulating film and on the cavity, and the first (2) A semiconductor device including a wiring formed through a barrier film so as to reach the substrate from a wiring groove formed in an insulating film, wherein a slit connected to the cavity is provided in the wiring side wall. To do.

  In the semiconductor device of the present invention, since the slit connected to the cavity is provided on the wiring side wall, the cavity can be formed without depending on the density of the wiring by removing the first insulating film from the slit.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first insulating film on a substrate; and forming a second insulating film made of a material different from the first insulating film on the first insulating film; Forming a groove in the insulating film and the first insulating film, and then embedding a wiring material in the groove through a barrier film; and removing excess material on the second insulating film; Forming a wiring made of the wiring material through a barrier film, wherein a step of removing excess material on the second insulating film in the wiring sidewall A slit reaching one insulating film is formed, and the first insulating film is removed from the slit to form a cavity in the removal region.

  In the method for manufacturing a semiconductor device according to the present invention, the slit is formed in the wiring side wall in the step of removing the excess material on the second insulating film, so that there is no increase in the number of steps for forming the slit. Further, since the first insulating film is removed from the slit, a cavity is formed without depending on the density of the wiring.

  According to the semiconductor device of the present invention, since the first insulating film is removed from the slit formed in the sidewall of the wiring to form a cavity, the air gap structure that does not depend on the density of the wiring is provided. Can be reduced. This has the advantage that it is possible to provide a high-performance semiconductor device.

  According to the method for manufacturing a semiconductor device of the present invention, since the first insulating film is removed from the slit formed in the side wall of the wiring to form the cavity, the air gap structure can be formed without depending on the density of the wiring. Therefore, a wiring structure with reduced wiring capacitance can be easily formed. This has the advantage that it is possible to provide a high-performance semiconductor device.

  An embodiment (first example of a semiconductor device) according to the semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG.

  As shown in FIG. 1, a cavity 20 is formed by removing a first insulating film (not shown) formed on a base 11 formed on a base (not shown). This first insulating film is formed of, for example, an organic insulating film. This organic insulating film is, for example, a polyaryl ether film, and is formed to a thickness of, for example, 100 nm. A second insulating film 13 formed on the first insulating film is formed on the cavity 20. The second insulating film 13 is a silicon carbide oxide (SiOC) film, for example, and has a thickness of 150 nm, for example. A wiring groove 14 is formed in the second insulating film 13, and a wiring 17 is formed in the wiring groove 14 through the barrier film 15 so as to reach the base 11. The barrier film 15 is made of, for example, a tantalum (Ta) film. The barrier film 15 is not limited to a tantalum (Ta) film, and any barrier film may be used as long as it prevents diffusion of a material forming the wiring and prevents oxygen from entering the wiring 17. A slit 18 connected to the cavity 20 is formed between the side walls of the wiring 17, specifically, between the barrier film 15 and the second insulating film 13. Since the slits 18 are formed intermittently, a part of the second insulating film 13 is supported by the wiring 17 through the barrier film 15 and therefore does not fall.

  The second insulating film 13 preferably has a film thickness ratio of 1 or more for the polyaryl ether film and the silicon carbide oxide film so that the slit 18 can be easily formed by chemical mechanical polishing. Therefore, in this embodiment, the setting is made as described above.

  The first insulating film and the second insulating film 13 are formed of insulating films of different materials. For example, the first insulating film and the second insulating film 13 are formed of a material that selectively etches the first insulating film while leaving the second insulating film 13. And what is necessary is just to form the slit 18 at the time of chemical mechanical polishing. For example, the first insulating film can be formed of an organic insulating film, and the second insulating film 13 can be formed of an inorganic insulating film. In the above example, a polyaryl ether film is used for the organic insulating film, and a silicon carbide (SiOC) film is used for the inorganic insulating film, but a polyimide insulating film, a polyamide insulating film, etc. are used for the organic insulating film. Such an organic insulating film may be used, and the inorganic insulating film may be another inorganic insulating film such as a silicon carbonitride film.

  An insulating film 21 for preventing copper diffusion is formed on the wiring 17. Usually, for example, a silicon carbide nitride film (SiCN) is used for the insulating film 21 and is formed to a thickness of, for example, 50 nm.

  In the semiconductor device 1 of the present invention, since the slit 18 connected to the cavity 20 is formed on the side wall of the wiring 17, the first insulating film is removed from the slit 18 without depending on the density of the wiring 17. The cavity 20 can be formed. As described above, since the air gap structure does not depend on the density of wiring, the capacitance between wirings can be reduced. As a result, the signal delay can be reduced, so that it is possible to provide a high-speed and high-performance semiconductor device.

  Next, an embodiment (first example of the manufacturing method) according to the manufacturing method of the semiconductor device of the present invention will be described with reference to the manufacturing process sectional views of FIGS.

As shown in FIG. 2A, a first insulating film 12 is formed on a base 11 formed on a base (not shown). The first insulating film 12 is, for example, a polyaryl ether film, and is formed to a thickness of, for example, 100 nm. This polyaryl ether film can be formed, for example, by applying a precursor of polyaryl ether by a spin coating method and then performing a curing process at 350 ° C. for 60 minutes. Further, a second insulating film 13 serving as a hard mask is formed on the first insulating film 12. The second insulating film 13 is a silicon carbide oxide (SiOC) film, for example, and is formed to a thickness of 150 nm, for example. This SiOC film is formed using, for example, a parallel plate type plasma CVD apparatus and using methylsilane (SiCH ₃ ) as a silicon source.

  Here, the second insulating film 13 preferably has a film thickness ratio of 1 or more for the polyaryl ether film and the silicon carbide oxide film in order to facilitate the formation of slits during subsequent chemical mechanical polishing. In this embodiment, the setting is made as described above.

  The first insulating film 12 and the second insulating film 13 are formed of insulating films of different materials. For example, the first insulating film 12 is formed of a material by which the first insulating film 12 is selectively etched leaving the second insulating film 13. What is necessary is just a thing in which a slit is formed at the time of subsequent chemical mechanical polishing. For example, the first insulating film 12 can be formed of an organic insulating film, and the second insulating film 13 can be formed of an inorganic insulating film. In the above example, a polyaryl ether film is used for the organic insulating film, and a silicon carbide (SiOC) film is used for the inorganic insulating film, but a polyimide insulating film, a polyamide insulating film, etc. are used for the organic insulating film. Such an organic insulating film may be used, and the inorganic insulating film may be another inorganic insulating film such as a silicon carbonitride film.

Next, as shown in FIG. 2B, wiring grooves 14 are formed in the second insulating film 13 and the first insulating film 12 using a resist mask (not shown) having a wiring groove pattern. The SiOC film of the second insulating film 13 is processed by using a mixed gas of octafluorobutane (C ₄ F ₈ ) and argon (Ar) as an etching gas with a general magnetron etching apparatus, and bias power is increased. Set to 400W. The gas flow rate ratio is, for example, C ₄ F ₈ : Ar = 1: 4, and the substrate temperature is set to 20 ° C. The polyaryl ether film is etched using, for example, a general high-density plasma etching apparatus, for example, using ammonia (NH ₃ ) as an etching gas. The RF power is set to 150 W and the base temperature is set to 10 ° C. Since the etching rate of the wiring groove pattern resist under this etching condition is almost equal to the etching rate of the polyaryl ether film, the resist mask recedes into the opening of the polyaryl ether film, but the hard mask 13 made of SiOC. Therefore, the wiring groove 14 can obtain a favorable opening shape. Thereafter, the wiring groove 14 is completed by washing with an appropriate chemical solution.

  Next, as shown in FIG. 3 (3), after performing an appropriate degassing process, a barrier film 15 is formed on the inner surface of the wiring groove 14. The barrier film 15 serves as a diffusion preventing film for the second insulating film 13 of the copper wiring, and is formed, for example, by depositing tantalum (Ta) to a thickness of 10 nm, for example. For example, the film is formed by a directional sputtering method using a tantalum target using a general magnetron sputtering apparatus.

  Next, a wiring material 16 made of copper or an alloy containing copper is embedded in the wiring groove 14 via a barrier film 15. The wiring material is formed using, for example, an electrolytic plating method, a sputtering method, or a CVD method. When the electrolytic plating method is used, a layer (not shown) serving as a copper plating seed is formed on the inner surface of the wiring groove 14 in advance. In this case, the barrier film 15 needs to be formed in the wiring groove 14 with good coverage, and a directional sputtering method such as a self-discharge ionization sputtering method or a long-distance sputtering method is preferably used. Further, it is desirable that the thickness of the barrier film 15 be 10 nm or more in order to facilitate the formation of slits during subsequent chemical mechanical polishing. In this example, it was set to 10 nm.

  Next, as shown in FIG. 3D, the excess wiring material 16 and the barrier film 15 on the first insulating film 12 are removed. For this removal processing, for example, chemical mechanical polishing is used. As a result, the wiring 17 made of the wiring material 16 is formed in the wiring groove 14 via the barrier film 15.

  At this time, as shown in FIG. 4 (5), the thicknesses of the polyaryl ether film of the first insulating film 12, the SiOC film of the second insulating film 13, and the tantalum film of the barrier film 15 are set as described above. As a result, when the barrier film 15 on the first insulating film 12 is removed during chemical mechanical polishing, the barrier film 15 on the side wall of the wiring 17 and the second insulating film 13 are released by releasing the film stress of the barrier film 15. In the middle, a slit 18 reaching the first insulating film 12 is formed. The slit 18 is characterized by being formed intermittently. The point here is that the slit 18 is formed without adding a special process. A copper oxide film 19 is formed on the surface of the wiring 17.

Next, as shown in FIG. 4 (6), pre-processing is performed for the purpose of removing the copper oxide film 19 [see FIG. 4 (5)] on the surface of the wiring 17. This pretreatment uses, for example, ammonia (NH ₃ ) plasma. By this plasma treatment, the copper oxide film on the surface of the wiring 17 is reduced and removed. At the same time, the polyaryl ether film of the first insulating film 12 is removed through the slit 18 to form a cavity (air gap) 20. Thus, since the formation process of the cavity 20 is removal of the polyaryl ether film through the slit 18, a special process can be added easily and reliably without depending on the density of the wiring 17. Therefore, it is possible to form an air gap structure.

  Next, as shown in FIG. 4 (7), following the pretreatment, an insulating film 21 that prevents diffusion of copper is formed so as to cover the wiring 17. Usually, for example, a silicon carbide nitride film (SiCN) is used for the insulating film 21 and is formed to a thickness of, for example, 50 nm. By performing the above steps, a copper wiring having an air gap structure can be formed.

  In the manufacturing method of the first embodiment, polyaryl ether is used as the organic insulating film of the first insulating film 12, but any material can be used as long as it is etched (removed) by plasma used as a pretreatment of the insulating film 21. Such an organic insulating film can also be applied. In addition, although the SiOC film is used as the second insulating film 13 serving as a cap film on the organic insulating film, any inorganic insulating film can be applied as long as it has a sufficient processing selectivity with respect to PAE. However, in order to efficiently form slits, a film having compressive stress is desirable.

  In the manufacturing method (first embodiment), the slit 18 is formed on the side wall of the wiring 17 in the step of removing the excess material on the second insulating film 13, so that the number of steps for forming the slit 18 is not increased. . Further, since the first insulating film 12 is removed from the slit 18, the cavity 20 is formed without depending on the density of the wiring 17. Thus, since an air gap structure that does not depend on the density of the wirings 17 can be formed, a wiring structure with reduced inter-wiring capacitance can be formed. As a result, the signal delay can be reduced, so that it is possible to provide a high-speed and high-performance semiconductor device.

  An embodiment (second example of a semiconductor device) according to a semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG.

As shown in FIG. 5, a cavity 20 is formed by removing a first insulating film (not shown) formed on a base 11 formed on a base (not shown). This first insulating film is formed of, for example, an organic insulating film. This organic insulating film is, for example, a polyaryl ether film, and is formed to a thickness of, for example, 100 nm. A second insulating film 13 formed on the first insulating film is formed on the cavity 20. The second insulating film 13 is a silicon carbide oxide (SiOC) film, for example, and has a thickness of 150 nm, for example. A wiring groove 14 is formed in the second insulating film 13, and a wiring 17 is formed in the wiring groove 14 through the barrier film 15 so as to reach the base 11. The barrier film 15 is formed of, for example, a silicon-containing manganese oxide (MnSi _x O _y ) film. The barrier film 15 is not limited to the silicon-containing manganese oxide film, and may be any film that prevents diffusion of the material forming the wiring and prevents oxygen from entering the wiring 17. A slit 18 connected to the cavity 20 is formed on the side wall of the wiring 17. Since the slits 18 are formed intermittently, the second insulating film 13 is supported by the wiring 17 via the barrier film 15 and therefore does not fall.

  The first insulating film and the second insulating film 13 are formed of insulating films of different materials. For example, the first insulating film and the second insulating film 13 are formed of a material that selectively etches the first insulating film while leaving the second insulating film 13. Any part of the barrier film 15 may be etched to form the slit 18 during chemical mechanical polishing. For example, the first insulating film can be formed of an organic insulating film, and the second insulating film 13 can be formed of an inorganic insulating film. In the above example, a polyaryl ether film is used for the organic insulating film, and a silicon carbide (SiOC) film is used for the inorganic insulating film, but a polyimide insulating film, a polyamide insulating film, etc. are used for the organic insulating film. Such an organic insulating film may be used, and the inorganic insulating film may be another inorganic insulating film such as a silicon carbonitride film.

  An insulating film 21 for preventing copper diffusion is formed on the wiring 17. Usually, for example, a silicon carbide nitride film (SiCN) is used for the insulating film 21 and is formed to a thickness of, for example, 50 nm.

  In the semiconductor device 2 of the present invention, the slit 18 connected to the cavity 20 is provided on the side wall of the wiring 17, so that the cavity 20 can be removed without depending on the density of the wiring 17 by removing the first insulating film from the slit 18. Can be formed. As described above, since the air gap structure does not depend on the density of wiring, the capacitance between wirings can be reduced. As a result, the signal delay can be reduced, so that it is possible to provide a high-speed and high-performance semiconductor device.

  Next, an embodiment (second example of the manufacturing method) according to the manufacturing method of the semiconductor device of the present invention will be described with reference to the manufacturing process cross-sectional views of FIGS.

As shown in FIG. 6A, a first insulating film 12 is formed on a base 11 formed on a base (not shown). The first insulating film 12 is, for example, a polyaryl ether film, and is formed to a thickness of, for example, 100 nm. This polyaryl ether film can be formed, for example, by applying a precursor of polyaryl ether by a spin coating method and then performing a curing process at 350 ° C. for 60 minutes. Further, a second insulating film 13 serving as a hard mask is formed on the first insulating film 12. The second insulating film 13 is a silicon carbide oxide (SiOC) film, for example, and is formed to a thickness of 150 nm, for example. This SiOC film is formed using, for example, a parallel plate type plasma CVD apparatus and using methylsilane (SiCH ₃ ) as a silicon source.

  The first insulating film 12 and the second insulating film 13 are formed of insulating films of different materials. For example, the first insulating film 12 is formed of a material by which the first insulating film 12 is selectively etched leaving the second insulating film 13. Anything is acceptable. For example, the first insulating film 12 can be formed of an organic insulating film, and the second insulating film 13 can be formed of an inorganic insulating film. In the above example, a polyaryl ether film is used for the organic insulating film, and a silicon carbide (SiOC) film is used for the inorganic insulating film, but a polyimide insulating film, a polyamide insulating film, etc. are used for the organic insulating film. Such an organic insulating film may be used, and the inorganic insulating film may be another inorganic insulating film such as a silicon carbonitride film.

Next, as shown in FIG. 6B, wiring grooves 14 are formed in the second insulating film 13 and the first insulating film 12 using a resist mask (not shown) having a wiring groove pattern. The SiOC film of the second insulating film 13 is processed by using a mixed gas of octafluorobutane (C ₄ F ₈ ) and argon (Ar) as an etching gas with a general magnetron etching apparatus, and bias power is increased. Set to 400W. The gas flow rate ratio is, for example, C ₄ F ₈ : Ar = 1: 4, and the substrate temperature is set to 20 ° C. The polyaryl ether film of the first insulating film 12 is etched using, for example, a general high-density plasma etching apparatus, for example, using ammonia (NH ₃ ) as an etching gas. The RF power is set to 150 W and the base temperature is set to 10 ° C. Since the etching rate of the wiring groove pattern resist under this etching condition is almost equal to the etching rate of the polyaryl ether film, the resist mask recedes into the opening of the polyaryl ether film, but the second insulation made of SiOC. Since the film 13 is present, the wiring groove 14 can obtain a favorable opening shape. Thereafter, the wiring groove 14 is completed by washing with an appropriate chemical solution.

  Next, as shown in FIG. 7 (3), after performing an appropriate degassing process, a manganese-containing copper (CuMn) film 31 is sputtered as a seed layer for forming copper as a wiring material by electrolytic plating. The film is formed by the method. The formation of the CuMn film here needs to be formed on the inner surface of the wiring groove 14 with good coverage, and preferably a directional sputtering method such as a self-discharge ionization sputtering method or a long-distance sputtering method is used. In this example, a film having a thickness of 60 nm was formed by a directional sputtering method using a copper (Cu) target containing 5% manganese (Mn). Subsequently, the wiring material 16 is formed of copper (Cu) by electroplating, sputtering, or CVD.

Next, as shown in FIG. 7 (4), heat treatment is performed to react manganese (Mn) in the manganese-containing copper (CuMn) film 31 with silicon in the second insulating film 13 to obtain copper (Cu ), A barrier film 32 made of a silicon-containing manganese oxide film (MnSi _x O _y ) having a high barrier property is formed in a self-aligning manner. The heat treatment is performed, for example, at an annealing temperature of 300 ° C. in an atmosphere of 100% nitrogen (N ₂ ). The generation mechanism of the silicon-containing manganese oxide film is disclosed in, for example, the 65th JSAP Preliminary Proceedings p711, “New Alloy Element for Formation of Self-Diffusion Barrier Layer in Copper Wiring”. Further, in the heat treatment, manganese that cannot be reacted is deposited on the surface of the wiring material 16 to form a manganese layer 33. Note that the manganese-containing copper (CuMn) film (not shown) may remain on the wiring material 16 side of the barrier film 32.

  Next, as shown in FIG. 8 (5), the excess wiring material 16 and the manganese layer 33 (see FIG. 7 (4)) and the barrier film 32 on the second insulating film 13 are removed. For this removal processing, for example, chemical mechanical polishing is used. As a result, the wiring 17 made of the wiring material 16 is formed in the wiring groove 14 via the barrier film 32. In this chemical mechanical polishing, by using an alkaline slurry having a pH of 9 or more, the barrier film 32 made of a silicon-containing manganese oxide film is etched, so that between the wiring 17 side wall and the second insulating film 13 made of SiOC, A slit 18 reaching the first insulating film 12 is formed. The slit 18 is characterized by being formed intermittently. The point here is that the slit 18 can be formed without adding a special process. A copper oxide film 19 is formed on the surface of the wiring 17.

Next, as shown in FIG. 8 (6), pre-processing is performed for the purpose of removing the copper oxide film 19 [see FIG. 8 (5)] on the surface of the wiring 17. This pretreatment uses, for example, ammonia (NH ₃ ) plasma. By this plasma treatment, the copper oxide film 19 on the surface of the wiring 17 is reduced and removed. At the same time, the polyaryl ether film of the first insulating film 12 [see FIG. 8 (5)] is removed through the slit 18, and a cavity (air gap) 20 is formed. Thus, since the formation process of the cavity 20 is removal of the polyaryl ether film through the slit 18, a special process can be added easily and reliably without depending on the density of the wiring 17. Therefore, it is possible to form an air gap structure.

  Next, as shown in FIG. 8 (7), following the pretreatment, an insulating film 21 for preventing copper diffusion is formed so as to cover the wiring 17. Usually, for example, a silicon carbide nitride film (SiCN) is used for the insulating film 21 and is formed to a thickness of, for example, 50 nm. By performing the above steps, a copper wiring having an air gap structure can be formed.

  According to the above manufacturing method (second embodiment), polyaryl ether is used as the organic insulating film of the first insulating film 12, but any material that is etched (removed) by plasma used as a pretreatment of the insulating film 21 may be used. Any organic insulating film can be applied. In addition, although the SiOC film is used as the second insulating film 13 serving as a cap film on the organic insulating film, any inorganic insulating film can be used as long as the processing selectivity with the organic insulating film is sufficiently high. Can do.

  Moreover, although CuMn was used as the seed layer, any combination can be used as long as the slit can be generated by the slurry. For example, if titanium (Ti) is used instead of CuMn and an acidic material containing hydrofluoric acid (HF) is used for the slurry, the same slit and air gap structure can be formed. Further, the barrier metal does not have to be a single layer. For example, if a tantalum (Ta) film is formed after forming CuMn, a wiring having a barrier film can be formed inside the slit 18 (wiring side). It is possible to provide a semiconductor device with higher reliability.

  In the above manufacturing method (second embodiment), the slit 18 is formed on the side wall of the wiring 17 in the process of removing the excess material on the second insulating film 13, so that the number of processes for forming the slit 18 is not increased. . Further, since the first insulating film 12 is removed from the slit 18, the cavity 20 is formed without depending on the density of the wiring 17. Thus, since an air gap structure that does not depend on the density of the wirings 17 can be formed, a wiring structure with reduced inter-wiring capacitance can be formed. As a result, the signal delay can be reduced, so that it is possible to provide a high-speed and high-performance semiconductor device.

  An embodiment (third example of a semiconductor device) according to the semiconductor device of the present invention will be described with reference to the schematic configuration cross-sectional view of FIG.

  As shown in FIG. 9, a wiring layer insulating film 42 is formed on a base 41 formed on a substrate (not shown). The wiring layer insulating film 42 is formed of, for example, a laminated film of a polyaryl ether film and a silicon carbide oxide (SiOC) film. A first wiring 44 made of copper (Cu) is formed on the wiring layer insulating film 12 via a barrier film 43. Here, the first wiring 44 is formed to have a height of 150 nm, and a stopper film 45 for preventing copper diffusion and oxidation is formed on the first wiring 44. The stopper film 45 is formed, for example, by forming a silicon carbonitride (SiCN) film to a thickness of 35 nm, for example.

  On the stopper film 45, an insulating film 46 for forming wiring grooves and connection holes is formed. The insulating film 16 is, for example, a silicon carbide oxide (SiOC) film having a thickness of, for example, 150 nm, forming a connection hole, and having a thickness of, for example, 150 nm. For example, a silicon carbide oxide (SiOC) film is formed with a thickness of, for example, 80 nm.

A wiring groove 49 is formed in the second insulating film 463 of the insulating film 46, and a connection hole 50 is formed in the insulating film 461 that forms a connection hole below the wiring groove 49. A second wiring 54 is formed in the wiring groove 49 through the barrier film 52 so as to reach the insulating film 461 that forms the connection hole, and the side wall portion is formed in the connection hole 50 below the second wiring 54. In addition, a plug 55 connected to the first wiring 44 is formed continuously to the second wiring 54 through the barrier film 52. The barrier film 52 is formed of, for example, a silicon-containing manganese oxide (MnSi _x O _y ) film. The barrier film 52 is not limited to the silicon-containing manganese oxide film, and any barrier film may be used as long as it prevents diffusion of the material forming the wiring and prevents oxygen from entering the wiring material. In addition, slits 56 connected to the cavity 58 are formed intermittently on the side wall of the second wiring 54. Since the slits 56 are formed intermittently, the second insulating film 463 is supported by the wiring 54 via the barrier film 52 and therefore does not fall.

  In this embodiment, the slit 56 is formed by removing a part of the barrier film 52. However, as in the first embodiment, the slit 56 is provided between the barrier film 52 and the second insulating film 463. Is also possible.

  On the second wiring 54, an insulating film 59 for preventing diffusion of copper is formed. Usually, for example, a silicon carbide nitride film (SiCN) is used for the insulating film 59 and formed to a thickness of, for example, 50 nm.

  In the semiconductor device 3 of the present invention, since the slit 56 connected to the cavity 58 is formed on the side wall of the second wiring 54, the first insulating film is removed from the slit 56 and depends on the density of the second wiring 54. Without this, the cavity 58 can be formed. As described above, since the air gap structure does not depend on the density of wiring, the capacitance between wirings can be reduced. As a result, the signal delay can be reduced, so that it is possible to provide a high-speed and high-performance semiconductor device.

  Next, an embodiment (third example of the manufacturing method) according to the method for manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process sectional views of FIGS.

As shown in FIG. 10A, a wiring layer insulating film 42 is formed on a base 41 formed on a base (not shown). The wiring layer insulating film 42 is formed of, for example, a laminated film of a polyaryl ether film and a silicon carbide oxide (SiOC) film. A first wiring 44 made of copper (Cu) is formed on the wiring layer insulating film 12 through a barrier film 43. Here, the first wiring 44 is formed to have a height of 150 nm, and a stopper film 45 that prevents copper diffusion and oxidation is formed on the first wiring 44. The stopper film 45 is formed, for example, by forming a silicon carbonitride (SiCN) film with a thickness of 35 nm, for example, and also functions as an etching stopper in a later process. The SiCN film is formed by using, for example, a parallel plate type plasma CVD apparatus, using methylsilane (SiCH ₃ ) as a silicon source, a pressure of 550 Pa, and a plasma power of 200 W.

Subsequently, an insulating film 46 for forming wiring grooves and connection holes is formed on the stopper film 45. In this insulating film 16, for example, an insulating film 461 that forms a connection hole is formed of, for example, a silicon carbide oxide (SiOC) film, a first insulating film 462 that forms wiring is formed of, for example, a polyaryl ether film, The two insulating film 463 is formed of, for example, a silicon carbide oxide (SiOC) film. As described above, the insulating film 46 is formed of a stacked film of the insulating film 461 that forms the connection hole, the first insulating film 462, and the second insulating film 463. The insulating film 461 for forming the connection hole is a silicon carbide oxide (SiOC) film having a thickness of, for example, 150 nm. The silicon carbide oxide film 461 uses, for example, a parallel plate type plasma CVD apparatus, and uses methylsilane (SiCH ₃ ) as a silicon source in the source gas. The polyaryl ether film of the first insulating film 462 is formed by applying a precursor of polyaryl ether by a spin coating method and then performing a curing process at 350 ° C. for 30 minutes, for example. The silicon carbide oxide (SiOC) film of the second insulating film 463 is formed with a thickness of 80 nm, for example. This silicon carbide oxide film uses, for example, a parallel plate type plasma CVD apparatus, and uses methylsilane (SiCH ₃ ) as a silicon source in the source gas. The second insulating film 463 also functions as a hard mask in a later etching process.

  Further, a first hard mask 47 and a second hard mask 48 are stacked on the insulating film 46. The first hard mask 47 is formed of, for example, a silicon nitride (SiN) film, and the second hard mask 48 is formed of, for example, a silicon oxide film.

  Next, as shown in FIG. 10B, wiring is performed on the laminated hard mask such as the second hard mask 48 [see FIG. 10 (1)] and the first hard mask 47 [see FIG. 10 (1)]. After the groove 49 is opened, the connection hole 50 is opened in the middle, and then the wiring groove 49 and the connection hole 50 are completely opened using the second hard mask 48 and the first hard mask 47. In this manner, the wiring groove 49 and the connection hole 50 are formed in the insulating film 46 at the bottom of the wiring groove 49, thereby obtaining a so-called dual damascene structure. That is, the wiring groove 49 is formed in the silicon carbide oxide film 463 and the polyaryl ether film 462, and the connection hole 50 is formed in the silicon carbide oxide film 461. Then, the stopper film 45 at the bottom of the connection hole 50 is removed.

  Next, as shown in FIG. 11 (3), after performing an appropriate degassing process, a manganese-containing copper film (CuMn) 61 is sputtered as a seed layer for forming copper as a wiring material by electrolytic plating. The film is formed by the method. The formation of the CuMn film here needs to be formed with good coverage on the inner surfaces of the wiring groove 49 and the connection hole 50, and preferably a directional sputtering method such as a self-discharge ionization sputtering method or a long-distance sputtering method is used. Is good. In this example, a film having a thickness of 60 nm was formed by a directional sputtering method using a copper (Cu) target containing 5% manganese (Mn). Subsequently, the wiring material 51 is formed of copper (Cu) by electroplating, sputtering, or CVD.

Next, as shown in FIG. 11 (4), a heat treatment is performed to manufacture manganese (Mn) in the manganese-containing copper film (CuMn) 61 [see FIG. 11 (3)] and the insulating film 46 (silicon carbide oxide film). 461, 463) and the silicon in the stopper film 45 are reacted to form a barrier film 52 made of a silicon-containing manganese oxide film (MnSi _x O _y ) having a high barrier property with respect to copper (Cu) in a self-aligned manner. To do. The heat treatment is performed, for example, at an annealing temperature of 300 ° C. in an atmosphere of 100% nitrogen (N ₂ ). The generation mechanism of the silicon-containing manganese oxide film is disclosed in, for example, the 65th JSAP Preliminary Proceedings p711, “New Alloy Element for Formation of Self-Diffusion Barrier Layer in Copper Wiring”. Further, in the heat treatment, manganese that cannot be reacted is deposited on the surface of the wiring material 51 to form a manganese layer 53. The manganese-containing copper (CuMn) film (not shown) may remain on the wiring material 16 side of the barrier film 52.

  Next, as shown in FIG. 12 (5), the excessive wiring material 51, the manganese layer 53, and the barrier film 52 on the insulating film 46 are removed. For this removal processing, for example, chemical mechanical polishing is used. As a result, the second wiring 54 made of the wiring material 51 is formed in the wiring groove 50 through the barrier film 52, and the plug 55 is formed in the connection hole 50 through the barrier film 52. In this chemical mechanical polishing, since the barrier film 52 made of a silicon-containing manganese oxide film is etched by using an alkaline slurry having a pH of 9 or more, the gap between the side wall of the wiring 54 and the silicon carbide oxide film 463 of the insulating film 46 is etched. In addition, a slit 56 reaching the polyaryl ether film 463 is formed. The slit 56 is characterized by being formed intermittently. The point here is that the slit 56 can be formed without adding a special process. A copper oxide film 57 is formed on the surface of the wiring 54.

Next, as shown in FIG. 12 (6), pre-processing is performed for the purpose of removing the copper oxide film 57 [see FIG. 11 (5)] on the surface of the wiring 54. This pretreatment uses, for example, ammonia (NH ₃ ) plasma. By this plasma treatment, the copper oxide film 57 on the surface of the second wiring 54 is reduced and removed. At the same time, the polyaryl ether film of the first insulating film 462 is removed through the slit 56 to form a cavity (air gap) 58. As described above, since the formation process of the cavity 58 is the removal of the polyaryl ether film through the slit 56, a special process is added easily and reliably without depending on the density of the second wiring 54. The air gap structure can be formed without any problem.

  Finally, as shown in FIG. 13 (7), following the pretreatment, an insulating film 59 for preventing copper diffusion is formed so as to cover the second wiring 54. Usually, for example, a silicon carbide nitride film (SiCN) is used for the insulating film 59 and formed to a thickness of, for example, 50 nm. By performing the above steps, a copper wiring having an air gap structure can be formed.

  According to the above manufacturing method (third embodiment), polyaryl ether is used as the organic insulating film of the first insulating film 462, but it is etched (removed) by plasma used as a pretreatment for forming the insulating film 59. Any organic insulating film can be used as long as it is a material. In addition, although a silicon carbide oxide (SiOC) film is used as the second insulating film 463 serving as a cap film on the organic insulating film, any inorganic insulating film can be used as long as it has a sufficient processing selectivity with respect to the organic insulating film. Can be applied.

  Moreover, although CuMn was used as the seed layer, any combination can be used as long as the slit can be generated by the slurry. For example, if titanium (Ti) is used instead of CuMn and an acidic material containing hydrofluoric acid (HF) is used for the slurry, the same slit and air gap structure can be formed. Moreover, the barrier metal does not need to be a single layer. For example, if a tantalum (Ta) film is formed after forming CuMn, a wiring having a barrier metal can be formed inside the slit (wiring side). It is possible to provide a semiconductor device with higher reliability.

  In the manufacturing method (third embodiment), the slit 56 is formed on the side wall of the second wiring 54 in the step of removing excess material on the second insulating film 463, and therefore, the number of steps for forming the slit 56 is increased. There is no. Further, since the first insulating film 462 is removed from the slit 56, the cavity 58 is formed without depending on the density of the second wiring 54. As described above, since an air gap structure that does not depend on the density of the second wiring 54 can be formed, a wiring structure with a reduced inter-wiring capacitance can be formed. As a result, the signal delay can be reduced, so that it is possible to provide a high-speed and high-performance semiconductor device.

  An embodiment (fourth example of a semiconductor device) according to the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG.

  As shown in FIG. 14, a wiring layer insulating film 42 is formed on a base 41 formed on a base (not shown). The wiring layer insulating film 42 is formed of, for example, a laminated film of a polyaryl ether film and a silicon carbide oxide (SiOC) film. A first wiring 44 made of copper (Cu) is formed on the wiring layer insulating film 12 via a barrier film 43. Here, the first wiring 44 is formed to have a height of 150 nm, and a stopper film 45 for preventing copper diffusion and oxidation is formed on the first wiring 44. The stopper film 45 is formed, for example, by forming a silicon carbonitride (SiCN) film to a thickness of 35 nm, for example.

A cavity 58 is formed on the stopper film 45 by removing the first insulating film (not shown) formed on the stopper film 45. This first insulating film is formed of, for example, an organic insulating film. The organic insulating film is, for example, a polyaryl ether film and is formed to a thickness of, for example, 200 nm. A second insulating film 72 formed on the first insulating film is formed on the cavity 58. The second insulating film 72 is, for example, a silicon carbide oxide (SiOC) film and has a thickness of, for example, 140 nm. A wiring groove 49 is formed in the second insulating film 72, and a plug that connects the second wiring 54 and the first wiring 44 below the second wiring 54 through the barrier film 52 so as to reach the base 11. 55 is formed. The barrier film 52 is formed of, for example, a silicon-containing manganese oxide (MnSi _x O _y ) film. The barrier film 52 is not limited to the silicon-containing manganese oxide film, and any barrier film may be used as long as it prevents diffusion of the material forming the wiring and prevents oxygen from entering the wiring material. In addition, slits 56 connected to the cavity 58 are formed intermittently on the side wall of the second wiring 54. Since the slits 56 are formed intermittently, the second insulating film 463 is supported by the second wiring 54 via the barrier film 52 and therefore does not fall.

  In this embodiment, the slit 56 is formed by removing a part of the barrier film 52. However, the slit 56 is provided between the barrier film 52 and the second insulating film 72 as in the first embodiment. Is also possible.

  On the second wiring 54, an insulating film 59 for preventing diffusion of copper is formed. Usually, for example, a silicon carbide nitride film (SiCN) is used for the insulating film 59 and formed to a thickness of, for example, 50 nm.

  In the semiconductor device 4 of the present invention, since the slit 56 connected to the cavity 58 is formed on the side wall of the second wiring 54, it depends on the density of the second wiring 54 by removing the first insulating film from the slit 56. Without this, the cavity 58 can be formed. As described above, since the air gap structure does not depend on the density of wiring, the capacitance between wirings can be reduced. As a result, the signal delay can be greatly reduced, and there is an advantage that it is possible to provide a high-speed high-performance semiconductor device.

  Next, an embodiment (fourth example of a manufacturing method) according to a method for manufacturing a semiconductor device of the present invention will be described with reference to manufacturing process cross-sectional views of FIGS.

As shown in FIG. 15A, a wiring layer insulating film 42 is formed on a base 41 formed on a base (not shown). The wiring layer insulating film 42 is formed of, for example, a laminated film of a polyaryl ether film and a silicon carbide oxide (SiOC) film. A first wiring 44 made of copper (Cu) is formed on the wiring layer insulating film 12 through a barrier film 43. Here, the first wiring 44 is formed to have a height of 150 nm, and a stopper film 45 that prevents copper diffusion and oxidation is formed on the first wiring 44. The stopper film 45 is formed, for example, by forming a silicon carbonitride (SiCN) film with a thickness of 35 nm, for example, and also functions as an etching stopper in a later process. The SiCN film is formed by using, for example, a parallel plate type plasma CVD apparatus, using methylsilane (SiCH ₃ ) as a silicon source, a pressure of 550 Pa, and a plasma power of 200 W.

Subsequently, an insulating film 46 for forming wiring grooves and connection holes is formed on the stopper film 45. In this insulating film 46, the first insulating film 71 is formed of, for example, a polyaryl ether film, and the second insulating film 72 is formed of, for example, a silicon carbide oxide (SiOC) film. The polyaryl ether film of the first insulating film 71 is formed to a thickness of, for example, 200 nm. For example, the polyaryl ether film is formed by applying a precursor of a polyaryl ether by a spin coating method, for example, at 350 ° C., 30 nm. It is formed by performing a curing process for a minute. The silicon carbide oxide (SiOC) film of the second insulating film 72 is formed to a thickness of 140 nm, for example. This silicon carbide oxide film uses, for example, a parallel plate type plasma CVD apparatus, and uses methylsilane (SiCH ₃ ) as a silicon source in the source gas. The second insulating film 72 also functions as a hard mask in a later etching process.

  Further, a hard mask 73 is formed on the insulating film 46. The hard mask 73 is formed of, for example, a silicon nitride (SiN) film.

Next, as shown in FIG. 15B, the first insulating film is formed by dry etching using a resist mask (not shown) of a connection hole pattern and a hard mask 73 (see FIG. 13A). A wiring groove 49 and a connection hole 50 are formed in the bottom of the wiring groove 49 in the SiOC film 72 and the polyaryl ether film of the first insulating film 71. Here, the processing of the SiOC film of the second insulating film 72 is performed using a mixed gas of octafluorobutane (C ₄ F ₈ ) and argon (Ar) as an etching gas with a general magnetron etching apparatus. Set the bias power to 400W. The gas flow rate ratio is set to, for example, C ₄ F ₈ : Ar = 1: 4, and the substrate temperature is set to 20 ° C., for example.

Further, the processing of the polyaryl ether film of the first insulating film 71 here is performed using, for example, a general high-density plasma etching apparatus, for example, using ammonia (NH ₃ ) as an etching gas. For example, the RF power is set to 150 W and the substrate temperature is set to 10 ° C. Further, the processing time was set so that the processed wiring groove 49 had a depth of 150 nm. Under this etching condition, the etching selectivity between the SiOC film of the second insulating film 71 and the SiOC film of the lower wiring interlayer insulating film 12 can be obtained to be 100 or more. Even in this case, it can be performed with good controllability without causing so-called lower layer penetration.

  Next, as shown in FIG. 16 (3), after performing an appropriate degassing process, a manganese-containing copper film (CuMn) 61 is sputtered as a seed layer for forming a copper wiring material by electrolytic plating. The film is formed by the method. The formation of the CuMn film here needs to be formed with good coverage on the inner surfaces of the wiring groove 49 and the connection hole 50, and preferably a directional sputtering method such as a self-discharge ionization sputtering method or a long-distance sputtering method is used. Is good. In this example, a film having a thickness of 60 nm was formed by a directional sputtering method using a copper (Cu) target containing 5% manganese (Mn). Subsequently, the wiring material 51 is formed of copper (Cu) by electroplating, sputtering, or CVD.

Next, as shown in FIG. 16 (4), heat treatment is performed, manganese (Mn) in the manganese-containing copper film (CuMn) 61 [see FIG. 16 (3)], the second insulating film 72, and the stopper film. By reacting with silicon in 45, a barrier film 52 made of a silicon-containing manganese oxide film (MnSi _x O _y ) having a high barrier property with respect to copper (Cu) is formed in a self-aligned manner. The heat treatment is performed, for example, at an annealing temperature of 300 ° C. in an atmosphere of 100% nitrogen (N ₂ ). The generation mechanism of the silicon-containing manganese oxide film is disclosed in, for example, the 65th JSAP Preliminary Proceedings p711, “New Alloy Element for Formation of Self-Diffusion Barrier Layer in Copper Wiring”. Further, in the heat treatment, manganese that cannot be reacted is deposited on the surface of the wiring material 51 to form a manganese layer 53. The manganese-containing copper (CuMn) film (not shown) may remain on the wiring material 16 side of the barrier film 52.

  Next, as shown in FIG. 17 (5), the excessive wiring material 51, the manganese layer 53 (see FIG. 16 (4)) and the barrier film 52 on the insulating film 46 are removed. For this removal processing, for example, chemical mechanical polishing is used. As a result, the second wiring 54 made of the wiring material 51 is formed in the wiring groove 49 through the barrier film 52, and the plug 55 is formed in the connection hole 50 through the barrier film 52. In this chemical mechanical polishing, since the barrier film 52 made of a silicon-containing manganese oxide film is etched by using an alkaline slurry having a pH of 9 or more, the first insulating film 72 is formed between the side wall of the wiring 54 and the second insulating film 72. A slit 56 reaching the insulating film 71 is formed. The slit 56 is characterized by being formed intermittently. The point here is that the slit 56 can be formed without adding a special process. A copper oxide film 57 is formed on the surface of the wiring 54.

Next, as shown in FIG. 17 (6), pre-processing is performed for the purpose of removing the copper oxide film 57 [see FIG. 17 (5)] on the surface of the wiring 54. This pretreatment uses, for example, ammonia (NH ₃ ) plasma. By this plasma treatment, the copper oxide film 57 on the surface of the wiring 54 is reduced and removed. At the same time, the polyaryl ether film of the first insulating film 71 [see FIG. 17 (5)] is removed through the slit 56, and a cavity (air gap) 58 is formed. As described above, since the formation process of the cavity 58 is removal of the polyaryl ether film of the first insulating film 71 through the slit 56, it is easily and reliably performed without depending on the density of the wiring 54, and moreover a special process. An air gap structure can be formed without adding a process.

  Finally, as shown in FIG. 18 (7), following the pretreatment, an insulating film 59 for preventing copper diffusion is formed so as to cover the wiring 54. Usually, for example, a silicon carbide nitride film (SiCN) is used for the insulating film 59 and formed to a thickness of, for example, 50 nm. By performing the above steps, a copper wiring having an air gap structure can be formed.

  According to the manufacturing method (fourth embodiment), polyaryl ether is used as the organic insulating film of the first insulating film 71, but it is etched (removed) by plasma used as a pretreatment for forming the insulating film 59. Any organic insulating film can be used as long as it is a material. In addition, although a silicon carbide oxide (SiOC) film is used as the second insulating film 72 serving as a cap film on the organic insulating film, any inorganic insulating film can be used as long as it has a sufficient processing selectivity with respect to the organic insulating film. Can be applied.

  Moreover, although CuMn was used as the seed layer, any combination can be used as long as the slit can be generated by the slurry. For example, if titanium (Ti) is used instead of CuMn and an acidic material such as hydrofluoric acid (HF) is used for the slurry, the same slit and air gap structure can be formed. Moreover, the barrier metal does not need to be a single layer. For example, if a tantalum (Ta) film is formed after forming CuMn, a wiring having a barrier metal can be formed inside the slit (wiring side). It is possible to provide a semiconductor device with higher reliability.

  In the above manufacturing method (fourth embodiment), the slit 56 is formed on the side wall of the second wiring 54 in the step of removing excess material on the second insulating film 72, and therefore the number of steps for forming the slit 56 is increased. There is no. Further, since the first insulating film 462 is removed from the slit 56, the cavity 58 is formed without depending on the density of the second wiring 54. As described above, since an air gap structure that does not depend on the density of the second wiring 54 can be formed, a wiring structure with a reduced inter-wiring capacitance can be formed. Furthermore, since the layer in which the plug 55 is formed is also formed with the cavity 58, it is possible to further reduce the capacitance between wirings and the capacitance between wiring layers as compared with the third embodiment. As a result, the signal delay can be greatly reduced, and there is an advantage that it is possible to provide a high-speed high-performance semiconductor device.

  In each of the above embodiments, the barrier film may be a tantalum film or a silicon-containing manganese oxide film, and while preventing diffusion of the wiring material and preventing oxidation of the wiring material, Other barrier films can also be used.

  As described above, in the above manufacturing method, an air gap structure that does not depend on the density of the wiring reliably, easily and with good controllability without adding complicated and long-time processes as compared with the conventional copper wiring process. Therefore, it is possible to provide a good high-performance semiconductor device.

1 is a schematic cross-sectional view showing an embodiment (first example of a semiconductor device) according to a semiconductor device of the present invention. It is manufacturing process sectional drawing which showed one Embodiment (1st Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (1st Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (1st Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. 1 is a schematic cross-sectional view showing an embodiment (second example of a semiconductor device) according to a semiconductor device of the present invention. It is manufacturing process sectional drawing which showed one Embodiment (2nd Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (2nd Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (2nd Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. FIG. 6 is a schematic cross-sectional view showing an embodiment (third example of a semiconductor device) according to a semiconductor device of the invention. It is manufacturing process sectional drawing which showed one Embodiment (3rd Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (3rd Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (3rd Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (3rd Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. It is a schematic structure sectional view showing one embodiment (the 4th example of a semiconductor device) concerning a semiconductor device of the present invention. It is manufacturing process sectional drawing which showed one Embodiment (4th Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (4th Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (4th Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (4th Example of a manufacturing method) which concerns on the manufacturing method of the semiconductor device of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 13 ... 2nd insulating film, 14 ... Wiring groove, 15 ... Barrier film, 17 ... Wiring, 18 ... Slit, 20 ... Cavity

Claims (9)

A cavity formed by removing the first insulating film formed on the substrate;
A second insulating film formed on the first insulating film and on the cavity;
A semiconductor device comprising: a wiring formed through a barrier film so as to reach the substrate from a wiring groove formed in the second insulating film;
A semiconductor device comprising a slit connected to the cavity on the wiring side wall. The semiconductor device according to claim 1, wherein the slit is intermittently formed on a side wall of the wiring. The semiconductor device according to claim 1, further comprising: a plug that connects the wiring and a lower-layer wiring in a lower portion of the wiring in the cavity. Forming a first insulating film on the substrate and a second insulating film made of a different material from the first insulating film on the first insulating film;
Forming a groove in the second insulating film and the first insulating film and then embedding a wiring material in the groove through a barrier film;
Removing a surplus material on the second insulating film, and forming a wiring made of the wiring material in the trench through a barrier film, wherein the second insulation Forming a slit reaching the first insulating film on the wiring sidewall in a step of removing excess material on the film;
A method of manufacturing a semiconductor device, wherein the first insulating film is removed from the slit to form a cavity in the removal region. The method of manufacturing a semiconductor device according to claim 4, wherein the slit is intermittently formed on a side wall of the wiring. The method for manufacturing a semiconductor device according to claim 4, wherein the barrier film is made of a tantalum film. 5. The method of manufacturing a semiconductor device according to claim 4, wherein when a tantalum film is used as the barrier film, the step of removing excess material on the second insulating film is performed by polishing using an acidic chemical solution. Method. The second insulating film is made of a silicon compound,
The method of manufacturing a semiconductor device according to claim 4, wherein the barrier film is made of a manganese compound film obtained by reacting manganese with the second insulating film. 5. The semiconductor device according to claim 4, wherein when a manganese compound film is used as the barrier film, the step of removing excess material on the second insulating film is performed by polishing using an alkaline chemical solution. Production method.

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