JP2007294625A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for preventing a defect caused by conductive particles adhered to a side wall of a connection hole due to sputter etching of a lower layer wiring and preventing deterioration in an embedding characteristic and a continuity characteristic. <P>SOLUTION: The manufacturing method of the semiconductor device includes the steps of: first forming a dual damascene opening 8 comprising a wiring groove 8a and a connection hole 8b to an inter-layer isolation film 7 provided onto a substrate; forming a sacrificial film 21 in a state of covering an inner wall of the dual damascene opening 8 in a way of exposing the lower layer wiring 5 and applying sputter etching to the lower layer wiring 5; then selectively removing at least a surface side of the sacrificial film 21 with respect to the lower layer wiring 5; and thereafter embedding a conductive film to the dual damascene opening 8 and respectively forming an upper wire and a via to the wiring groove 8a and the connection hole 8b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for forming a multilayer wiring structure using copper (Cu) wiring.

  With the miniaturization and high integration of semiconductor devices, delays in electrical signals due to wiring time constants become a serious problem. For this reason, Cu wiring is introduced into the conductive layer used in the multilayer wiring process instead of aluminum (Al) alloy wiring. Unlike metal materials used for conventional multilayer wiring structures such as Al, Cu is difficult to pattern by dry etching. Therefore, a wiring groove is formed in the interlayer insulating film, and the wiring pattern is formed by embedding Cu. The forming damascene method is generally used. In particular, a dual damascene method in which a connection hole and a wiring groove are formed in an interlayer insulating film and Cu is buried at the same time is effective in reducing the number of processes (for example, see Patent Document 1).

  In the formation of fine wiring using Cu by the damascene method, it is important to improve the step coverage of the barrier metal and to improve the filling characteristics of Cu in the high aspect opening. Metallization, which is currently the mainstream, uses a tantalum (Ta) -based material barrier film and a seed Cu layer as a seed layer by physical vapor deposition (PVD), such as directional sputtering. A manufacturing method is used in which a thin film is sequentially formed and then a Cu film is embedded by electrolytic plating. An important index in determining the details of this manufacturing method is not only the degree of continuity and low resistance of wiring and connection holes, but also wiring reliability represented by electromigration and stress migration. It is how it can be improved. Accordingly, there is an urgent need to construct a Cu metallization technology that can cope with the miniaturization of semiconductor devices, has low resistance, high yield, and high wiring reliability.

  In recent years, an anchor process (via-punch through process) has been proposed as a barrier metal formation technique for Cu metallization that can particularly improve wiring reliability (see, for example, Non-Patent Document 1).

  A method for forming a Cu wiring by the damascene method using the anchor process will be described with reference to FIGS. First, as shown in FIG. 5A, an interlayer insulating film 2 made of a carbon-containing silicon oxide (SiOC) film is formed on a base insulating film 1 deposited on a substrate (not shown). A lower layer wiring 5 in which Cu is embedded in the formed wiring trench 3 through a barrier film 4 is formed. Further, a silicon carbide (SiC) film, for example, is provided as a Cu diffusion preventing film 6 on the lower wiring 5 and the interlayer insulating film 2.

Then, an interlayer insulating film 7 formed by sequentially laminating a low dielectric material (low-k) layer 7 a made of a SiOC film and a hard mask layer 7 b made of a silicon oxide (SiO ₂ ) film is formed on the diffusion preventing film 6. To do. Next, a dual damascene opening 8 composed of a wiring groove 8a and a connection hole 8b communicating with the bottom of the wiring groove 8a is formed in the interlayer insulating film 7 of this structure. Thereafter, the diffusion prevention film 6 at the bottom of the connection hole 8b is removed, and the lower layer wiring 5 is exposed.

  Next, as shown in FIG. 5B, on the hard mask layer 7b in a state of covering the inner wall of the dual damascene opening 8 so as to expose the lower layer wiring 5 by a normal directional sputtering method. A first barrier film 9 made of tantalum nitride (TaN) is formed.

  As this method, for example, using a directional magnetron sputtering apparatus in which a Ta target is installed, first a TaN film is formed on the entire surface in an atmosphere of a desired substrate bias, target DC power, and nitrogen / argon flow ratio. Then, the substrate bias is raised in the same chamber, and the discharge treatment for a predetermined time is performed by setting the film formation and etching on the field insulating film to be plus or minus zero. As a result, a TaN film is further deposited on the inner wall of the dual damascene opening 8 excluding the bottom of the connection hole 8b and the hard mask layer 7b, while a bias is applied at the bottom of the connection hole 8b having a higher aspect ratio than the Ta film deposition. Since the etching component becomes large, the lower layer wiring 5 can be selectively penetrated by sputter etching. Subsequently, the lower layer wiring 5 exposed at the bottom of the connection hole 8b is dug until the connection hole 8b reaches the inside of the lower layer wiring 5 by sputter etching. Thereby, the conductive particles 10 made of Cu scattered from the lower layer wiring 5 adhere to the surface of the barrier film 9 formed on the side wall of the connection hole 8b.

  After that, as shown in FIG. 5C, on the first barrier film 9 in a state of covering the inner wall of the dual damascene opening 8 so as to cover the conductive particles 10 by a normal directional sputtering method. A second barrier film 11 made of Ta is formed. Subsequently, as shown in FIG. 6D, a conductive film 12 made of Cu is formed on the second barrier film 11 in a state where the dual damascene opening 8 is embedded by electrolytic plating or sputtering.

  Next, as shown in FIG. 6E, a conductive film 12 unnecessary as a wiring pattern (see FIG. 6D) and a second barrier film are formed by a chemical mechanical polishing (CMP) method. 11 and the first barrier film 9 are removed, thereby forming the upper layer wiring 13 in the wiring groove 8a and the via 14 in the connection hole 8b. Subsequently, as with the lower layer wiring 5, as the Cu diffusion prevention film 15 from the upper layer wiring 13, for example, an SiC film is formed on the upper layer wiring 13 and the hard mask layer 7b. By repeating the processes of FIGS. 5A to 6E described above, a multilayer wiring structure having a dual damascene structure is formed.

  In the multilayer wiring structure formed by the manufacturing method as described above, an anchor-shaped wiring structure in which the bottom of the via 14 is embedded in the lower layer wiring 5 is formed, so that the contact area between the via 14 and the lower layer wiring 5 is small. By increasing, the dissimilar metal interface between the second barrier film 11 and the lower layer wiring 5 constituting the lower layer wiring 5 side of the via 14 is stabilized, and improvement of wiring reliability such as electromigration and stress migration can be expected.

Japanese Patent Laid-Open No. 10-143914 `` Extendibility of PVD Barrier / Seed for BEOL Cu Metallization '' 2005 International Interconnect Technology Conference (IITC) p.135-137

  However, in the manufacturing method as described above, when the lower layer wiring 5 exposed at the bottom of the connection hole 8b is dug beyond a depth at which the improvement of the wiring reliability becomes clear, the side wall of the connection hole 8b is covered. The amount of the conductive particles 10 attached to the surface of the first barrier film 9 also increases. Therefore, the adhesion between the second barrier film 11 and the conductive film 12 embedded in the connection hole 8 is required unless the second barrier film 11 formed on the first barrier film 9 is thicker than a certain thickness. There is a problem that voids are caused in the via 14 due to deterioration of adhesion. However, if the second barrier film 11 is formed too thick, the opening of the connection hole 8b when the conductive film 12 is embedded becomes narrow, and the embedding characteristic is deteriorated. Further, when the second barrier film 11 is formed thick, the ratio of the conductive film 12 in the upper layer wiring 13 and the via 14 is reduced, so that conduction characteristics such as resistance increase are deteriorated. Therefore, as the design rule becomes finer, the process becomes difficult to apply from the viewpoint of controllability.

  As described above, the present invention prevents a problem caused by the conductive particles adhering to the side wall of the connection hole by sputter etching of the lower layer wiring, and also prevents a deterioration of the embedding characteristic and the conduction characteristic. The purpose is to provide.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is characterized by sequentially performing the following steps. First, in the first step, an insulating film is formed on a substrate provided with a first conductive layer on the surface side, and a recess reaching the first conductive layer is formed in the insulating film. Next, in the second step, a sacrificial film is formed in a state of covering the inner wall excluding the bottom of the recess, and the first conductive layer exposed at the bottom of the recess is sputter-etched. Next, in the third step, at least the surface side of the sacrificial film is selectively removed with respect to the first conductive layer. In the subsequent fourth step, a second conductive layer is embedded in the recess from which at least the surface side of the sacrificial film has been removed.

  According to such a method for manufacturing a semiconductor device, in the second step, after forming the sacrificial film on the inner wall excluding the bottom of the recess, and performing the sputter etching of the first conductive layer exposed from the bottom of the recess, In the third step, since at least the surface side of the sacrificial film is removed, the conductive particles scattered from the first conductive layer and adhered to the sacrificial film covering the side walls of the recesses are sacrificed by sputter etching in the second step. It can be removed together with the film. Thereby, in the fourth step, when the second conductive layer is buried and formed in the concave portion, problems caused by the remaining conductive particles are prevented. For example, when a barrier film that prevents diffusion of the conductive material from the second conductive layer is formed between the third step and the fourth step so as to cover the inner wall of the recess, the conductive particles are removed. This prevents a decrease in adhesion between the barrier film and the second conductive layer. Further, since the conductive particles are removed, it is not necessary to form a thick barrier film, so that deterioration of embedding characteristics and conduction characteristics of the second conductive layer is prevented.

  As described above, according to the method for manufacturing a semiconductor device of the present invention, a decrease in the adhesion between the barrier film and the second conductive layer due to the remaining conductive particles is prevented, and the second conductive layer Since deterioration of the embedding characteristic and the conduction characteristic is prevented, a semiconductor device with high performance, high yield, and high reliability can be manufactured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
The present embodiment is an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention, and relates to the formation of a dual damascene structure. Hereinafter, the first embodiment of the present invention will be described with reference to the cross-sectional views of the manufacturing steps shown in FIGS. In addition, the same number is attached | subjected and demonstrated to the structure similar to background art.

  As shown in FIG. 1A, an interlayer insulating film 2 is formed on a base insulating film 1 deposited on a substrate (not shown), and a wiring film 3 formed in the interlayer insulating film 2 is interposed through a barrier film 4. Thus, for example, a lower wiring 5 (first conductive layer) embedded with Cu is formed. For example, a SiOC film is used for the interlayer insulating film 2. Further, a diffusion prevention film 6 made of, for example, a SiC film is provided on the lower wiring 5 and the interlayer insulating film 2 in order to prevent Cu from diffusing from the lower wiring 5. The diffusion prevention film 6 also functions as an etching stopper film when forming a connection hole in an oxidation prevention film for preventing the oxidation of Cu constituting the lower wiring 5 or an interlayer insulation film formed on the diffusion prevention film 6. When the diffusion preventing film 6 made of SiC is formed, as an example, a parallel plate type plasma CVD apparatus is used by a chemical vapor deposition (CVD) method, and as a gas used at that time. Uses methylsilane as a silicon source.

An interlayer formed by sequentially laminating a low dielectric material layer 7a made of, for example, a SiOC film, which is an inorganic low dielectric material, and a hard mask layer 7b made of, for example, a silicon oxide (SiO ₂ ) film, on the diffusion prevention film 6. An insulating film 7 is formed. When the low dielectric material layer 7a made of the SiOC film is formed, for example, a parallel plate type plasma CVD apparatus is used, and as a gas used at that time, methylsilane is used as a silicon source.

  Next, a dual damascene opening 8 (concave portion) including a wiring groove 8a and a connection hole 8b communicating with the bottom of the wiring groove 8a is formed in the interlayer insulating film 7 of this structure. Subsequently, the diffusion prevention film 6 at the bottom of the connection hole 8b is removed, and the surface of the lower wiring 5 is exposed at the bottom of the connection hole 8b.

  Here, as a method of forming the dual damascene opening 8, a method of opening the connection hole 8b first and then opening the wiring groove 8a is used. This detailed formation method is disclosed in, for example, “A Manufacturable Copper / Low-k SiOC / SiCN Process Technology for 90 nm-node High Performance eDRAM” International Interconnect Technology Conference (IITC) 2002 p15-17. Also, after opening the wiring groove pattern in the laminated hard mask formed on the interlayer insulating film 7, the connection hole 8b is opened in the middle, and then the wiring groove 8a and the connecting hole 8b are completely opened using the laminated hard mask. A technique may be used. This detailed forming method is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-63859.

  Next, as shown in FIG. 1B, a sacrifice made of, for example, a titanium (Ti) film on the hard mask layer 7b in a state of covering the inner wall except the bottom of the dual damascene opening 8 by, for example, PVD. The film 21 is formed with a film thickness of 30 nm, for example.

  Here, the material of the sacrificial film 21 may be any material that can be selectively removed with respect to the exposed lower layer wiring 5 because at least the surface side of the sacrificial film 21 is removed in a later step. It may be a conductive film or an insulating film. As will be described later, when all the sacrificial film 21 is removed, it is preferable that the sacrificial film 21 be formed of a material that can be selectively removed from the interlayer insulating film 7. Here, an example in which the sacrificial film 21 is formed of a conductive film will be described, and an example in which the sacrificial film 21 is an insulating film will be described in a second embodiment to be described later. As the conductive material constituting the sacrificial film 21, in addition to Ti described above, Al, tungsten (W), manganese (Mn), or an alloy film containing these or titanium nitride (TiN) can be used.

  As a method for forming the sacrificial film 21, for example, a directional magnetron sputtering apparatus in which a Ti target is installed is used. First, as a first step, a substrate bias is set to 500 W, a target DC power is set to 40 kW, and an argon atmosphere is 100%. Below, a Ti film is formed on the entire surface at a thickness of about 30 nm at 67 mPa. After that, as the second step, the substrate bias is increased to 1000 W and the target DC power is decreased to 5 kW, and Ti film formation and etching are plus or minus zero on the field insulating film at 26.6 mPa in an argon 100% atmosphere. Then, the discharge process is performed for a predetermined time. As a result, the Ti film remains on the inner wall of the dual damascene opening 8 excluding the bottom of the connection hole 8b and on the hard mask layer 7b, while the bias etching component is higher than the Ti film deposition at the bottom of the connection hole 8b having a high aspect ratio. By increasing the thickness, the Ti film can be selectively penetrated to the lower layer wiring 5 by sputter etching.

  Subsequently, the lower layer wiring 5 exposed at the bottom of the connection hole 8b is dug until the connection hole 8b reaches the inside of the lower layer wiring 5 by sputter etching. This makes it possible to form an anchor-shaped wiring structure in which the bottom of the via formed in the connection hole 8b is embedded in the lower layer wiring 5 in a later step. At this time, as the contact area between the via and the lower layer wiring is larger, the wiring reliability can be improved. Therefore, it is preferable to dig the lower layer wiring 5 beyond the depth at which the wiring reliability is surely increased. By this sputter etching, conductive particles 10 made of Cu scattered from the lower layer wiring 5 adhere to the surface of the sacrificial film 21 covering the side wall of the connection hole 8b.

  In the formation process of the sacrificial film 21, the example in which the sacrificial film 21 is formed on the inner wall of the dual damascene opening 8 excluding the bottom of the connection hole 8 b in the chamber of the same apparatus has been described. The sacrificial film 21 can also be formed by a method in which the Ti film is formed thicker than the above film thickness, and then transferred to another chamber and the Ti film at the bottom of the connection hole 8b is removed by normal sputter etching. It is. Here, the sacrificial film 21 is formed by the PVD method. However, the sacrificial film 21 may be formed by another film forming method such as a CVD method.

  Subsequently, as shown in FIG. 1C, at least the surface side of the sacrificial film 21 (see FIG. 1B) is selectively removed with respect to the lower layer wiring 5, for example, by wet etching. Then, the conductive particles 10 (see FIG. 1B) attached to the surface of the sacrificial film 21 are removed. Here, the sacrificial film 21 is completely removed to expose the interlayer insulating film 7.

  This wet etching is performed by using a normal cleaning machine, for example, a chemical solution made of diluted hydrofluoric acid (DHF) diluted to 1/100 so as to obtain a desired etching amount at room temperature. I do. At this time, the sacrificial film 21 made of the Ti film has an etching rate higher by one digit or more than the interlayer insulating film 7 including the low dielectric constant layer 7a and the lower layer wiring 5 made of Cu. The film 21 can be selectively removed. Further, the conductive particles 10 themselves made of Cu are not etched into the chemical solution, but are removed together with the sacrificial film 21 by etching the sacrificial film 21.

Here, the sacrificial film 21 made of a Ti film is removed by wet etching using DHF, but the removing method is appropriately changed depending on the material of the sacrificial film 21 described above. For example, when the sacrificial film 21 is formed of an Al film, the lower layer wiring 5 is formed by wet etching using DHF or wet etching using a mixed solution of ammonia water and hydrogen peroxide water, similarly to the Ti film. Can be selectively removed. Also, when the sacrificial film 21 is formed of a W film, dry etching using a sulfur hexafluoride (SF ₆ ) -based gas, and when formed of a TiN film, dry etching using a Cl-based gas is performed. Can be selectively removed.

  Here, all of the sacrificial film 21 is removed, but only the surface side of the sacrificial film 21 is removed, and the inner wall excluding the bottom of the dual damascene opening 8 is covered on the hard mask layer 7b. The sacrificial film 21 may be left. In this case, only the surface side of the sacrificial film 21 is removed by controlling the etching rate of the chemical treatment. Furthermore, the sacrificial film 21 may be left in a sidewall shape only on the side wall of the dual damascene opening 8, that is, only on the side wall of the wiring groove 8a and the connection hole 8b.

  Thereafter, if necessary, the surface of the lower wiring 5 exposed at the bottom of the connection hole 8b is cleaned by hydrogen annealing, and then, as shown in FIG. A barrier film 11 ′ made of Ta, for example, is formed to a thickness of 15 nm on the hard mask layer 7 b so as to cover the inner wall of the opening 8. Here, the barrier film 11 ′ is made of Ti, W, TaN, TiN, titanium silicon nitride (TiSiN), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr) alloy, etc. in addition to Ta. But you can.

  Subsequently, a conductive film 12 made of, for example, Cu is formed on the barrier film 11 ′ in a state where the dual damascene opening 8 is embedded by electrolytic plating or PVD. For example, a Cu alloy film containing silver (Ag), tin (Sn), Ti, Al, Mn, and magnesium (Mg) may be applied as the conductive film 12 in addition to the Cu film.

  Thereafter, as shown in FIG. 2 (e), by removing the conductive film 12 (see FIG. 2 (d)) and the barrier film 11 ′ which are not necessary as a wiring pattern by, for example, a CMP method, the wiring groove is formed. The upper wiring 13 (second conductive layer) is formed in 8a, and the via 14 (second conductive layer) is formed in the connection hole 8b. Next, a diffusion prevention film 15 made of, for example, a SiC film is formed on the upper wiring 13 and the hard mask layer 7b. As a result, an anchor-shaped wiring structure in which the bottom of the via 14 is embedded in the lower layer wiring 5 is formed.

  Subsequent steps are performed by repeating the steps described with reference to FIGS. 1A to 2E to form a multilayer structure having a dual damascene structure.

  According to such a method of manufacturing a semiconductor device, as described with reference to FIG. 1B, the sacrificial film 21 is formed on the inner wall of the dual damascene opening 8 excluding the bottom of the connection hole 8b, and the connection hole 8b. After performing the sputter etching of the lower layer wiring 5 exposed from the bottom of the conductive layer 10, as described with reference to FIG. 1C, the conductive particles 10 attached to the sacrificial film 21 covering the side wall of the connection hole 8b are removed from the sacrificial film. It becomes possible to remove together with 21. This prevents a decrease in the adhesion between the barrier film 11 ′ and the via 14 due to the remaining conductive particles 10, thereby preventing the generation of voids in the via 14. Further, since the conductive particles 10 are removed, the barrier film 11 ′ does not have to be formed thick, so that deterioration of the embedding characteristics of the conductive film 12 and the conduction characteristics of the upper wiring 13 and the via 14 can be prevented. The As described above, a semiconductor device with high performance, high yield, and high reliability can be manufactured.

  Further, according to the method of manufacturing a semiconductor device of the present embodiment, since the anchor-shaped wiring structure in which the bottom of the via 14 is embedded in the lower layer wiring 5 is formed, the contact area between the via 14 and the lower layer wiring is increased. This stabilizes the dissimilar metal interface between the barrier film 11 ′ on the lower wiring 5 side of the via 14 and the lower wiring 5, and can be expected to improve wiring reliability such as electromigration and stress migration.

In the first embodiment, the example in which the interlayer insulating film 7 is composed of the laminated film of the low dielectric material layer 7a made of the SiOC film and the hard mask layer 7b made of the SiO ₂ film has been described. However, the constituent material of the interlayer insulating film 7 may be selected according to the device required performance. As the constituent material of the interlayer insulating film 7, as an inorganic material, in addition to the above-described SiO ₂ film and SiOC film, a fluorine-containing silicon oxide (SiOF) film which is an inorganic low dielectric material film, an organic low dielectric constant As the material film, a polyaryl ether (PAE) film, a P-benzocyclobutene (P-BCB) film, or the like may be used. Alternatively, a film obtained by making these porous (porous film) may be used. The above-described film may be used as a single layer or may be stacked. For example, an inorganic low dielectric material film and an organic low dielectric material film may be stacked to form a hybrid structure.

(Second Embodiment)
Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described using the manufacturing process sectional views of FIGS. In addition, the same number is attached | subjected and demonstrated to the structure similar to 1st Embodiment.

  First, as shown in FIG. 3A, an interlayer insulating film 2 made of SiOC is formed on a base insulating film 1 deposited on a substrate (not shown), and a wiring groove 3 formed in the interlayer insulating film 2 is formed in the wiring groove 3 formed in the interlayer insulating film 2. A lower layer wiring 5 in which Cu is embedded via the barrier film 4 is formed. A diffusion prevention film 6 made of SiC is provided on the lower wiring 5 and the interlayer insulating film 2.

Next, an interlayer insulating film 7 ′ is formed on the diffusion preventing film 6. Here, an interlayer insulating film 7 ′ formed by sequentially laminating a low dielectric material layer 7a ′ made of, for example, a porous (porous) SiOC film (porous SiOC film) and a hard mask layer 7b ′ made of, for example, SiO _{2 is} formed. It will be formed. Here, as a method for forming a porous SiOC film, it is formed by applying nano clustering silica (hereinafter referred to as NCS) and curing at 300 ° C. to 400 ° C. in a nitrogen atmosphere. This porous SiOC film has a relative dielectric constant of around 2.3 and an average pore size of 3 nm or less. Further, as the low dielectric material layer 7a ′, an LKD series manufactured by JSR, which is a low dielectric constant film having a porous structure, or other porous MSQ (Methyl silsesquioxane) film may be used. Further, the film may be cured after being formed by a parallel plate type plasma CVD method using a methylsilane-based gas and a pore source (a hole forming material). Further, the bonding of the low dielectric material layer 7a ′ may be adjusted by performing curing by electron beam irradiation or UV irradiation.

  Next, a dual damascene opening 8 comprising a wiring groove 8a and a connection hole 8b communicating with the bottom of the wiring groove 8a is formed in the interlayer insulating film 7 'of this structure. Subsequently, the diffusion prevention film 6 at the bottom of the connection hole 8b is removed, and the surface of the lower wiring 5 is exposed at the bottom of the connection hole 8b.

Next, as shown in FIG. 3B, a sacrificial film 22 made of, for example, SiO ₂ is, for example, 20 nm on the hard mask layer 7b ′ so as to cover the inner wall of the dual damascene opening 8 by, eg, CVD. The film thickness is formed.

Here, in this embodiment, the sacrificial film 22 is formed of an insulating film. As the insulating material constituting the sacrificial film 22, in addition to the above-described SiO ₂ , for example, a silicon nitride (SiN) film, a carbon-containing silicon nitride (SiCN) film, a nitrogen-containing silicon oxide (SiON) film, a SiOC film, SiC An inorganic insulating film such as a film, an organic insulating film such as a P-BCB film, a hydrocarbon film, or the like can be used.

As a method for forming the sacrificial film 22, for example, a parallel plate type plasma CVD apparatus is used. As a film forming gas, TEOS (Tetraethoxysilane) gas as a silicon source and dinitrogen monoxide (N ₂ O) gas as an oxidizing agent are used. Use. As film formation conditions, the substrate temperature is set to 300 to 400 ° C., the plasma power is set to 150 W to 350 W, and the pressure of the film formation atmosphere is set to about 100 Pa to 1000 Pa.

  Subsequently, as shown in FIG. 3C, the sacrificial film 22 at the bottom of the connection hole 8b is selectively removed to expose the lower wiring 5. Thereafter, the lower layer wiring 5 exposed at the bottom of the connection hole 8b is dug until the connection hole 8b reaches the inside of the lower layer wiring 5 by sputter etching. At this time, the conductive particles 10 made of Cu scattered from the lower layer wiring 5 adhere to the surface of the sacrificial film 22 covering the side wall of the connection hole 8b.

  This method uses a directional magnetron sputtering apparatus with a Ti target installed, a substrate bias of 1000 W, a target DC power of 5 kW, and a Ti film formation and etching at 67 mPa in an argon 100% atmosphere. A discharge process for a predetermined time is performed by setting so as to be plus or minus zero on the insulating film. As a result, on the hard mask layer 7b ′ and the wiring groove 8a excluding the bottom of the connection hole 8b and the inner wall of the connection hole 8b, the Ti film is formed on the bottom of the wiring groove 8a, the wiring groove 8a and The sacrificial film 22 is sputtered at the bottom of the connection hole 8b having a high aspect ratio while the sacrificial film 22 is formed on the side wall of the connection hole 8b. By etching, the lower layer wiring 5 can be selectively penetrated. In this step, a Ti film may be formed on the inner wall of the dual damascene opening 8 excluding the bottom of the connection hole 8b, but the Ti film may remain.

  Subsequently, as shown in FIG. 4D, at least the surface side of the sacrificial film 22 is selectively removed with respect to the lower wiring 5 by, for example, wet etching, so that the sacrificial film 22 and the sacrificial film 22 are formed. The conductive particles 10 (see FIG. 3C) attached to the surface are removed. Here, the sacrificial film 22 is left by removing about 5 nm on the surface side of the sacrificial film 22 having a thickness of about 20 nm. Thereby, the remaining sacrificial film 22 functions as a protective insulating film for the porous SiOC film constituting the low dielectric material layer 7a 'of the interlayer insulating film 7', and suppresses degassing from the porous SiOC film.

  This wet etching is performed using a normal cleaning machine, for example, with a chemical solution made of DHF diluted to 1/100 so that a desired etching amount is obtained at room temperature. At this time, by controlling the DHF hydrofluoric acid concentration and the processing time, etching in nm units can be controlled. At this time, the conductive particles 10 themselves made of Cu are not etched by the chemical solution, but are removed together with the sacrificial film 22 by etching the surface side of the sacrificial film 22.

Here, the sacrificial film 22 made of SiO ₂ is removed by wet etching using a chemical solution made of DHF, but the removal method is appropriately changed depending on the material of the sacrificial film 22. For example, when the sacrificial film 22 is formed of a SiOC film, the sacrificial film 22 can be selectively removed from the lower wiring 5 by wet etching using a chemical solution of ammonium fluoride, and the SiN film, SiON film, SiCN can be removed. When formed with a film, the film can be selectively removed by wet etching using a phosphoric acid chemical solution. When the sacrificial film 22 is formed of an organic insulating film such as a P-BCB film or a hydrocarbon film, it can be selectively removed by dry etching using ammonia gas.

  The subsequent steps are performed in the same manner as in the first embodiment. That is, if necessary, after the oxide layer on the surface of the lower layer wiring 5 exposed at the bottom of the connection hole 8b is cleaned by hydrogen annealing, as shown in FIG. A barrier film 11 ′ made of Ta, for example, is formed on the sacrificial film 22 so as to cover the inner wall of the opening 8. Subsequently, a conductive film 12 made of, for example, Cu is formed on the barrier film 11 ′ in a state where the dual damascene opening 8 is embedded by electrolytic plating or PVD.

  Thereafter, as shown in FIG. 4 (f), unnecessary portions of the conductive film 12, the barrier film 11 ′ and the sacrificial film 22 as a wiring pattern are removed by CMP to form the upper wiring 13 in the wiring groove 8a. At the same time, the via 14 is formed in the connection hole 8b. Next, a diffusion prevention film 15 made of, for example, a SiC film is formed on the upper layer wiring 13 and the hard mask layer 7b '. As a result, an anchor-shaped wiring structure in which the bottom of the via 14 is embedded in the lower layer wiring 5 is formed.

  Thereafter, the multi-layer wiring structure having a dual damascene structure is formed by repeatedly performing the steps described with reference to FIGS. 3A to 4F.

  Also by such a method of manufacturing a semiconductor device, the conductive particles 10 attached to the sacrificial film 22 covering the side wall of the connection hole 8b by sputter etching of the lower layer wiring 5 by removing the surface side of the sacrificial film 22 can be obtained. Since it is removed together with the sacrificial film 22, the same effect as that of the first embodiment can be obtained.

  Further, according to the method for manufacturing the semiconductor device of the present embodiment, only the surface side of the sacrificial film 22 made of an insulating film is removed, so that the remaining sacrificial film 22 is used as a protective insulating film for the low dielectric material layer 7a ′. Therefore, degassing from the low dielectric material layer 7a ′ can be prevented. Furthermore, by leaving the sacrificial film 22 to function as a protective insulating film for the low dielectric material layer 7a ′, the low dielectric material layer 7a ′ can be made to have a material having a lower relative dielectric constant (ultra low dielectric constant (ultra low− k)) Since a film can be used, the capacitance between wirings can be reduced.

  In the first and second embodiments described above, the lower layer wiring 5 exposed at the bottom of the connection hole 8b is dug until the connection hole 8b reaches the inside of the lower layer wiring 5 by sputter etching. Thus, the example in which the anchor-shaped wiring structure in which the bottom portion of the via 14 is embedded in the lower layer wiring 5 is formed has been described. However, the present invention is not limited to this, and the present invention is applicable even when the via 14 in a state reaching the surface of the lower wiring 5 is formed without digging the lower wiring 5 exposed at the bottom of the connection hole 8b. Is possible. However, also in this case, when the sacrificial film 21 or the sacrificial film 22 is formed in a state of covering the inner wall of the dual damascene opening 8 except the bottom of the connection hole 8b, the lower layer wiring exposed at the bottom of the connection hole 8b Sputter etching is performed on the surface of 5.

  In the first embodiment and the second embodiment described above, the dual damascene method is used as an example to describe a method for manufacturing a semiconductor device in which the upper wiring 13 and the via 14 are formed in the same process. The present invention can also be applied to the case where wirings and vias are formed in separate processes using a single damascene method. In this case, the sacrificial film is formed so as to cover the side wall except for the bottom of the wiring trench or the connection hole, and the vias exposed on the bottom or the wiring are sputter etched to adhere to the surface of the sacrificial film. The conductive particles are removed together with at least the surface side of the sacrificial film.

FIG. 6 is a manufacturing process cross-sectional view (No. 1) for describing the first embodiment of the semiconductor device manufacturing method of the present invention; FIG. 6 is a manufacturing process sectional view (No. 2) for describing the first embodiment of the manufacturing method of the semiconductor device of the invention; It is manufacturing process sectional drawing (the 1) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 2) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 1) for demonstrating the manufacturing method of the conventional semiconductor device. It is manufacturing process sectional drawing (the 2) for demonstrating the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  5 ... Lower layer wiring, 7, 7 '... Interlayer insulating film, 8a ... Wiring groove, 8b ... Connection hole, 8 ... Dual damascene opening, 13 ... Upper layer wiring, 14 ... Via, 21, 22 ... Sacrificial film

Claims (6)

A first step of forming an insulating film on a substrate provided with a first conductive layer on the surface side, and forming a recess reaching the first conductive layer in the insulating film;
A second step of forming a sacrificial film in a state of covering the inner wall excluding the bottom of the recess, and performing sputter etching of the first conductive layer exposed at the bottom of the recess;
A third step of selectively removing at least the surface side of the sacrificial film with respect to the first conductive layer;
And a fourth step of embedding and forming a second conductive layer in the concave portion from which at least the surface side of the sacrificial film has been removed. In the manufacturing method of the semiconductor device according to claim 1,
In the second step, the first conductive layer is dug until the concave portion reaches the inside of the first conductive layer by the sputter etching. In the manufacturing method of the semiconductor device according to claim 1,
In the third step, the conductive particles attached to the surface of the sacrificial film are removed together with at least the surface side of the sacrificial film by the sputter etching in the second step. In the manufacturing method of the semiconductor device according to claim 1,
In the third step, the sacrificial film is left on the inner wall except for the bottom of the recess by removing only the surface side of the sacrificial film. In the manufacturing method of the semiconductor device according to claim 1,
Between the third step and the fourth step,
A method of manufacturing a semiconductor device, comprising: forming a barrier film that prevents diffusion of a conductive material from the second conductive layer in a state of covering an inner wall of the recess. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the recess is composed of a wiring groove and a connection hole communicating with the bottom of the wiring groove.

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