CN112490181A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN112490181A CN112490181A CN201910867285.1A CN201910867285A CN112490181A CN 112490181 A CN112490181 A CN 112490181A CN 201910867285 A CN201910867285 A CN 201910867285A CN 112490181 A CN112490181 A CN 112490181A
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- groove
- trench
- conductive material
- titanium nitride
- etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A method of fabricating a semiconductor device, comprising: providing a substrate, wherein a groove is formed in the substrate, titanium nitride is attached to the wall of the groove, and a conductive material is filled in the groove; performing dry etching on the conductive material in the groove to partially remove the conductive material in the groove; performing inert gas ion bombardment on the groove wall of the groove; carrying out wet etching on the groove wall of the groove; and forming an insulating material on the conductive material in the trench. Through utilizing inert gas ion bombardment slot wall of slot to destroy the combination of the attached impurity on the slot wall of slot and titanium nitride and slot wall, in order to follow-up better etching get rid of attached impurity and titanium nitride on the slot wall, and then guarantee the holistic performance of product.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor device.
Background
In semiconductor manufacturing, in order to increase the number of transistors per unit area and reduce the chip cost, it is necessary to rely on a micro-fabrication process. However, the small size of the semiconductor device creates many problems to be overcome in the manufacturing process. For example, in the field of Dynamic Random Access Memory (DRAM), a Buried Channel Array Transistor (BCAT) structure is used to increase the effective Channel length and suppress the leakage current generated by short Channel without changing the unit area of the DRAM. Under the BCAT structure, a small trench (trench) needs to be etched down from the substrate (substrate) to serve as a gate electrode (gate electrode) of the transistor. Titanium nitride (TiN) and other impurities such as polymers are attached to the walls of the small trenches. Due to the shrinking process, the aspect ratio of the small trench is large, which makes the subsequent etching difficult to go deep into the trench to remove the titanium nitride (TiN) and other impurities attached on the trench wall, thereby affecting the performance of the product.
Disclosure of Invention
Therefore, it is desirable to provide a method for fabricating a transistor, which can effectively solve the above problems.
A method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate, wherein a groove is formed in the substrate, titanium nitride is attached to the wall of the groove, and a conductive material is filled in the groove;
performing dry etching on the conductive material in the groove to partially remove the conductive material in the groove;
performing inert gas ion bombardment on the groove wall of the part of the groove not filled with the conductive material;
carrying out wet etching on the groove wall of the groove; and
an insulating material is formed over the conductive material in the trench.
According to the preparation method, the inert gas ions are utilized to bombard the groove wall of the groove, so that impurities attached to the groove wall of the groove and the combination of the titanium nitride and the groove wall are damaged, the impurities and the titanium nitride attached to the groove wall are etched and removed better in the following process, and the overall performance of the product is further ensured.
Drawings
FIG. 1 is a flow chart of a method for fabricating a DRAM of a semiconductor device according to the present invention.
Fig. 2A-2H are schematic diagrams of a method of fabricating a semiconductor device.
Fig. 3 is a schematic plan view of a substrate of the semiconductor device.
Description of the main elements
The present invention will be further described with reference to the accompanying drawings.
Detailed Description
While the embodiments of the invention are illustrated in the drawings, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions may be exaggerated for clarity.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The invention provides a method for manufacturing a semiconductor device, which is suitable for manufacturing a semiconductor device such as a dynamic random access memory. In this embodiment, the semiconductor device is a dynamic random access memory. The following describes a method for manufacturing the semiconductor device, taking the semiconductor device as a dram as an example. Referring to fig. 1, the method for fabricating the semiconductor device includes the following steps.
Step S1: providing a substrate, wherein a groove is formed in the substrate, a titanium nitride layer is attached to the wall of the groove, and a conductive material is filled in the groove.
Step S1 further includes the following steps, as shown in fig. 2A-2D.
As shown in fig. 2A, a substrate 10 is provided, a first trench 131 is formed in the substrate 10, the substrate 10 has a contact surface 11, and the first trench 131 penetrates through the contact surface 11; forming an insulating oxide layer 20 on the contact surface 11, wherein the insulating oxide layer 20 is thinner than the substrate 10, and the insulating oxide layer 20 also extends into the groove wall attached to the first trench 131; and the trenches 13 are filled with an insulating oxide material 40. The substrate 10 may be a silicon substrate. The material of the insulating oxide layer 20 and the insulating oxide material 40 may be various oxide insulating materials conventionally used in the art, such as silicon oxide.
As shown in fig. 2B, a barrier layer 50 is then formed on the insulating oxide layer 20 on the contact surface 11, and the barrier layer 50 also covers the first trench 131. The barrier layer 50 is an insulating material such as silicon oxide. The barrier layer 50 is flat and has a thickness greater than the thickness of the insulating oxide layer 20. The barrier layer 50 is provided to protect the substrate 10 during the subsequent chemical mechanical polishing process, and to prevent the substrate 10 from being polished.
As shown in fig. 2C, the substrate 10 having the barrier layer 50, the insulating oxide layer 20 and the insulating oxide material 40 is then subjected to an etching process to form a second trench 133 in the substrate 10, which penetrates through the barrier layer 50 and the insulating oxide layer 20 on the contact surface 11, and at the same time, a portion of the insulating oxide material 40 filling the first trench 131 near the contact surface 11 is also etched away to form the accommodating portion 130 in the first trench 131. The second grooves 133 are independent of the first grooves 131. In this way, the depth of the newly etched second groove 133 is substantially equal to the depth of the accommodating portion 130 in the first groove 131. The grooves 13 include the first grooves 131 and the second grooves 133. In this embodiment, the second trench 133 is used for depositing a gate, and the first trench 131 is used for depositing a word line (or word select line). The first trench 131 and the second trench 133 each have a large aspect ratio. Only two first trenches 131 and two second trenches 133 are exemplarily present in fig. 2C.
As shown in fig. 2D, a gate oxide layer 60 (e.g., silicon oxide) and a titanium nitride layer 30 are sequentially formed on the walls of the second trench 133 and the walls of the unfilled portion of the first trench 131 (i.e., the accommodating portion 130), and the gate oxide layer 60 and the titanium nitride layer 30 are both thin, so that a large amount of empty space is left in the first trench 131 and the second trench 133. After titanium nitride layer 30 is formed, rapid thermal processing may be used to anneal the titanium nitride to reduce the resistance of the titanium nitride. The titanium nitride layer 30 attached to the walls of the trench 13 may be replaced with at least one of Ti, Ta, TaN and TiW.
As shown in fig. 2D, the remaining portion (i.e., the accommodating portion 130) of the first trench 131 is filled with the conductive material 70, and the second trench 133 is filled with the conductive material 70, wherein the conductive material 70 also covers the surface of the barrier layer 50 away from the substrate 10. In this embodiment, the conductive material 70 is metal tungsten.
Step S2: the conductive material in the trench is dry etched to partially remove the conductive material in the trench.
Step S2 further includes the following steps.
As shown in fig. 2E, the conductive material 70 on the surface of the barrier layer 50 remote from the substrate 10 is removed. This step may be performed by chemical mechanical polishing. Due to the presence of the barrier layer 50, the substrate 10 can be effectively prevented from being abraded during the chemical mechanical polishing process. The principle of the chemical mechanical polishing method is a processing technology combining chemical corrosion and mechanical removal, and is a technology capable of realizing global surface planarization in the current mechanical processing.
As shown in fig. 2F, the etching removes portions of the conductive material 70 in the first trenches 131 and the second trenches 133. The etching is performed by dry etching using an etching gas, for example, SF6Etching tungsten metal with Cl2And etching the TiN. The purpose of the etching is to form a free space in the first trench 131 and the second trench 133 for subsequent deposition of an insulating material therein.
The conductive material 70 remaining in the second trench 133 is formed as a gate, and the conductive material 70 remaining in the first trench 131 is formed as a word line.
During the dry etching of the portion of the conductive material 70 in the first trench 131 and the second trench 133, some impurities (e.g., polymers) may be formed on the walls of the trenches by the etching gas, and the impurities may also form chemical bonds with the walls of the trenches 13, which may affect the effect of the subsequent wet etching to remove the impurities and titanium nitride on the walls of the trenches. If these impurities and titanium nitride remain on the walls of the trenches, the performance of the semiconductor device is adversely affected.
Step S3: the walls of the trench that are exposed (i.e., not covered by the conductive material) are subjected to an inert gas ion bombardment.
As shown in fig. 2G, step S3 bombards the trench wall of the trench 13 with inert gas ions, which are not easy to generate chemical reaction and have a characteristic of large atomic mass, so as to destroy the impurities and titanium nitride bound to the trench wall (e.g., destroy the chemical bonds between the impurities and the trench wall by physical collision) at the trench wall of the portion of the first trench 131 and the second trench 133 not filled with the conductive material 70, so as to remove the impurities and titanium nitride bound to the trench wall by subsequent etching. The gate oxide layer 60 attached to the trench walls may remain unremoved during this step.
In this embodiment, the inert gas ion implantation is argon ion implantation. The specific process conditions of argon ion implantation are as follows: in the ionic state Ar+Or Ar2+Argon ion energy of 500eV or more and 15keV or less, and ion concentration of 1X 10 or more15cm-2And is not more than 1 x 1016cm-2The inclination angle is 0-30 degrees, and the rotation is X4 or X8.
Step S4: and carrying out wet etching on the wall of the groove.
The etching solution adopted by the wet etching contains sulfuric acid. The effect of this step is to remove titanium nitride and other impurities on the walls of the unfilled portion of trench 13 by etching with an etching solution.
Before or after performing the step S4, the method may further include: the insulating oxide layer 20 and the barrier layer 50 on the contact surface 11 of the substrate 10 are removed to expose the contact surface 11 of the substrate 10, as shown in fig. 2H.
Step S5: an insulating material is formed over the conductive material in the trench.
The step S5 may include: as shown in fig. 2H, a first insulating material layer 81 is deposited over the conductive material 70 in the trench 13, and then a second insulating material layer 82 is deposited over the first insulating material layer 81 until the trench 13 is filled. In this embodiment, the first insulating material layer 81 is made of silicon oxide, and the second insulating material layer 82 is made of silicon nitride.
The above-mentioned manufacturing method is a part of the steps in the manufacturing process of the semiconductor device, and it can be understood that many other steps are required when the semiconductor device is an actual semiconductor product such as a dynamic random access memory, for example, a step of forming other functional layers on the contact surface 11 of the substrate 10.
Referring to the top view of the DRAM substrate 10 shown in FIG. 3, the DRAM substrate 10 shown in FIG. 2H is taken along the line III-III in FIG. 3. As shown in fig. 3, 4 strips of conductive material 70 are disposed on the substrate 10, wherein the portions of the conductive material 70 on two sides corresponding to the first trench 131 are the conductive material 70 in the first trench 131 in fig. 2H, and the portions of the two conductive materials 70 in the middle corresponding to the second trench 133 are the conductive material 70 in the second trench 133 in fig. 2H. As shown in fig. 3, some locations on the substrate 10 are defined as locations of Storage Nodes (SN) and some locations are defined as locations of Bit Line nodes (BN).
According to the preparation method of the semiconductor device, the inert gas ions are utilized to bombard the groove wall of the groove, so that the combination of impurities and titanium nitride attached to the groove wall of the groove and the groove wall is damaged, the impurities and the titanium nitride attached to the groove wall are etched and removed better in the following process, and the overall performance of the product is further ensured.
The above embodiments are only intended to illustrate the technical solution of the present invention and not to limit, and the up, down, left and right directions shown in the drawings are only for convenience of understanding, although the present invention is described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate, wherein a groove is formed in the substrate, titanium nitride is attached to the wall of the groove, and a conductive material is filled in the groove;
performing dry etching on the conductive material in the groove to partially remove the conductive material in the groove;
performing inert gas ion bombardment on the groove wall of the part of the groove not filled with the conductive material;
carrying out wet etching on the groove wall of the groove; and
an insulating material is formed over the conductive material in the trench.
2. The method of claim 1, wherein: the dry etching includes etching the conductive material with an etching gas.
3. The method of claim 1, wherein: the function of the inert gas ion bombardment is to reduce the bonding of titanium nitride and other impurities on the trench walls with the trench walls.
4. The method of claim 1, wherein: the wet etching includes using an etching solution containing sulfuric acid to remove titanium nitride and other impurities on the walls of the trench.
5. The method of claim 1, wherein: the semiconductor device is a dynamic random access memory.
6. The method of claim 5, wherein: the substrate is a silicon substrate, and the conductive material is metal tungsten.
7. The method of claim 5, wherein: forming an insulating material over the conductive material in the trench including depositing a first layer of insulating material and then depositing a second layer of insulating material until the trench is filled; the first insulating material layer and the second insulating material layer are made of different materials.
8. The method of claim 1, wherein: the inert gas ion bombardment adopts argon ions, and the ion state is Ar+Or Ar2+Ion energy of 500eV-15KeV, and ion concentration of 1X 10 or more15cm-2And is not more than 1 x 1016cm-2。
9. The method of claim 1, wherein: and titanium nitride is attached to the wall of the groove and replaced by at least one of Ti, Ta, TaN and TiW.
10. The method of claim 1, wherein: the dry etching comprises using SF6Etching tungsten metal with Cl2The titanium nitride is etched.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910867285.1A CN112490181B (en) | 2019-09-12 | 2019-09-12 | Method for manufacturing semiconductor device |
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| CN201910867285.1A CN112490181B (en) | 2019-09-12 | 2019-09-12 | Method for manufacturing semiconductor device |
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| CN112490181B CN112490181B (en) | 2023-03-24 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112735946A (en) * | 2021-03-29 | 2021-04-30 | 度亘激光技术（苏州）有限公司 | Semiconductor device preparation method |
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| JP2007294625A (en) * | 2006-04-25 | 2007-11-08 | Sony Corp | Manufacturing method of semiconductor device |
| US20080211057A1 (en) * | 2007-01-04 | 2008-09-04 | Samsung Electronics Co., Ltd. | Semiconductor having buried word line cell structure and method of fabricating the same |
| US20120161218A1 (en) * | 2010-12-27 | 2012-06-28 | Elpida Memory, Inc. | Semiconductor device and method for manufacturing the same |
| CN104241359A (en) * | 2013-06-21 | 2014-12-24 | 联华电子股份有限公司 | Semiconductor element structure and manufacturing method thereof |
| US20170317086A1 (en) * | 2015-08-04 | 2017-11-02 | Micron Technology, Inc. | Method of Forming Conductive Material of a Buried Transistor Gate Line and Method of Forming a Buried Transistor Gate Line |
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Patent Citations (5)
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| JP2007294625A (en) * | 2006-04-25 | 2007-11-08 | Sony Corp | Manufacturing method of semiconductor device |
| US20080211057A1 (en) * | 2007-01-04 | 2008-09-04 | Samsung Electronics Co., Ltd. | Semiconductor having buried word line cell structure and method of fabricating the same |
| US20120161218A1 (en) * | 2010-12-27 | 2012-06-28 | Elpida Memory, Inc. | Semiconductor device and method for manufacturing the same |
| CN104241359A (en) * | 2013-06-21 | 2014-12-24 | 联华电子股份有限公司 | Semiconductor element structure and manufacturing method thereof |
| US20170317086A1 (en) * | 2015-08-04 | 2017-11-02 | Micron Technology, Inc. | Method of Forming Conductive Material of a Buried Transistor Gate Line and Method of Forming a Buried Transistor Gate Line |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112735946A (en) * | 2021-03-29 | 2021-04-30 | 度亘激光技术（苏州）有限公司 | Semiconductor device preparation method |
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