KR101069415B1 - Stacked Noah Flash Memory Array and Manufacturing Method Thereof - Google Patents

Abstract

The present invention relates to a noah flash memory array and a method of manufacturing the same, and more particularly, vertically stacked memory cells along each word line while being stacked vertically, and are vertically intersecting the word lines of each layer. A bit line is formed to contact each cell's source / drain, and stacked vertically to increase memory capacity as much as possible.

Description

Stacked NOR Flash Memory Array and Manufacturing Method Thereof {STACKED NOR FLASH MEMORY ARRAY AND FABRICATION METHOD THEREOF}

The present invention relates to a noah flash memory array and a method of manufacturing the same, and more particularly, the memory cells are formed in series along each word line while being stacked vertically, vertically intersecting the word lines of each layer and the source of each cell. A bit line is formed in contact with a drain, and stacked vertically to increase the memory capacity as much as possible.

Noah flash memory has a problem in that the manufacturing process is more complicated and less integrated than NAND flash memory, although the random access characteristics have the advantage of enabling fast read operation because of the advantage of enabling fast read operations.

In particular, the cost per unit bit, i.e., bit-cost, is expected to increase gradually due to the manufacturing process and the miniaturization limit of memory cells (devices). Recently, studies on stackable three-dimensional structures have been actively conducted.

However, most of the studies on vertically stackable three-dimensional structures are related to NAND flash memory arrays in which each cell can be connected in series to easily form a bit line, and is separated from the bit line to access each cell. There is almost no research on no-flash memory arrays that must form contacts.

Accordingly, an object of the present invention is to provide a Noah flash memory array having a stacked three-dimensional structure capable of stacking word lines vertically and increasing memory capacity as much as possible, and a method of manufacturing the same.

In order to achieve the above object, the stacked Noah flash memory array according to the present invention comprises a plurality of word lines stacked vertically spaced apart on the substrate; A plurality of semiconductor layers in which channel regions and sources / drains are repeatedly formed in a word line direction with an insulating film having a charge storage layer parallel to each other on one side of each word line; A plurality of interlayer insulating films formed on the upper and lower surfaces of the semiconductor lines parallel to the word lines and the word lines; And a plurality of bit lines passing through at least one of the plurality of interlayer insulating layers and having vertical connection plugs to contact upper and lower sources / drains of the semiconductor layers and intersect the word lines.

Here, a separate insulating film is formed on an opposite side of each word line on which the semiconductor layers are formed, and the interlayer insulating film forms a stacked structure with the separated insulating film, wherein each word line and the charge storage layer are formed around the stacked structure. An insulating film having a semiconductor layer and a basic array formed to be symmetrical with each semiconductor layer is repeatedly formed in a bit line direction, and the vertical connection plugs of the bit lines are in common contact with a source / drain of a semiconductor layer located between the base arrays. It may have a first form formed.

Alternatively, a basic array in which the word lines, the insulating film having the charge storage layer, the semiconductor layer and the interlayer insulating film are symmetrically around the vertical connection plugs of the respective bit lines is repeatedly formed in the bit line direction. The semiconductor array may have a second shape, in which a semiconductor substrate may be formed to be in contact with opposite sides of the word lines in which the semiconductor layers are adjacent to each other.

In the meantime, in the method of manufacturing a stacked type Noah flash memory array having the first aspect, n is repeatedly stacked on a predetermined substrate in the order of "interlayer insulating film-> separating insulating film" n times, and the n + 1 interlayer insulating film is placed on the nth insulating insulating film. Stacking one more time and then etching the first mask patterned in the word line direction to form a plurality of basic array patterns; A second step of isotropically etching the plurality of basic array patterns to recess the isolation insulating layer laterally; Depositing a wordline material on the entire surface of the substrate and etching anisotropically to fill the recessed portions of the respective basic array patterns with the wordline material; A fourth step of isotropically etching the filled wordline material to recess laterally; A fifth step of forming an insulating film having a charge storage layer on said recessed wordline material; Depositing a semiconductor material over the entire surface of the substrate and etching anisotropically to fill the recessed portion of the insulating film with the semiconductor material; A seventh step of depositing and planarizing a separation oxide film over the entire substrate; An eighth step of forming a second mask patterned in a bit line direction on the planarized separated oxide layer and etching the separated oxide layer to expose the filled semiconductor material between the etched separated oxide layers; A ninth step of implanting ions into the exposed semiconductor material to form a source / drain of a memory cell; And forming a bit line between the etched separated oxide layers by depositing and planarizing the bit line material on the entire surface of the substrate.

In the method for manufacturing a stacked Noah flash memory array having the second aspect, the method is repeatedly stacked n times on the predetermined substrate in the order of "stacking media layer-> semiconductor layer", and n + 1th stacking is performed on the nth semiconductor layer. Stacking the intermediate layer and the etch stop layer and etching the first mask patterned in the word line direction to form a plurality of basic array patterns; A second step of isotropically etching the plurality of basic array patterns to recess the stacking layer in a lateral direction; Depositing an interlayer dielectric material on the entire surface of the substrate and etching anisotropically to fill the recessed portions of the respective basic array patterns with the interlayer dielectric material; A fourth step of isotropically etching each of the filled basic array patterns to recess the semiconductor layer in a lateral direction; A fifth step of forming an insulating film having a charge storage layer on said recessed semiconductor layer; Depositing a wordline material on the entire surface of the substrate and etching anisotropically to fill the recessed portion of the insulating layer with the wordline material; A seventh step of depositing and planarizing a separation insulating film over the entire substrate; A second mask that separates each of the basic array patterns by sequentially etching the etch stop layer / n + 1 th stacking layer / n " semiconductor layer / laminate medial layer " with a second mask open in the word line direction among the etch stop layers; 8 steps; A ninth step of removing the stacking layers remaining in each of the separated basic array patterns, and then filling and planarizing the interlayer insulating film material in the separated space; Etching the interlayer insulating material filling the separated space portion with a third mask having a plurality of openings spaced apart in the word line direction on the at least one separated space portion to expose each of the separated semiconductor layers, and revealing each exposed semiconductor layer. A tenth step of ion implanting the layer to form a source / drain of the memory cell; And an eleventh step of forming a bit line having a vertical connection plug in contact with the source / drain of the memory cell by depositing and etching the bit line material on the front surface of the substrate.

According to the Noah flash memory array according to the present invention, it is possible to increase the memory capacity by stacking word lines vertically without miniaturizing each memory cell.

In addition, according to the manufacturing method of the Noah flash memory array according to the present invention, there is an effect that the contact process for accessing each cell can be made simply.

1 to 10 are process perspective views exemplarily illustrating a step of manufacturing a first form of a noah flash memory array according to the present invention.
FIG. 11 is a cross-sectional view illustrating main parts of an inner structure by cutting one side of FIG. 10. FIG.
12 is an enlarged view illustrating main parts of the main part to explain a basic structure and an operation relationship of a no-flash memory array according to the present invention.
FIG. 13 is an electrical characteristic diagram illustrating that the program interference can be effectively prevented by plotting an unselected bit line during a program operation with the basic structure of FIG. 12.
14 to 25 are process perspective views exemplarily illustrating steps for manufacturing a second form of a noah flash memory array according to the present invention.
FIG. 26 is a cross-sectional view illustrating main parts of an inner structure by cutting one side of FIG. 25.
<Description of the code | symbol about the principal part of drawing>
10, 100: substrate
20: substrate etch stop material layer (nitride film)
32, 34, 36, 512, 522, 524, 532, 534: interlayer insulating film
42a, 44a, and 800: separation insulating film
52a1, 52a2, 54a1, 54a2, 722, 724, 742, 744: bitline
60, 600: insulating film having a charge storage layer
72, 74, 314, 316, 324, 326: semiconductor layer
72a, 72c, 74a, 74c, 314a, 314c, 316a, 324a, 324c, 326a: source / drain
72b, 72d, 74b, 74d, 314b, 324b: channel area
82, 84, 86, 832, 834: separation oxide film
92, 94, 920, 940: bitline
92a, 922, 942: vertical connection plugs
400, 410, 420: etching prevention layer (nitride film)

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 to 10 and 14 to 25 of the accompanying drawings are shown based on a repeating basic array in order to conceptually and illustratively represent the technical spirit of the present invention and those skilled in the art to understand it.

Therefore, it will be understood that the technical idea of the present invention is not limited to the structure represented in the accompanying drawings.

First, an embodiment of the structure of a noah flash memory array according to the present invention is basically, on the substrate (10, 100), as commonly expressed in Figures 10, 11, 12, 25 and 26 A plurality of word lines (WL11, WL21) or (WL12, WL22) stacked vertically spaced apart from each other; The channel region [(74b, 74d) or 324b] and the source / drain [(74a) in the wordline direction with an insulating film 60 or 600 having a charge storage layer horizontally side by side on each side of each wordline. , 74c) or (324a, 324c)] with a plurality of semiconductor layers (72, 74) or (314, 324) repeatedly formed; A plurality of interlayer insulating films [32, 34, 36 or (512, 522, 532)] formed on and under each of the word lines and the semiconductor layers parallel to the word lines; Vertical connection to pass through at least one of the plurality of interlayer insulating films and to contact upper and lower sources / drains (72a, 74a), (72c, 74c) or (314a, 324a, (314c, 324c)) of the semiconductor layers; It includes a plurality of bit lines (BL1, BL2) having a plug (92a or 922) formed to cross each of the word lines.

In this embodiment, as shown in FIG. 12, the word line 54a2 and the semiconductor layer 74 are formed to be parallel to each other with the insulating film 60 having the charge storage layer 64 interposed therebetween, and the semiconductor layer 74 is disposed. ) Has a basic structure in which the channel regions 74b, 74d and the source / drain 74a, 74c, 74e are formed repeatedly in the word line direction, and the basic structure has the interlayer insulating films 32, 34, 36 interposed therebetween. The core technology is that the bit lines 92 are vertically stacked and the upper and lower sources / drains (eg, 72a and 74a) formed at corresponding positions of the respective semiconductor layers are commonly contacted with the vertical connection plugs 92a.

That is, a plurality of word lines are vertically stacked (eg, 52a2, 54a2) with the interlayer insulating films 32, 34, and 36 interposed therebetween in the first direction (for example, the z-axis direction), and the bit lines are aligned with the first direction. The plurality of bit lines are spaced apart in a second vertical direction (eg, x-axis direction) (eg, 92 and 94), and the bit lines are horizontally parallel to the respective word lines by vertical connection plugs (eg, 92a). The upper and lower corresponding sources / drains (eg, 72a and 74a) of the formed plurality of semiconductor layers (eg, 72 and 74) may be contacted in common.

Here, the insulating film having the charge storage layer may be formed in a blocking oxide film 62 / nitride film 64 / tunneling oxide film 66 structure from each word line (eg, 54a2), as shown in FIG. In this case, the charge storage layer may be a nitride layer 64, but is not limited thereto and may have a floating gate structure that forms a charge storage layer as a conductive layer instead of the nitride layer.

In addition, the insulating layer having the charge storage layer may be formed to surround three surfaces of each of the semiconductor layers 72 and 74, as shown in FIG. 11, and as illustrated in FIG. 26, three surfaces of each word line 722 and 742. It may be formed surrounding the.

As described above, as the plurality of word lines and the plurality of bit lines are formed to vertically cross each other on a vertical plane (for example, the xz plane), the NOR flash memory array can also increase the memory capacity vertically as much as possible. Unlike the upper structure, the area expansion for contact of each memory cell does not occur as the memory capacity increases.

FIG. 12 illustrates an example of applying power to bit lines and word lines connected to each source / drain when a program operation is performed with the array according to the embodiment, and FIG. 13 shows a source when operating as shown in FIG. 12. The charge amount of electrons injected into the left storage node 64a of the specific cell including (S; 74a), the channel region 74b, and the drain (D; 74c) of the electrons injected into the right storage node 64b of the neighboring cell. This shows that there is a remarkable difference from the amount of charge. As a result, it can be seen that the read operation can be effectively performed through reverse read as well as the program operation.

Next, in the structure according to the basic embodiment, there are forms (structures) that can be implemented by extending the memory array in a third direction (eg, y-axis direction) perpendicular to the second direction. Explain.

<First Embodiment of Noah Flash Memory Array Structure>

10 and 11, in the basic embodiment, an isolation insulating layer (eg, 42a) is formed on an opposite side of each word line (eg, 52a2) on which each of the semiconductor layers (eg, 72) is formed. Each of the interlayer insulating layers (eg, 32 or 34) forms a stack structure with the isolation insulating layer, and each of the word lines (eg, 52a2) and the charge storage centering around the isolation insulating layer (eg, 42a) forming the stack structure. An insulating film 60 having a layer and a basic array (for example, the structure shown in FIG. 10 or 11) formed such that each semiconductor layer (for example, 72) is symmetrically formed (refer to FIG. 10 or 11), Vertical connection plugs (e.g. 92a) of each bit line (e.g., 92) are the source / drain (e.g., 72a, 74a and not shown neighboring base arrays) of the semiconductor layer located between the base arrays. In common with Is formed) to select.

That is, for example, a plurality of word lines and a plurality of bit lines (structure of the basic embodiment) formed vertically intersecting with each other on a vertical xz plane are formed based on a separation insulating layer formed in a stacked structure with each interlayer insulating layer on opposite sides of each word line. And a basic array (for example, the structure shown in FIG. 10 or 11) to be symmetrically, and the basic array is repeatedly formed with a vertical connection plug of each bit line in the y-axis direction.

Here, the separated oxide layer 82 is disposed between the bit lines including the vertical connection plugs to cover the channel regions 72b and 72d of the semiconductor layers 74b and 74d and to block electrical connections between neighboring bit lines 92 and 94. , 84, 86).

On the other hand, the isolation insulating films 42a and 44a are for preventing electrical connection and interference between word lines 52a1, 52a2; 54a1, 54a2 of the basic array symmetrically formed on both sides, and an insulating film having an oxide film or a high dielectric constant is preferable. Do.

Since each of the interlayer insulating films 32, 34, and 36 is an insulating material having an etch rate different from that of the insulating insulating films 42a and 44a, the interlayer insulating films 32 may be formed of a nitride film if the insulating insulating film is an oxide film.

The word lines 52a1, 52a2, 54a1, and 54a2 may be conductive materials having an etch rate different from those of the interlayer insulating films 32, 34, and 36. If the interlayer insulating films are nitride films, the silicon doped with impurities may be used. It may be formed of a material layer (eg, doped polycrystalline silicon or doped amorphous silicon).

Each of the semiconductor layers 72 and 74 may be a semiconductor material layer that can be deposited on the insulating film 60 having the charge storage layer. For example, each of the semiconductor layers 72 and 74 may be formed of a silicon-based material layer (polycrystalline silicon or amorphous silicon). have.

Each of the bit lines 92 and 94 may be formed of a silicon-based material layer (eg, doped polysilicon or doped amorphous silicon) that is doped with a metal or an impurity as a conductive material.

The substrate 10 may be any material capable of supporting the array structure as described above, and a flexible material (eg, a plastic material) may be selected and used as long as the substrate structure can be maintained.

At least one of each of the word lines 52a1, 52a2, 54a1, 54a2, each of the semiconductor layers 72, 74, and the bit lines 92, 94 is formed of silicon while using a silicon substrate as the substrate 10. In the case of forming the material layer, as shown in FIG. 11, between the substrate 10 and the lowest interlayer insulating layer 32, a material layer (eg, nitride film) 20 having a difference in etching rate between silicon is prevented in order to prevent etching of the substrate during the manufacturing process. Can be further formed.

In addition, the insulating film 60 having the charge storage layer has an ONO (blocking oxide film: 62 / nitride film: 64 / tunneling oxide film: 66) structure as shown in FIG. 12, and as shown in FIG. 11, the substrate etch stop material layer 20 The interlayer insulating layers 32, 34, and 36 and the word lines 52a1, 52a2, 54a1, and 54a2 constituting the basic array may be formed on the substrate.

<Second Embodiment Regarding Noah Flash Memory Array Structure>

25 and 26, in the basic embodiment, each word line (eg, 724) and the charge storage centered around the vertical connection plug (eg, 922) of each bit line (eg, 920). A basic array (for example, the structure shown in FIG. 25 or FIG. 26) formed such that the insulating film 600 having a layer, each of the semiconductor layers (eg, 316) and each of the interlayer dielectrics (eg, 524) are symmetrical to each other The insulating insulating layer 800 is formed in contact with the opposite side of each word line (eg, 724) on which the semiconductor layer (eg, 316) is formed between the base arrays.

That is, for example, a plurality of word lines and a plurality of bit lines (structure of the basic embodiment) formed vertically intersecting with each other on a vertical xz plane may be symmetrically with respect to the vertical connection plug of each bit line (eg, FIG. 25). Or the structure shown in FIG. 26, wherein the basic array is repeatedly formed with the isolation insulating film interposed in the y-axis direction.

Here, the isolation oxide layers 832 and 834 are filled between the vertical connection plugs to cover the channel regions 314b and 324b of the semiconductor layers and to block electrical connections between neighboring vertical connection plugs.

On the other hand, the isolation insulating film 800 is to block the electrical connection and interference between the word lines exposed to the same height between the basic array is preferably an oxide film or an insulating film having a high dielectric constant.

Each of the interlayer insulating films 512, 522, 532; 524, and 534 may be formed of the same material as the isolation insulating film 800.

Each word line 722, 724, 742, 744 and each bit line 920, 940 are formed of a silicon-based material layer (eg, doped polysilicon or doped amorphous silicon) or a metal layer doped with impurities. Can be.

Each of the semiconductor layers 314, 316, 324, and 326 is preferably formed of a single crystal silicon layer.

The substrate 10 may be any material capable of supporting the array structure as described above, and a flexible material (eg, a plastic material) may be selected and used as long as the substrate structure can be maintained.

An etch stop layer (eg, nitride layers 410 and 420) may be further formed on uppermost interlayer insulating layers 532 and 534 among the plurality of interlayer insulating layers so as to be symmetrical with respect to the vertical connection plugs (eg, 922) of the bit lines. .

In addition, the insulating film 600 having the charge storage layer has an ONO structure as shown in FIG. 12, and as shown in FIG. 26, an interlayer insulating film 512, 522, 532; 524, 534 constituting a basic array on a substrate, and a semiconductor. The layers 314, 316, 324 and 326 may be formed to surround the etch stop layers 410 and 420.

Next, a method of manufacturing a Noah flash memory array having each of the above-described shapes will be described with reference to the accompanying drawings.

<First Embodiment of Manufacturing Method of Noah Flash Memory Array>

This is a method of manufacturing the shape according to the first embodiment of the Noah flash memory array structure, and is manufactured through the steps illustrated in FIGS. 1 to 10.

First, as shown in FIG. 1, n layers are repeatedly stacked in order of " interlayer insulating film 32-&gt; separation insulating film 42 &quot; on the predetermined substrate 10 (in FIG. The n + 1th interlayer insulating layer 36 is further stacked on the nth isolation insulating layer 44 and then etched with a first mask patterned in the word line direction to form a plurality of basic array patterns 32, 42, 34, 44, 36). In FIG. 1, only the basic array pattern is illustrated, but the plurality of basic array patterns are spaced at a predetermined interval in the bit line direction (a first step).

In this case, since the isolation insulating films 42 and 44 are intended to block electrical connection and interference between neighboring word lines in the future, the isolation insulating films 42 and 44 may be formed of an oxide film or an insulating film having a high dielectric constant.

The interlayer insulating films 32, 34, and 36 may be formed of an insulating material having a difference in etching rate from that of the isolation insulating films 42 and 44, and thus may be formed of a nitride film having a lower etching rate than that of the insulating insulating film.

The substrate 10 may be any material capable of supporting the array structure, and a flexible material (eg, a plastic material) may be selected and used as long as the substrate structure can be maintained.

In the case where a silicon substrate is used as the substrate 10 and at least one or more of a word line, a semiconductor layer, and a bit line are formed of a silicon based material layer in a subsequent process, as shown in FIG. 1, a substrate such as a nitride film is formed on the substrate 10. It is preferable to further form the etch stop material layer 20 and to proceed with the above process.

Next, as shown in FIG. 2, the plurality of basic array patterns are isotropically etched by using the difference in the etch rate between the interlayer insulating layers 32, 34, and 36 and the separation insulating layers 42 and 44 to laterally align the separation insulating layers. Recess (second step). 2 shows recessed isolation films 42a and 44a.

3, the word line material is deposited on the entire surface of the substrate and etched anisotropically to fill the recessed portions of the respective basic array patterns with the word line materials 52 and 54 (third step).

In this case, the word line material may be a conductive material having an etch rate different from that of the interlayer insulating films 32, 34, and 36. If the interlayer insulating film is a nitride film, a silicon-based material (eg, doped polycrystalline silicon or doped with impurities) may be used. Amorphous silicon) is preferred for depositing and etching to fill the recessed areas.

Next, as shown in FIG. 4, the filled wordline materials 52 and 54 are isotropically etched to recess laterally (fourth step). 4 shows recessed wordline materials 52a and 54a.

In this case, it is preferable that the recess depth of the word line material is 1/2 to 2/3 of the depth of the isolation insulating film recess in the second step. Of course, when using a silicon-based material as a semiconductor material, it is difficult to form source / drain and channel regions sufficient to secure the driving capability of the cell. However, when the silicon-based material is larger than 2/3, the isolation insulating film is relatively reduced, so that the distance between neighboring word lines is reduced. This is because there is a problem of insulation or interference or a problem of unnecessarily increasing the horizontal area.

Thereafter, an insulating film having a charge storage layer is formed on the recessed wordline materials 52a and 54a (a fifth step). In this case, as shown in FIG. 5, an insulating film 60 having the charge storage layer may be formed on the entire surface of the substrate including the recessed word line materials 52a and 54a. In the case where the insulating film 60 is formed in an oxide film / nitride film / oxide film structure, a blocking oxide film 62-> nitride film 64-> tunnel oxide film 66 is formed in the same manner as a known method.

Next, as shown in FIG. 6, a semiconductor material is deposited on the entire surface of the substrate, and anisotropically etched to fill the recessed portions on the insulating layer 60 with the semiconductor materials 72 and 74 (sixth step).

In this case, the semiconductor material may be a semiconductor capable of being deposited on the insulating layer 60 having the charge storage layer. For example, the semiconductor material may be formed of silicon-based material (polycrystalline silicon or amorphous silicon).

Subsequently, as shown in FIG. 7, the separation oxide film 80 is deposited and planarized on the entire surface of the substrate (seventh step).

Next, as shown in FIG. 8, a second mask 89 patterned in the bit line direction is formed on the planarized separation oxide film 80 using a photoresist film PR, and the like, and the separation oxide film is etched as shown in FIG. 9. The filled semiconductor material 72, 74 is exposed between the etched separated oxide layers 82, 84, and 86 (Eighth Step).

Next, as shown in FIG. 9, ion implantation is performed on the exposed semiconductor materials 72 and 74 to form source / drain 72a and 72c and 74a and 74c of the memory cell as shown in FIG. 11 (ninth step). . In this case, ion implantation may use plasma doping or the like.

Finally, as shown in FIG. 10, a bit line material (eg, a silicon-based material or a metal doped with impurities) is deposited and planarized on the entire surface of the substrate, thereby forming the bit line 92 between the etched isolation oxide layers 82, 84, and 86. 94) (step 10).

As described above, since the bit line material directly contacts the ion implanted source / drain, the conventional contact process for connecting (contacting) each cell is unnecessary.

<Second Embodiment Regarding Manufacturing Method of Noah Flash Memory Array>

This is a method of manufacturing the shape according to the second embodiment of the Noah flash memory array structure, which is manufactured through each step illustrated in FIGS. 14 to 25.

First, as shown in FIG. 14, n-layers are repeatedly stacked on a predetermined substrate 100 in the order of "stack-mediated layer 210-> semiconductor layer 310" (in FIG. 14, repeatedly stacked twice). Further, the n + 1 th stacking layer 230 and the etch stop layer 400 are further stacked on the n th semiconductor layer 320, and then etched with a first mask patterned in a word line direction to form a plurality of basic array patterns ( 210, 310, 220, 320, 230, 400). In FIG. 14, only the basic array pattern is illustrated, but the plurality of basic array patterns are spaced at a predetermined interval in the bit line direction (a first step).

In this case, the substrate 100 may be any material capable of supporting the array structure, and a flexible material (eg, a plastic material) may be selected and used as long as the substrate structure can be maintained.

In addition, when the silicon substrate is used as the substrate 100, the stacking layers 210, 220, and 230 are similar to silicon and have a lattice structure but have different etching rates (eg, silicon germanium). 310 and 320 may be formed of a material having a similar lattice structure to that of the stacking layer and having an etch rate difference (for example, silicon), alternately by epitaxy.

In addition, the etch stop layer 400 is preferably formed of a nitride film to function as an etch stopper during the planarization process.

Next, as shown in FIG. 15, the plurality of basic array patterns are isotropically etched to recess the stacking layers 210, 220, and 230 laterally (second step). 15 shows recessed stacking layers 212, 222, 232.

At this time, it is preferable that the stacking layer 210, 220, 230 is sufficiently recessed to leave only a portion of the space for forming the vertical connection plug of the bit line.

Next, as shown in FIG. 16, an interlayer insulating film material such as an oxide film is deposited on the entire surface of the substrate, and anisotropically etched to fill the recessed portions of the respective basic array patterns with the interlayer insulating film materials 510, 520, and 530 ( Third step).

Next, as shown in FIG. 17, each of the filled basic array patterns is etched again isotropically, and this time, the semiconductor layers 310 and 320 are laterally recessed (fourth step). 17 shows recessed semiconductor layers 312 and 322.

At this time, the depth of the recess is lower than the depth of the stacking layer in the second step.

Thereafter, an insulating film having a charge storage layer is formed on the recessed semiconductor layer (fifth step). In this case, as shown in FIG. 18, an insulating film 600 having the charge storage layer may be formed on the entire surface of the substrate including the recessed semiconductor layers 312 and 322. In addition, when the insulating film 600 is formed in an oxide film / nitride film / oxide film structure, a blocking oxide film-> nitride film-> tunneling oxide film is sequentially formed as in a known method.

Next, as shown in FIG. 19, a word line material is deposited on the entire surface of the substrate and anisotropically etched to fill the recessed portions on the insulating layer with the word line materials 720 and 740 (Sixth Step).

In this case, the word line materials 720 and 740 may be a metal as well as a silicon-based material doped with impurities.

Next, as shown in FIG. 20, a separation insulating film 800 is deposited and planarized on the entire surface of the substrate (seventh step).

In this case, since the isolation insulating film 800 fills between the basic array patterns and prevents electrical insulation and interference between neighboring word lines exposed between the basic array patterns, an oxide film or an insulating film having a high dielectric constant is preferable.

In addition, the planarization process may be performed by a known CMP process, in which case the nitride film formed of the etch stop layer 400 serves as an etch stopper. In this case, the insulating layer 600 having the charge storage layer formed on the etch stop layer 400 in FIG. 20 is removed.

Next, as shown in FIG. 21, a second mask 810 opened in a word line direction is formed in the center of the etch stop layer 400 using a photoresist film PR, and the like, using the etch stop layer 400 / n + 1. A second trench mediation layer 232 / n "semiconductor layer / lamination media layer" (322/222/312/212) is sequentially etched to form a trench 820 in the center to separate each of the basic array pattern (second) Step 8).

Subsequently, as shown in FIG. 22, the stacking layer 234 remaining in each of the separated basic array patterns is removed, and as shown in FIG. 23, the interlayer insulating film material 830 is filled in the separated space 822. Planarize (ninth step).

In this case, the planarization process may be performed by a known CMP process. In this case, the nitride films 410 and 420 separated by the etch stop layer serve as an etch stopper. In this case, the insulating layer 600 having the charge storage layer formed on the etch stop layers 410 and 420 separated from FIG. 23 is removed.

Next, as shown in FIG. 24, an interlayer insulating film material 830 filling the separated space portion with a third mask (not shown) having a plurality of openings 824 at predetermined intervals in a word line direction on the separated space portion. The semiconductor layers 324 and 326 are etched to expose the semiconductor layers 324 and 326, and as shown in FIG. 26, ion implanted into each of the exposed semiconductor layers to source / drain the memory cells 314a and 314c; 324a and 324c; 316a. 326a) (step 10).

In this case, when the substrate 100 is silicon, the etching of the interlayer insulating material 830 may be such that the height of the minimum interlayer insulating film 510 remains so that the vertical connection plugs of the bit lines are not electrically connected to the substrate afterwards. 24), the ion implantation may use plasma doping or the like.

Finally, as shown in FIG. 25, bit line material is deposited and etched on the entire surface of the substrate to form bit lines 920 and 940 having vertical connection plugs 922 and 942 contacting the source / drain of the memory cell (see FIG. 25). Eleventh step).

In this case, a silicon-based material doped with impurities as the bit line material may be used, but a metal is more preferable.

As described above, since the bit line material directly contacts the ion implanted source / drain, the conventional contact process for connecting (contacting) each cell is unnecessary.

Industrial availability

Noah flash memory array and a method for manufacturing the same according to the present invention can increase the memory capacity by stacking word lines vertically without miniaturizing each memory cell, and can easily perform a contact process for accessing each cell. As a result, industrial applicability is very high.

Claims (13)

A plurality of word lines stacked vertically spaced apart on the substrate;
A plurality of semiconductor layers in which channel regions and sources / drains are repeatedly formed in a word line direction with an insulating film having a charge storage layer parallel to each other on one side of each word line;
A plurality of interlayer insulating films formed on the upper and lower surfaces of the semiconductor lines parallel to the word lines and the word lines;
And a plurality of bit lines passing through at least one of the plurality of interlayer insulating layers and having vertical connection plugs to contact upper and lower sources / drains of the semiconductor layers and intersecting the word lines. Flash memory array. The method of claim 1,
Separate insulating films are formed on opposite sides of the word lines on which the semiconductor layers are formed,
The interlayer insulating films form a stacked structure with the separation insulating film,
The word array, the insulating layer having the charge storage layer, and a basic array formed to be symmetrical with respect to each of the word lines, the insulating layer having the charge storage layer, are repeatedly formed in the bit line direction with respect to the isolation insulating layer forming the stacked structure.
And a vertical connection plug of each bit line is formed in common contact with a source / drain of a semiconductor layer positioned between the base arrays. The method of claim 2,
Each of the interlayer insulating films is a nitride film,
Each word line is a doped layer of silicon-based material,
And each semiconductor layer is a silicon-based material layer. The method of claim 1,
A basic array in which the word lines, the insulating films having the charge storage layers, the semiconductor layers and the interlayer insulating films are symmetrical with respect to the vertical connection plugs of the respective bit lines is repeatedly formed in the bit line direction,
And a separation insulating layer formed between the base arrays and in contact with opposite sides of the word lines on which the semiconductor layers are formed. The method of claim 4, wherein
A nitride film is further formed on the uppermost interlayer insulating film of the plurality of interlayer insulating films so as to be symmetrical to the vertical connection plugs of the bit lines.
Each of the interlayer insulating films is an oxide film,
Each word line is a doped silicon-based material layer or a metal layer,
And each semiconductor layer is a single crystal silicon layer. 6. The method according to any one of claims 1 to 5,
And an insulating film having the charge storage layer has a blocking oxide film / nitride film / tunneling oxide film structure from each word line. In manufacturing a stacked Noah flash memory array according to claim 2,
N layers are repeatedly stacked on a predetermined substrate in the order of " interlayer insulating film- &gt; separation insulating film &quot;, and the n + 1th interlayer insulating film is further laminated on the nth insulating insulating film, and then patterned in the word line direction. Etching to form a plurality of basic array patterns;
A second step of isotropically etching the plurality of basic array patterns to recess the isolation insulating layer laterally;
Depositing a wordline material on the entire surface of the substrate and etching anisotropically to fill the recessed portions of the respective basic array patterns with the wordline material;
A fourth step of isotropically etching the filled wordline material to recess laterally;
A fifth step of forming an insulating film having a charge storage layer on said recessed wordline material;
Depositing a semiconductor material over the entire surface of the substrate and etching anisotropically to fill the recessed portion of the insulating film with the semiconductor material;
A seventh step of depositing and planarizing a separation oxide film over the entire substrate;
An eighth step of forming a second mask patterned in a bit line direction on the planarized separated oxide layer and etching the separated oxide layer to expose the filled semiconductor material between the etched separated oxide layers;
A ninth step of ion implanting the exposed semiconductor material to form a source / drain of a memory cell;
And forming a bit line between the etched separated oxide layers by depositing and planarizing the bit line material on the entire surface of the substrate. The method of claim 7, wherein
The interlayer insulating film is a nitride film,
The isolation insulating film is an oxide film,
The word line material is a silicon-based material doped with impurities,
And the bit line material is a silicon-based material or a metal doped with an impurity. The method of claim 8,
The recess etch depth of the fourth step is 1/2 to 2/3 of the recess etch depth of the second step. In manufacturing a stacked Noah flash memory array according to claim 4,
N layers are repeatedly stacked on a predetermined substrate in the order of "stacking media layer-> semiconductor layer", and n + 1th stacking media layer and an etch stop layer are further stacked on the nth semiconductor layer, and then patterned in the word line direction. A first step of forming a plurality of basic array patterns by etching with a first mask;
A second step of isotropically etching the plurality of basic array patterns to recess the stacking layer in a lateral direction;
Depositing an interlayer dielectric material on the entire surface of the substrate and etching anisotropically to fill the recessed portions of the respective basic array patterns with the interlayer dielectric material;
A fourth step of isotropically etching each of the filled basic array patterns to recess the semiconductor layer in a lateral direction;
A fifth step of forming an insulating film having a charge storage layer on said recessed semiconductor layer;
Depositing a wordline material on the entire surface of the substrate and etching anisotropically to fill the recessed portion of the insulating layer with the wordline material;
A seventh step of depositing and planarizing a separation insulating film over the entire substrate;
A second mask that separates each of the basic array patterns by sequentially etching the etch stop layer / n + 1 th stacking layer / n " semiconductor layer / laminate medial layer &quot; with a second mask open in the word line direction among the etch stop layers; 8 steps;
A ninth step of removing the stacking layers remaining in each of the separated basic array patterns, and then filling and planarizing the interlayer insulating film material in the separated space;
The interlayer insulating material filling the separated spaces is etched with a third mask having a plurality of openings spaced apart at predetermined intervals in a word line direction on the separated spaced portions to expose each of the separated semiconductor layers and to expose each of the exposed semiconductor layers. A tenth step of ion implanting the layer to form a source / drain of the memory cell;
And depositing a bit line material on the entire surface of the substrate and etching the bit line material to form a bit line having a vertical connection plug in contact with the source / drain of the memory cell. . The method of claim 10,
The stacking of the stacking media layer and the semiconductor layer is by an epitaxy method,
The material of the stacking layer is a lattice structure Noah flash memory array, characterized in that the lattice structure is similar to the material of the semiconductor layer. The method of claim 11,
The material of the substrate and the semiconductor layer is silicon,
The material of the stacking layer is silicon germanium,
The material of the etch stop layer is nitride (nitride),
The interlayer insulating film and the isolation insulating film are oxide films,
And said word line material and said bit line material are silicon-based materials or metals doped with impurities. 13. The method according to any one of claims 7 to 12,
N is a natural number of 2 or more,
The insulating film having the charge storage layer of the fifth step is formed of an oxide film / nitride film / oxide film surrounding each basic array pattern.

Images