JP2009231300A - Semiconductor memory and fabrication method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory which has a cavity between the word lines and is configured, such that the side surface of a control gate electrode is not exposed to the cavity and degradation in the breakdown voltage between the word lines is prevented. <P>SOLUTION: A semiconductor memory includes a semiconductor substrate 1, a plurality of word lines WL formed on the semiconductor substrate at a predetermined interval and having a first insulating film 2; a charge storage layer 3, a second insulating film 4 and a control gate electrode 5 laminated sequentially; a third insulating film 11 formed on the sidewall of the word line and having a height which is larger than that of the word line; a fourth insulating film 18, formed on the word lines and above the semiconductor substrate between adjoining word lines; and a cavity 19 located between adjoining word lines and having an upper portion covered with the fourth insulating film. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof.

  In a conventional nonvolatile semiconductor memory device, a word line having a stacked structure of a tunnel oxide film, a floating gate electrode, an interpoly insulating film, and a control gate electrode is filled with an oxide film or a nitride film. However, as the device is miniaturized, the distance between the word lines becomes shorter, the variation in the threshold voltage of the floating gate electrode due to the parasitic capacitance generated between the floating gate electrodes of adjacent word lines, and the parasitic capacitance generated between the floating gate and the diffusion layer. The problem is the decrease in writing speed. In addition, there is a problem that a buried material between word lines is destroyed by a high electric field applied between the electrodes.

  In order to solve such a problem, it has been proposed to provide an air gap (cavity) between word lines to reduce parasitic capacitance and to suppress variations in threshold voltage of the floating gate electrode and a decrease in writing speed.

  For example, a method is known in which a word line and an oxide film with poor embedding property are deposited between the word lines and a gap is provided between adjacent floating gate electrodes (see, for example, Patent Document 1). However, this method has a problem in that the position and shape of the air gap vary, and the threshold voltage varies from cell to cell, reducing reliability.

  As a technique for solving such a problem, a spacer made of a silicon nitride film covering the word lines is formed, a sacrificial film made of a silicon oxide film is formed between the word lines to a predetermined height, and silicon nitride is formed on the sacrificial film. A method of forming an air gap by forming a mini-spacer made of a film, removing a sacrificial film while ensuring a selection ratio with a silicon nitride film, and depositing a cover film with poor embeddability is known (for example, Patent Document 2).

  In addition, without forming a mini-spacer, a sacrificial film is formed between the word lines up to the same height as the word line, this sacrificial film is removed, and silicidation is performed to reduce the resistance of the control gate electrode, thereby embedding. There is also a method of forming an air gap by depositing a cover film having a bad shape.

  However, in this method, a region that is not covered with the cover film or the side wall film (spacer oxide film) and is exposed to the air gap may be formed on the side surface of the control gate electrode. Therefore, problems such as surface leakage between word lines via the cover film may occur.

Further, when nickel is used for silicidation of the control gate electrode, the control gate electrode expands. As a result, the side wall surface exposed to the air gap increases, and problems such as the above-described surface leakage are likely to occur. Furthermore, there is a problem in that the cover film enters between the control gate electrodes, and the electric field concentrates on this portion, causing dielectric breakdown, thereby degrading the breakdown voltage between the word lines.
US Patent Application Publication No. 2006/0001073 US Patent Application Publication No. 2007/0096202

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a cavity between word lines, a side surface of a control gate electrode not exposed to the cavity, and preventing breakdown voltage degradation between word lines, and a method of manufacturing the same. To do.

  A semiconductor memory device according to one embodiment of the present invention includes a semiconductor substrate, a first insulating film, a charge storage layer, a second insulating film, and a control layer which are formed over the semiconductor substrate at predetermined intervals and are sequentially stacked. A plurality of word lines each having a gate electrode; a third insulating film formed on a side wall of the word line and having a height equal to or higher than the height of the word line; and between the word lines on and adjacent to the word line A fourth insulating film formed above the semiconductor substrate, and a cavity located between the adjacent word lines and having an upper portion covered with the fourth insulating film.

  A method for manufacturing a semiconductor memory device according to one embodiment of the present invention includes a first insulating film, a charge storage layer, a second insulating film, a control gate electrode, and a first gate electrode, which are sequentially stacked on a semiconductor substrate at a predetermined interval. Forming a plurality of word lines each including three insulating films, forming an oxide film so as to cover the word lines and the semiconductor substrate, and sacrificing the oxide film so as to embed between the word lines Forming a film; removing the sacrificial film and the oxide film so that an upper surface of the third insulating film is exposed; removing the third insulating film; A step of exposing, a step of siliciding the control gate electrode, a step of removing the sacrificial film between the word lines, and a fourth insulating film so as to cover an upper portion of the region where the sacrificial film has been removed. Form And the extent, those with a.

  In addition, a method for manufacturing a semiconductor memory device according to one embodiment of the present invention includes a first insulating film, a charge storage layer, a second insulating film, and a polysilicon film, which are sequentially stacked on a semiconductor substrate at a predetermined interval. Forming a plurality of word lines each including a control gate electrode and a third insulating film, forming an oxide film so as to cover the word lines and the semiconductor substrate, and filling the space between the word lines Forming a sacrificial film on the oxide film, removing the sacrificial film and the oxide film so that an upper surface of the third insulating film is exposed, removing the third insulating film, Exposing a top surface of the control gate electrode; removing at least an upper portion of the polysilicon film of the control gate electrode; forming a metal layer between the oxide films above the second insulating film; , Removing the sacrificial layer between the serial word lines, and forming a fourth insulating film so as to cover the upper part of the sacrificial film is removed regions are those comprising a.

  According to the present invention, the side surface of the control gate electrode is not exposed to the cavity between the word lines, and the breakdown voltage deterioration between the word lines can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  (First Embodiment) FIGS. 1 to 8 are sectional views for explaining a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention. In each figure, (a) shows a longitudinal section of the memory cell array portion along the bit line direction, and (b) shows a longitudinal section of the end portion of the memory cell array and the select gate transistor along the bit line direction.

  As shown in FIG. 1, a tunnel oxide film 2 made of a silicon oxide film and a floating gate electrode 3 made of a polysilicon film are formed on a semiconductor substrate 1.

  Then, the floating gate electrode 3, the tunnel oxide film 2, and the semiconductor substrate 1 are removed at a predetermined interval along the first direction (bit line direction) to form a trench. A silicon oxide film is buried in the trench to a predetermined height to form an element isolation region (not shown).

  Then, an interpoly insulating film 4 is formed so as to cover the floating gate electrode 3 and the element isolation region, and a first polysilicon film is formed on the interpoly insulating film 4. A part of the first polysilicon film and the interpoly insulating film 4 in a region where the selection transistor ST and the peripheral transistor (not shown) are formed is removed to form a groove. A second polysilicon film is formed on the first polysilicon film so as to fill this groove.

  In the memory cell array portion, the control gate electrode 5 is composed of a first polysilicon film and a second polysilicon film. The select gate transistor ST and the peripheral transistor have an etching interpoly structure in which the polysilicon films (electrode layers) above and below the interpoly insulating film 4 are connected. The film thickness of the control gate electrode 5 is, for example, 95 nm.

  Then, a silicon nitride film 6 is formed on the control gate electrode 5 with a film thickness of 30 nm, for example. Subsequently, the silicon nitride film 6, the control gate electrode 5, the interpoly insulating film 4, the floating gate electrode 3, and the tunnel are spaced at predetermined intervals along a second direction (word line direction) orthogonal to the first direction. By removing the oxide film 2, the word line WL and the select transistor ST are processed. One selection transistor ST is disposed at each of both ends of the plurality of word lines WL.

  As shown in FIG. 2, a silicon oxide film (spacer oxide film) 11 is formed by a CVD (Chemical Vapor Deposition) method so as to cover the word line WL, the select transistor ST, and the semiconductor substrate 1.

  Here, the thickness of the silicon oxide film 11 is set to be 3 nm or more and 15 nm or less. In order to prevent surface leakage, an oxide film or the like must be formed so as to cover the word line WL, and the silicon oxide film 11 is formed for this reason.

  Then, for example, arsenic is implanted into the surface portion of the semiconductor substrate 1 between the word lines WL, between the select transistors ST, and between the select transistor ST and the word line WL1 adjacent thereto, thereby forming a diffusion layer (not shown). .

  Subsequently, a sacrificial film 12 made of a silicon nitride film is formed on the silicon oxide film 11 by a CVD method so as to embed between the word lines WL.

  As shown in FIG. 3, RIE (reactive ion etching) is performed so that the surface of the semiconductor substrate 1 is exposed between the select transistors ST and between the select transistor ST and the word line WL1 adjacent thereto, The sacrificial film 12 and the silicon oxide film 11 are removed.

  As a result, sidewalls (sidewall films) SW composed of the sacrificial film 12 and the silicon oxide film 11 are formed on the sidewalls of the select transistor ST and the sidewalls of the word line WL1 on the select transistor ST side. For example, arsenic is implanted using the sidewall SW as a mask to form a high-concentration diffusion layer (not shown) on the surface of the semiconductor substrate 1 between the select transistors ST to form an LDD (Lightly Doped Drain) structure.

  At this time, the upper surface of the silicon nitride film 6 is exposed.

  As shown in FIG. 4, a silicon oxide film 14 is formed by a CVD method so as to cover the word line WL, the select transistor ST, the sidewall SW, and the semiconductor substrate 1, and a silicon nitride film 15 is formed on the silicon oxide film 14 by CVD. Form by law. The silicon nitride film 15 is formed at a higher temperature than the silicon nitride film (sacrificial film) 12 to form a high-density film.

  Then, a silicon oxide film 16 is formed by a CVD method so as to embed between the select transistors ST and between the select transistors and the word line WL1.

  Subsequently, planarization is performed by CMP (Chemical Mechanical Polishing) using the silicon nitride film 6 as a stopper.

  As shown in FIG. 5, the silicon nitride film 6 is removed by CDE (Chemical Dry Etching) so that the upper surface of the control gate electrode 5 is exposed. Since this CDE is performed under the condition that the selection ratio between the silicon nitride film and the silicon oxide film is obtained, a part of the sacrificial film 12 is also removed, and the upper surface position becomes substantially the same as the upper surface position of the control gate electrode 5. The upper surface position of the control gate electrode 5 is lower than the upper surface position of the silicon oxide film 11.

  At this time, the silicon oxide film is also removed to some extent, so that the upper surface of the sacrificial film 12 of the sidewall SW is exposed.

  As shown in FIG. 6, the sacrificial film 12 is removed by wet etching. A phosphoric acid solution (hot phosphoric acid) or the like can be used as the chemical solution. At this time, the silicon nitride film 15 can also be removed. However, since the silicon nitride film 15 is a higher density film than the sacrificial film 12 and has high etching resistance, the amount removed is small.

  The remaining silicon nitride film 15 functions as a stopper when the contact hole is opened in the subsequent bit line contact formation step.

  As shown in FIG. 7, a part or all of the control gate electrode 5 is silicided from the upper surface of the control gate electrode 5 to form a silicide layer 17. Ni is used for the silicide metal material, for example, heating is performed at 350 ° C. for 120 seconds, and then heating is performed at 500 ° C. for 60 seconds. When silicidation is performed using Ni, the control gate electrode 5 expands. For example, the film thickness is changed from 95 nm to 115 nm by silicidation. The reason for heating at a low temperature first and then heating at a high temperature is to suppress the degree of expansion of the silicide layer.

  In the process shown in FIG. 5, since the upper surface position of the control gate electrode 5 is lower than the upper surface position of the silicon oxide film 11, even if the control gate electrode 5 expands due to silicidation, the upper surface position of the control gate electrode 5 is It is not higher than the upper surface position of the silicon oxide film 11.

  As shown in FIG. 8, a silicon oxide film (cover film) 18 is formed by plasma CVD. Since the plasma CVD method is a deposition method with poor embeddability, the sacrificial film 12 between the word lines WL and the sidewall SW is removed without entering between the word lines WL having a narrow interval (between the silicon oxide films 11). The region can be a cavity (air gap) 19.

  Further, the height of the side wall of the word line WL from the surface of the substrate 1 of the silicon oxide film 11 is not less than the height of the word line WL. That is, the side surface of the control gate electrode 5 is not exposed to the cavity 19. Further, since the silicon oxide film 18 does not enter between the word lines WL, the upper end of the cavity 19 is formed higher than the upper surface of the control gate electrode 5.

  That is, the side surface of the control gate electrode 5 is covered with the silicon oxide film 11. Further, between the word lines WL, the lower end of the silicon oxide film 18 is formed at a position higher than the upper surface of the control gate electrode 5.

  Accordingly, since the cavity can be formed between the word lines WL without exposing the side wall surface of the control gate electrode 5 to the cavity 19, the occurrence of surface leak between the word lines WL can be prevented, and the reliability can be improved.

  In addition, since the silicon oxide film 18 does not enter between the control gate electrodes 5 of the adjacent word lines WL, and an electric field is uniformly applied between the control gate electrodes 5, it is possible to prevent deterioration of the breakdown voltage between the word lines.

  (Comparative Example) A method of manufacturing a semiconductor memory device according to a comparative example is shown in FIGS. Since the steps shown in FIG. 4 are the same as those in the first embodiment, the description thereof is omitted.

  As shown in FIG. 9, the silicon nitride film 6 and the like are removed by RIE (reactive ion etching) so that the upper surface of the control gate electrode 5 and the upper surface of the sacrificial film 12 of the sidewall SW are exposed. At this time, the height of the silicon oxide film 11 is lower than the word line WL. This is because the silicidation is also performed from the side wall of the control gate electrode 5 during the silicidation described later, thereby promoting the silicidation.

  In the present invention, silicidation is performed only from the upper surface of the control gate electrode 5 as described above. However, silicidation can be promoted more than the comparative example by adjusting the relationship between temperature and time.

  As shown in FIG. 10, the sacrificial film 12 is removed by wet etching. A phosphoric acid solution (hot phosphoric acid) or the like can be used as the chemical solution.

  As shown in FIG. 11, part or all of the control gate electrode 5 is silicided to form a silicide layer 17. Ni is used as the silicide metal material, for example, heating is performed at 350 ° C. for 60 seconds, and then heating is performed at 500 ° C. for 60 seconds. When silicidation is performed using Ni, the control gate electrode 5 expands. Therefore, on the side surface of the control gate electrode 5, the region a1 that is not covered with the silicon oxide film 11 increases.

  As shown in FIG. 12, a silicon oxide film 30 is formed by plasma CVD. Since the plasma CVD method is a deposition method with poor embeddability, the region from which the sacrificial film 12 has been removed becomes a cavity 31 without being embedded.

  At this time, a region which is not covered with either of the silicon oxide films 11 and 30 and is exposed to the cavity 31 may be generated on the side surface of the control gate electrode 5. When such a region occurs, problems such as surface leakage between word lines WL occur.

  In addition, since the silicon oxide film 30 enters between the control gate electrodes 5, the electric field concentrates on this portion when a voltage is applied, causing dielectric breakdown, thereby degrading reliability.

  On the other hand, in the first embodiment, since the silicon oxide film 11 is formed higher than the word line WL and covers the side surface of the control gate electrode 5, the side surface of the control gate electrode is not exposed in the cavity.

  In addition, since the silicon oxide film 18 does not enter between the adjacent control gate electrodes 5, an electric field is uniformly applied between the control gate electrodes 5, and deterioration of the breakdown voltage between the word lines can be prevented.

  (Second Embodiment) FIGS. 13 to 16 are process sectional views for explaining a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention. In each figure, (a) shows a longitudinal section of the memory cell array portion along the bit line direction, and (b) shows a longitudinal section of the end portion of the memory cell array and the select gate transistor along the bit line direction. Since the processes up to the step shown in FIG. 5 are the same as those in the first embodiment, description thereof will be omitted.

  As shown in FIG. 13, the polysilicon film forming the control gate electrode 5 is etched back by CDE. Although all of the polysilicon film may be removed, a part of the polysilicon film is left in consideration of the reliability of the interpoly insulating film 4.

  As shown in FIG. 14, the barrier metal 21 and the metal 22 are formed by sputtering. The barrier metal 21 is, for example, TiN or Ti, and the metal 22 is, for example, W (tungsten). The control gate electrode 5 has a laminated structure of a polysilicon film and a metal.

  Then, planarization is performed by CMP. As a result, the upper surface of the control gate electrode 5 is flush with the upper surface of the silicon oxide film 11. Moreover, the upper surface of the sacrificial film 12 of the sidewall SW is exposed by this planarization process.

  As shown in FIG. 15, the sacrificial film 12 is removed under the condition that the selection ratio between the silicon oxide film 11 and the sacrificial film 12 is obtained. For example, the sacrificial film 12 is removed by wet etching. A phosphoric acid solution (hot phosphoric acid) or the like can be used as the chemical solution. The silicon nitride film 15 is a film having a higher density than the sacrificial film 12 and has a high etching resistance, so that only part of the silicon nitride film 15 is removed.

  The remaining silicon nitride film 15 functions as a stopper when the contact hole is opened in the subsequent bit line contact formation step.

  At this time, the barrier metal 21 and the metal 22 can be somewhat removed. A part of the barrier metal 21 and the metal 22 may be removed by CDE or the like to reduce the height of the control gate electrode.

  As shown in FIG. 16, a silicon oxide film 23 is formed by plasma CVD. Since the plasma CVD method is a deposition method with poor embeddability, the sacrificial film 12 between the word lines WL and the sidewall SW is removed without entering between the word lines WL having a narrow interval (between the silicon oxide films 11). The region can be a cavity (air gap) 24.

  Further, since the height of the silicon oxide film 11 on the side wall of the word line is equal to or higher than the height of the word line WL, the silicon oxide film 23 does not enter between the word lines WL, and the upper end of the cavity 24 is higher than the upper surface of the control gate electrode 5. It is formed.

  That is, the side surface of the control gate electrode 5 is covered with the silicon oxide film 11. Further, the lower end of the silicon oxide film 23 is formed at a position higher than the upper surface of the control gate electrode 5 between the word lines WL.

  Therefore, since the cavity can be formed between the word lines WL without exposing the side wall surface of the control gate electrode 5 to the cavity 24, the occurrence of surface leakage between the word lines WL can be prevented and the reliability can be improved.

  Further, since the silicon oxide film 23 does not enter between the control gate electrodes 5 of the adjacent word lines WL, and an electric field is uniformly applied between the control gate electrodes 5, it is possible to prevent the breakdown voltage between the word lines.

  Each of the above-described embodiments is an example and should be considered as not limiting. For example, the semiconductor memory device according to the above embodiment has a stack gate type memory cell structure of control gate electrode / interpoly insulating film / floating gate electrode / tunnel oxide film, but an air gap (cavity) is provided between adjacent cells. Thus, the present invention can also be applied to other memory cell structures capable of reducing the parasitic capacitance between the electrodes and increasing the breakdown voltage.

  For example, when the first embodiment is applied to a MONOS type memory cell structure, a semiconductor memory device as shown in FIG. 17 is obtained.

As shown in FIG. 17, the word line WL includes a tunnel oxide film 42, a charge storage layer (trap nitride film) 43, for example, a block layer 44 made of Al ₂ O ₃ , and a control gate electrode, which are sequentially stacked on a semiconductor substrate 41. 45.

  The control gate electrode 45 includes a metal layer 45a made of, for example, TiN or TaN, a polysilicon film 45b, and a nickel silicide layer 45c.

  The selection transistor ST includes a tunnel oxide film 42, a block layer 44, and a gate electrode 46 that are sequentially stacked. The gate electrode 46 includes, for example, a metal layer 46a made of TiN, a polysilicon film 46b, and a nickel silicide layer 46c.

  A sidewall film (silicon oxide film) 47 having a height higher than that of the word line WL is formed on the sidewall of the word line WL. Therefore, the side surface of the control gate electrode 45 is not exposed to the cavity 48, and the occurrence of surface leakage between the word lines WL can be prevented.

  In addition, since the cover film (silicon oxide film) 49 does not enter between the word lines WL (between the control gate electrodes 45), an electric field is uniformly applied between the control gate electrodes 45, and deterioration of breakdown voltage can be prevented.

  FIG. 18 shows a semiconductor memory device obtained when the second embodiment is applied to a MONOS type memory cell structure. Unlike the semiconductor memory device shown in FIG. 17, the control gate electrode 45 and the gate electrode 46 of the select transistor ST are constituted by barrier metals 45d and 46d made of TiN and metals 45e and 46e made of W, for example. This semiconductor memory device can obtain the same effects as those of the above embodiment.

  In the above embodiment, Ni is used for silicidation of the control gate electrode. However, in addition to Ni, a metal belonging to Group 4 to 11 of transition metals such as Ti, Co, Pt, Pd, Ta, and Mo can be used. The manufacturing method of the semiconductor memory device according to the above embodiment is a particularly useful technique when using a metal whose control gate electrode expands by silicidation like Ni.

  The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 1st Embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by a comparative example. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by a comparative example. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by a comparative example. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by a comparative example. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 2nd Embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 2nd Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 2nd Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor memory device by the 2nd Embodiment. It is a schematic block diagram of the semiconductor memory device by a modification. It is a schematic block diagram of the semiconductor memory device by a modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Tunnel oxide film 3 Floating gate electrode 4 Interpoly insulating film 5 Control gate electrodes 6 and 15 Silicon nitride film 11 Spacer oxide film 12 Sacrificial film 14 and 16 Silicon oxide film 17 Silicide layer 18 Cover film 19 Cavity ST Select transistor SW Side wall WL Word line

Claims (5)

A semiconductor substrate;
A plurality of word lines each having a first insulating film, a charge storage layer, a second insulating film, and a control gate electrode, which are formed on the semiconductor substrate at predetermined intervals and are sequentially stacked;
A third insulating film formed on a sidewall of the word line and having a height equal to or higher than the height of the word line;
A fourth insulating film formed on the word line and above the semiconductor substrate between adjacent word lines;
A cavity that is located between the adjacent word lines and whose upper part is covered with the fourth insulating film; and
A semiconductor memory device.   2. The height of the lower end of the fourth insulating film between adjacent word lines from the surface of the semiconductor substrate is higher than the height of the upper surface of the control gate electrode from the surface of the semiconductor substrate. The semiconductor memory device described in 1.   3. The semiconductor memory device according to claim 1, wherein the third insulating film is also formed on the surface of the semiconductor substrate between adjacent word lines and has a thickness of 3 nm to 15 nm. A plurality of word lines each including a first insulating film, a charge storage layer, a second insulating film, a control gate electrode, and a third insulating film, which are sequentially stacked, are formed on the semiconductor substrate at predetermined intervals. Process,
Forming an oxide film so as to cover the word line and the semiconductor substrate;
Forming a sacrificial film on the oxide film so as to fill the space between the word lines;
Removing the sacrificial film and the oxide film such that an upper surface of the third insulating film is exposed;
Removing the third insulating film and exposing an upper surface of the control gate electrode;
Removing the sacrificial layer between the word lines;
Performing silicidation of the control gate electrode;
Forming a fourth insulating film so as to cover the area above the sacrificial film removed;
A method for manufacturing a semiconductor memory device. A plurality of first insulating films, a charge storage layer, a second insulating film, a control gate electrode including a polysilicon film, and a third insulating film, which are sequentially stacked on the semiconductor substrate at predetermined intervals. Forming a word line;
Forming an oxide film so as to cover the word line and the semiconductor substrate;
Forming a sacrificial film on the oxide film so as to fill the space between the word lines;
Removing the sacrificial film and the oxide film such that an upper surface of the third insulating film is exposed;
Removing the third insulating film and exposing an upper surface of the control gate electrode;
Removing at least the upper part of the polysilicon film of the control gate electrode;
Forming a metal layer between the oxide films above the second insulating film;
Removing the sacrificial layer between the word lines;
Forming a fourth insulating film so as to cover the area above the sacrificial film removed;
A method for manufacturing a semiconductor memory device.

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