CN104241359A - Semiconductor element structure and manufacturing method thereof - Google Patents

Semiconductor element structure and manufacturing method thereof Download PDF

Info

Publication number
CN104241359A
CN104241359A CN201310249910.9A CN201310249910A CN104241359A CN 104241359 A CN104241359 A CN 104241359A CN 201310249910 A CN201310249910 A CN 201310249910A CN 104241359 A CN104241359 A CN 104241359A
Authority
CN
China
Prior art keywords
layer
groove
metal gates
transistor
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310249910.9A
Other languages
Chinese (zh)
Other versions
CN104241359B (en
Inventor
吴宜静
黄志森
洪庆文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN201310249910.9A priority Critical patent/CN104241359B/en
Publication of CN104241359A publication Critical patent/CN104241359A/en
Application granted granted Critical
Publication of CN104241359B publication Critical patent/CN104241359B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer

Abstract

The invention discloses a semiconductor element and a manufacturing method of the semiconductor element. The manufacturing method comprises the steps that a substrate is firstly provided, at least one first transistor is formed on the substrate, a first conduction type is included, and the first transistor comprises a first metal grid and a protection layer covering the side wall of the first metal grid; then, part of the first metal grid is removed to form a first groove to expose part of the protection layer, and a second groove is formed by removing the exposed part of the protection layer after the first groove is formed to form. After the second groove is formed, an contact etch stop layer is formed in the second groove.

Description

Semiconductor structure and preparation method thereof
Technical field
The present invention relates to a kind of semiconductor structure and preparation method thereof, especially relate to a kind of semiconductor element and contact plunger and preparation method thereof with metal gates.
Background technology
At integrated circuit (integrated circuit, IC), in, each different semiconductor element sets up the electrical connection between element by contact structures such as contact plunger (contact plug) and internal connection-wire structure (interconnection structure) etc.But constantly promote and the lasting reduction of characteristic size (feature size) along with integrated circuit amasss into degree, live width and the physical dimension of semiconductor element are also more and more less.Under the trend that this limit for width constantly reduces, any alignment error occurred when making contact plunger, all likely causes the skew of contact plunger, and then causes in element or interelement short circuit.When in element, such as, when coming in contact connector alignment issues between grid structure and source/drain and cause short circuit, the inefficacy of semiconductor element will be caused; And interelement short circuit more may cause whole IC to lose efficacy.
Therefore, still need a kind of semiconductor element and preparation method thereof at present, offset the problems such as the short circuit caused and component failure effectively to avoid contact plunger.
Summary of the invention
For solving the problem; the invention provides a kind of manufacture method of semiconductor element; first this manufacture method provides a substrate; this substrate is formed with at least one the first transistor; there is one first conduction type, and this first transistor includes the protective layer that one first metal gates and covers the sidewall of this first metal gates.Next, remove this first metal gates of part to form the first groove that exposes this protective layer, and forming this protective layer of removing after this first groove and exposing to form one second groove.After this second groove of formation, in this second groove, form an etching stopping layer.
The present invention another a kind of semiconductor element is provided, this semiconductor element includes a substrate, a transistor and an etching stopping layer.This transistor is arranged in this substrate, and this transistor comprises a metal gates.This etching stopping layer is arranged at the top of this metal gates, and a width of this etching stopping layer is greater than a width of this metal gates.
According to semiconductor element provided by the present invention and preparation method thereof, this etching stopping layer is formed in the top of this transistor, and the width of this etching stopping layer is greater than the width of the metal gates of this transistor, therefore follow-up carry out the manufacture crafts such as contact plunger making time, the exposure causing metal gates when etching contact hole can be avoided, contact plunger more can be avoided because of alignment issues to cause the problem such as metal gates and source/drain short circuit.
Accompanying drawing explanation
Fig. 1 ~ Fig. 2 and Fig. 5 ~ Figure 10 is the schematic diagram of a preferred embodiment of the manufacture method of semiconductor element provided by the present invention, wherein:
Fig. 6 is the schematic diagram of a change type of this preferred embodiment;
Fig. 7 is the schematic diagram of another change type of this preferred embodiment; And
Fig. 9 is the schematic diagram of another change type of this preferred embodiment.
Fig. 3 and Fig. 4 is this is the schematic diagram of another preferred embodiment of the manufacture method of semiconductor element provided by the present invention.
Figure 11 is the schematic diagram of a preferred embodiment of semiconductor element provided by the present invention.
Figure 12 ~ Figure 13 is the schematic diagram of another preferred embodiment of semiconductor element provided by the present invention.
Main element symbol description
100 substrates
102 shallow isolating trough
104 dielectric layers
106 first workfunction layers
108 second workfunction layers
109 fill metal level
110 the first transistors
112 transistor secondses
114 first metal gates
116 second metal gates
120 first lightly doped drains
122 second lightly doped drains
124 clearance walls
130 first source/drains
132 second source/drains
133 fin structures
140 contact hole etching stopping layers
142 inner layer dielectric layers
144 first dielectric layers
150 first grooves
152 the 3rd grooves
154 second grooves
156 the 4th grooves
160 etching stopping layers
162 cavities
170,172 metal levels
180 metal gate contact connectors
182 source/drain contact plungers
182a offsets source electrode/drain contact connector
184 share contact plunger
Embodiment
For making the general technology person being familiar with the technical field of the invention further can understand the present invention, hereafter spy enumerates preferred embodiment of the present invention, and coordinates appended accompanying drawing, describe in detail constitution content of the present invention and the effect for reaching.
For convenience of description, each accompanying drawing of the present invention is only signal to be easier to understand the present invention, and its detailed ratio can adjust according to the demand of design.The described in the text upper and lower relation for opposed member in figure, people in this area all will be understood that its relative position referring to object, therefore all can overturn and present identical component, this all should belong to the scope disclosed in this specification together, first chats bright in this appearance.
Refer to the schematic diagram that Fig. 1 ~ Fig. 2 and Fig. 5 ~ Figure 10, Fig. 1 ~ Fig. 2 and Fig. 5 ~ Figure 10 is a preferred embodiment of the manufacture method of semiconductor element provided by the present invention.As shown in Figure 1, first this preferred embodiment provides a substrate 100, such as a silicon base, containing silicon base or silicon-coated insulated (silicon-on-insulator, SOI) substrate.Substrate 100 is formed with the first transistor 110 and a transistor seconds 112, and be formed with the shallow isolating trough (shallow trench isolation, STI) 102 that electrical isolation is provided in substrate 100 between the first transistor 110 and transistor seconds 112.The first transistor 110 has one first conductive type, and transistor seconds 112 has one second conductive type, and the first conductive type and the second conductive type complementation (complementary).In this preferred embodiment, the first transistor 110 is a n-type transistor; And transistor seconds 112 is a p-type transistor.
Please continue to refer to Fig. 1.The first transistor 110 and transistor seconds 112 respectively comprise dielectric layer 104, nominal grid if a polysilicon layer (not shown) and is in order to define the hard mask (not shown) of nominal grid position and size.In addition the first transistor 110 and transistor seconds 112 comprise one first lightly doped drain (light doped drain, hereinafter referred to as LDD) 120 and one the 2nd LDD122, a clearance wall 124, and one first source/drain 130 and one second source/drain 132 respectively.The surface of the first source/drain 130 and the second source/drain 132 can include a metal silicide (not shown) respectively.In addition, in rear self-aligned metal silicate (post contact salicide) manufacture craft, after metal silicide also can be formed at contact hole (contact hole).And on the first transistor 110 with transistor seconds 112, be sequentially provided with a contact hole etching stopping layer (contact etch stop layer, hereinafter referred to as CESL) 140 and an internal layer dielectric (inter-layer dielectric, hereinafter referred to as ILD) layer 142, and as shown in Figure 1, ILD layer 142 is around the first transistor 110 and transistor seconds 112.The making step of said elements and Material selec-tion, or even in semiconductor industry for provide effect of stress more to improve electrical performance and implement selective epitaxial grow up (selective epitaxial growth, SEG) method formation epitaxial source/drain electrode 130,132 etc. are all known by the personage in this field, therefore all repeat no more in this.
Please still consult Fig. 1.After formation CESL140 and ILD layer 142, removed ILD layer 142 and the CESL140 of part by a planarization manufacture craft, until expose hard mask or the nominal grid of the first transistor 110 and transistor seconds 112.An etching process be applicable to is utilized to remove hard mask and the nominal grid of the first transistor 110 and transistor seconds 112 subsequently, and in the first transistor 110 with transistor seconds 112, form a first grid groove (not shown) and a second grid groove (not shown) respectively, and expose dielectric layer 104 simultaneously.It should be noted that, this preferred embodiment and first gate dielectric (high-k first) manufacture craft are integrated, therefore dielectric layer 104 can be a high-k (high dielectric constant, high-k) dielectric layer, and this high-k dielectric layer can be a metal oxide layer, a such as rare-earth oxide layer.High-k gate dielectric 104 optional autoxidation hafnium (hafnium oxide, HfO 2), hafnium silicate oxygen compound (hafnium silicon oxide, HfSiO 4), hafnium silicate nitrogen oxide (hafnium silicon oxynitride, HfSiON), aluminium oxide (aluminum oxide, Al 2o 3), lanthana (lanthanum oxide, La 2o 3), tantalum oxide (tantalum oxide, Ta 2o 5), yittrium oxide (yttrium oxide, Y 2o 3), zirconia (zirconium oxide, ZrO 2), strontium titanates (strontium titanate oxide, SrTiO 3), zirconium silicate oxygen compound (zirconium silicon oxide, ZrSiO 4), zirconic acid hafnium (hafnium zirconium oxide, HfZrO 4), strontium bismuth tantalum pentoxide (strontium bismuth tantalate, SrBi 2ta 2o 9, SBT), lead zirconate titanate (lead zirconate titanate, PbZr xti 1-xo 3, PZT) and barium strontium (barium strontium titanate, Ba xsr 1-xtiO 3, BST) group that forms.In addition, this preferred embodiment of personage Ying Zhi being familiar with this technology is not limit yet and is integrated with post tensioned unbonded prestressed concrete dielectric layer (high-k last) manufacture craft.
Please still consult Fig. 1.After formation first grid groove and second grid groove, in first grid groove and second grid groove, form one first workfunction layers 106, remove the first workfunction layers in first grid groove subsequently.In this preferred embodiment, the first workfunction layers 106 is a p-type workfunction layers, and its work function is between 4.8 ~ 5.2.Next in first grid groove and second grid groove, form one second workfunction layers 108, in this preferred embodiment, the second workfunction layers 108 is a N-shaped workfunction layers, and its work function is between 3.9 ~ 4.3.Subsequently, in first grid groove and second grid groove, form one fill metal level 109, and remove unnecessary metal level by a planarization manufacture craft, and one first metal gates 114 and the second metal gates 116 is formed respectively in the first transistor 110 with transistor seconds 112.In addition, be familiar with the personage Ying Zhi of this technology, in metal gates manufacture craft, according to electrical requirements before gate trench inserts different workfunction metals, the rete often first inserting other, if barrier layer (barrier layer), etching stopping layer (etch stop layer) are even retes such as stressor layers (strained layer), seldom give at this and repeating.
Refer to Fig. 2.In this preferred embodiment, after formation first metal gates 114 and the second metal gates 116, suitable metal etching method is utilized again to etch the first metal gates 114 and the second metal gates 116, to form one first groove 150 and one the 3rd groove 152 in the first metal gates 114 and the second metal gates 116 respectively.The degree of depth of the first groove 150 and the 3rd groove 152 can be 250 ~ 400 dusts, but is not limited thereto.Should be noted in addition; first metal gates 114 contacts with clearance wall 124 with the sidewall of the second metal gates 116, and the clearance wall 124 therefore covering the first metal gates 114 and the second metal gates 116 sidewall can be used as the protective layer of the first metal gates 114 and the second metal gates 116.Therefore as shown in Figure 2, the first groove 150 exposes protective layer (i.e. clearance wall 124), fills metal level 109 and the second workfunction layers 108; In like manner the 3rd groove 152 exposes protective layer (i.e. clearance wall 124), fills metal level 109, second workfunction layers 108 and the first workfunction layers 106.
Refer to Fig. 3 and Fig. 4 in addition, Fig. 3 and Fig. 4 is this is the schematic diagram of another preferred embodiment of the manufacture method of semiconductor element provided by the present invention.First should be noted that element identical with aforementioned preferred embodiment in this preferred embodiment is by identical symbol description, and comprise identical material and conduction type, therefore the plurality of details all repeats no more.This preferred embodiment and aforementioned preferred embodiment difference are: as previously mentioned when making metal gates, except workfunction metal, other metallic diaphragm more may be inserted in gate trench, and the formation of each rete, capital causes the A/F of gate trench to reduce, and causes subsequent film such as workfunction metal not easily to insert the problem of gate trench.Therefore, this preferred embodiment, more after formation first workfunction layers 106 and the second workfunction layers 108, removes part first workfunction layers 106 and second workfunction layers 108 of gate trench opening respectively.Therefore, follow-up rete such as the second workfunction layers and filling metal level etc. inserted in gate trench can successfully be inserted in gate trench, avoids the formation in space, and space can be avoided the negative effect of semiconductor element electric.Therefore in this preferred embodiment, the first workfunction layers 106 in the first metal gates 114 and the second metal gates 116 and the second workfunction layers 108 is rough has a U-shape.
Refer to Fig. 4.After formation first metal gates 114 and the second metal gates 116, suitable metal etching method is more utilized again to etch the first metal gates 114 and the second metal gates 116, to form one first groove 150 and one the 3rd groove 152 in the first metal gates 114 and the second metal gates 116 respectively.Because in this preferred embodiment, the first workfunction layers 106 and the second workfunction layers 108 have the specific profile of U-shape, therefore as shown in Figure 4, the first groove 150 only exposes protective layer (i.e. clearance wall 124) and fills metal level 109; In like manner the 3rd groove 152 only exposes protective layer (i.e. clearance wall 124) and fills metal level 109.In other words, fill metal level 109 and be exposed in the first groove 150 and the 3rd groove 152, and cover the first workfunction layers 106 and the second workfunction layers 108 completely.
Refer to Fig. 5.First please note that the later described step of Fig. 5 can be connected in aforementioned two embodiments and carry out, therefore Fig. 5 hookup 2 and Fig. 4 can consult simultaneously.As shown in Figure 5; after formation first groove 150 and the 3rd groove 152; this preferred embodiment more utilizes other etching process being different from metal etching method; the protective layer (i.e. clearance wall 124) being exposed to the first groove 150 and the second groove 152 sidewall removes by such as dry ecthing or wet etching completely; to widen the A/F of the first groove 150 and the 3rd groove 152, and form one second groove 154 and one the 4th groove 156 respectively.In this preferred embodiment, dry ecthing can utilize following gas or its combination to etch: octafluorocyclobutane (octafluorobutylene, C 4f 8), hexachlorobutadiene (hexafluorobutadiene, C 4f 6), fluoroform (methyl fluoride, CH 3f), difluoromethane (difluoromethane, CH 2f 2), boron chloride (tricholorborane, BCl 3), argon gas (Argon, Ar), oxygen and nitrogen.In this preferred embodiment, wet etching can utilize following etchant to etch: phosphoric acid (phosphoric acid, H 3pO 4), dilute hydrofluoric acid (diluted hydrofluoride, DHF) etc.
Refer to Fig. 6, Fig. 6 is the schematic diagram of a change type of this preferred embodiment.According to this change type, argon plasma also can be utilized to bombard or utilize SiCoNi tMengraving method, removes the partial protection layer (i.e. clearance wall 124) being exposed to the first groove 150 and the second groove 152 sidewall, to widen the A/F of the first groove 150 and the 3rd groove 152, and forms one second groove 154 and one the 4th groove 156 respectively.
Refer to Fig. 7 in addition, Fig. 7 is the schematic diagram of a change type of this preferred embodiment.Because clearance wall 124 and CESL140 are all arranged at the sidewall of the first metal gates 114 and the second metal gates 116, therefore clearance wall 124 and CESL140 can together be considered as a protective layer.Therefore in this change type, after removing the clearance wall being exposed to the first groove 150 and the 3rd groove 152 sidewall, more can continue etch exposed CESL142 out, make the second groove 154 of final acquisition and the 4th groove 156 have wider larger opening.And as shown in Figure 7, ILD layer 142 is exposed to the sidewall of the second groove 154 and the 4th groove 156.
Briefly, this preferred embodiment and change type thereof utilize be different from metal etching method dry/wet/plasma bombardment/SiCoNi tMetc. method under the prerequisite not affecting depth of groove, widen the opening of the first groove 150 and the 3rd groove 152 to form the second groove 154 and the 4th groove 156, therefore an A/F of the second groove 154 is greater than an A/F of the first groove 150, in like manner an A/F of the 4th groove 156 is greater than an A/F of the 3rd groove 152, and the degree of depth of the second groove 154 and the 4th groove 156 is same as the degree of depth of the first groove 150 and the 3rd groove 152, i.e. 250 ~ 400 dusts.
Refer to Fig. 8.After formation second groove 154 and the 4th groove 156, chemical gaseous phase depositing process (chemical vapor deposition can be utilized, CVD) in substrate 100, an etching stopping layer 160 is formed, to fill up the second groove 154 and the 4th groove 156.Etching stopping layer 160 can comprise silicon nitride (SiN) or carbonitride of silicium (SiCN), but is not limited thereto.
Refer to Fig. 9 in addition, Fig. 9 is the schematic diagram of another change type of this preferred embodiment.According to this change type, a liquidation CVD (Chemical Vapor Deposition) method (flowable chemical vapor deposition, FCVD) is utilized to form etching stopping layer 160.Etching stopping layer 160 can comprise silicon nitride (SiN) or carbonitride of silicium (SiCN), but is not limited thereto.It should be noted that when utilizing FCVD to form etching stopping layer 160, cavity (void) 162 may be formed in etching stopping layer 160, and cavity 162 as shown in Figure 9, is formed at the below of plane of the opening (showing it with dotted line).
Refer to Figure 10.After formation etching stopping layer 160, optionally carry out a planarization manufacture craft and remove unnecessary etching stopping layer 160, and obtain the coplanar flat surfaces in etching stopping layer 160 top and ILD layer 142 top.As shown in Figure 10; because etching stopping layer 160 fills up the second groove 154 and the 4th groove 156; therefore the bottom contact protection layer of etching stopping layer 160 knows top; the i.e. top of clearance wall 124 or the top of clearance wall 124 and CESL140, and a thickness of etching stopping layer 160 is between 250 dust-400 dusts.
According to the manufacture method of the semiconductor element that this preferred embodiment and change type thereof provide, groove 150/152 is formed in metal gates top 114/116, widen the plurality of groove 150/152 subsequently, and insert etching stopping layer 160, the width being therefore arranged at the etching stopping layer 160 at metal gates 114/116 top is greater than a width of metal gates 114/116.And the comparatively large and etching stopping layer 160 that is covering metal grid 114/116 completely of this width can follow-up carry out contact plunger manufacture craft time; effectively protect metal gates 114/116, because offset problem causes the short circuit problem of the exposure of metal gates 114/116 and follow-up initiation when avoiding etching contact hole.
Next Figure 11 is referred to.Figure 11 is the schematic diagram of another preferred embodiment of semiconductor element provided by the present invention.First it is noted that in this preferred embodiment, identical symbol description continued to use by the element identical with aforementioned preferred embodiment, and has identical Material selec-tion, therefore something in common repeats no more.Should be noted in addition, be described for the first transistor 110 in previous embodiment and composed component thereof in this preferred embodiment, but the semiconductor element that this preferred embodiment of personage Ying Zhi being familiar with this technology provides also can comprise the transistor seconds 112 electrically complementary with the first transistor 110.In addition the composed component of the first transistor 110 and the production order of etching stopping layer 160 can consult above-described embodiment and change type, also repeat no more at this.As shown in figure 11, this preferred embodiment comprises a substrate 100, substrate 100 is formed with at least one metal gates 114 and at least one source/drain (not shown).Should be noted in addition, due to the present invention can with fin field-effect transistor (fin field effect transistor, FinFET) Technology Integration, therefore in this preferred embodiment, source/drain can be formed in the fin structure 133 of metal gates 114 both sides.Certainly, source/drain also can as above-described embodiment sayed, be formed in the substrate 100 of metal gates 114 both sides.
Please continue to refer to Figure 11.As previously mentioned, after formation etching stopping layer 160, optionally carry out a planarization manufacture craft and remove unnecessary etching stopping layer 160 to form a flat surfaces, on this flat surfaces, form the first dielectric layer 144 subsequently.But personage Ying Zhi first dielectric layer 144 being familiar with this technology also directly can be formed on etching stopping layer 160 after formation etching stopping layer 160.Next, a hard mask layer (not shown) and a photoresist oxidant layer (not shown) can be formed on the first dielectric layer 144.Hard mask layer can be an individual layer or composite film, and for example, hard mask layer from bottom to top sequentially can comprise titanium nitride (titanium nitride, TiN) layer and monoxide layer, but is not limited thereto.Photoresist oxidant layer can be an individual layer or a composite film, for example photoresist oxidant layer from bottom to top sequentially can comprise an organic dielectric layer (organic dielectric layer, ODL), one containing silicon mask anti-reflecting layer (silicon-containing hard mask bottom anti-reflecting coating, SHB) with a photo anti-corrosion agent material (photoresist, but be not limited thereto PR).
Next, patterning photoresist oxidant layer, in order to define position and the size of multiple source/drain contact plunger.Afterwards by photoresist design transfer to hard mask layer, more pass through applicable etching process subsequently and utilize hard mask layer to etch the first dielectric layer 144 and ILD layer 142 as an etching mask, even CESL142, and form multiple source/drain contact hole (not shown) exposing source/drain (fin structure 133 namely in this preferred embodiment), remove photoresist oxidant layer subsequently.It should be noted that when forming source/drain contact hole, the situation offset may occur because of reasons such as misregistrations, thus may be formed in the first dielectric layer 144 with ILD layer 142 and offset source electrode/drain contact hole.The more important thing is, owing to there is etching stopping layer 160 above metal gates 114, even if therefore formed skew source electrode/drain contact hole, also can not expose metal gates, therefore effectively can maintain the integrality of metal gates.Next, then form a photoresist oxidant layer (not shown), its structure can be identical with aforesaid photoresist oxidant layer with material, but be not limited thereto.Patterning photoresist oxidant layer subsequently, in order to define position and the size of multiple metal gate contact connector.It should be noted that in this preferred embodiment, metal gate contact connector in order to be electrically connected the first layer metal structure of metal gates 114 and multiple layer metal internal connection-wire structure, therefore can be considered level 0 metal structure (M0).
Please continue to refer to Figure 11.Carry out an etching step subsequently, by metal gate contact connector design transfer in each Rotating fields under photoresist oxidant layer, and at least one metal gates 114, form a metal gate contact hole (not shown).Remove photoresist oxidant layer subsequently, and contact in hole with source/drain in metal gate contact hole and form barrier layer (not shown) and metal level 170.Barrier layer can comprise the more barrier layers etc. such as titanium nitride, tantalum nitride (tantalum nitride, TaN) or titanium/titanium nitride (Ti/TiN), to promote the adhesive force between the inwall in contact hole and the metal level 170 of follow-up formation; Metal level 170 can comprise and has the better metal material filling out hole ability, such as tungsten (tungsten, W), but is all not limited thereto.Therefore this preferred embodiment inserts manufacture craft by the twice point of etching process opened and metal once complete metal gate contact connector 180, source/drain contact plunger 182 and shared contact plunger 184 in the first dielectric layer 144 with ILD layer 142 simultaneously.As shown in figure 11, because metal gate contact connector 180, source/drain contact plunger 182 and shared contact plunger 184 are all complete after inserting metal level 170 simultaneously, therefore metal gate contact connector 180, source/drain contact plunger 182 and shared contact plunger 184 are all integrally formed structure.
Please still consult Figure 11.As previously mentioned, when making source/drain contact hole, the contact plunger of follow-up formation is likely caused to offset because of alignment issues.But owing to having the etching stopping layer 160 that a width is greater than metal gates 114 above the metal gates 114 that this preferred embodiment provides, therefore can avoid directly exposing metal gates 114 during etching source/drain contact hole, further avoid the biased contact connector 182a of follow-up formation and metal gates 114 to form short circuit.
Refer to Figure 12 and Figure 13 in addition, Figure 12 and Figure 13 is the schematic diagram of the another preferred embodiment of semiconductor element provided by the present invention.First it is noted that in this preferred embodiment, identical symbol description also continued to use by the element identical with aforementioned preferred embodiment, and has identical Material selec-tion, therefore something in common repeats no more.This preferred embodiment and aforementioned preferred embodiment difference are, as shown in figure 12, this case is after formation ILD layer 142, namely in ILD layer 142, etch source/drain contact hole, and after formation source/drain contact hole, namely in source/drain contact hole, sequentially form barrier layer and metal level 170 immediately, and remove unnecessary metal level by a planarization manufacture craft.
Refer to Figure 13.Next, the first dielectric layer 144 is formed on ILD layer 142, photoresist oxidant layer (not shown), afterwards a patterning photoresist oxidant layer is formed again subsequently, in order to define position and the size of multiple source/drain contact plunger and metal gate contact connector on the first dielectric layer 144.As previously mentioned, in this preferred embodiment, metal gate contact connector can be electrically connected the first layer metal structure of metal gates 114 and multiple layer metal internal connection-wire structure, therefore can be considered level 0 metal structure (M0).Carry out an etching step subsequently, by source/drain contact plunger and metal gate contact connector design transfer in each Rotating fields under photoresist oxidant layer, and on metal level 170 and at least one metal gates 114, form source/drain electrode contact hole and metal gate contact hole (not shown) respectively.Remove photoresist oxidant layer subsequently, and contact in hole with source/drain in metal gate contact hole and form barrier layer (not shown) and metal level 172, remove excess metal by a planarization manufacture craft more subsequently, and complete source/drain contact plunger 182, metal gate contact connector 180 and shared contact plunger 184 in the first dielectric layer 144 with ILD layer 142.As shown in figure 13, insert manufacture craft from source/drain contact plunger 182 by different etching process and different metals due to metal gate contact connector 180 and shared contact plunger 184 to complete, therefore part contact connector, especially source/drain contact plunger 182 is with in shared contact plunger 184, comprise metal level 170 and metal level 172, and there is an interface (interface).
Please still consult Figure 13.As previously mentioned, when making source/drain contact hole, the contact plunger of follow-up formation is likely caused to offset because of alignment issues.But owing to having the etching stopping layer 160 that a width is greater than metal gates 114 above the metal gates 114 that this preferred embodiment provides, therefore can avoid directly exposing metal gates 114 during etching source/drain contact hole, further avoid the biased contact connector 182a of follow-up formation and metal gates 114 to form short circuit.
In sum, according to semiconductor element provided by the present invention and preparation method thereof, etching stopping layer is formed in the top of transistor, and the width of etching stopping layer is greater than the width of the metal gates of transistor, therefore follow-up carry out the manufacture crafts such as contact plunger making time, the exposure causing metal gates when etching contact hole can be avoided, contact plunger more can be avoided because of alignment issues to cause the problem such as metal gates and source/drain short circuit.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.

Claims (20)

1. a manufacture method for semiconductor element, includes:
One substrate is provided, this substrate is formed with at least one the first transistor, there is the first conduction type, and this first transistor includes the protective layer of the sidewall of the first metal gates and this first metal gates of covering;
Remove this first metal gates of part to form one first groove, and this this protective layer of the first groove expose portion;
Remove this protective layer of part of exposure to form one second groove; And
An etching stopping layer is formed in this second groove.
2. manufacture method as claimed in claim 1, wherein this first metal gates comprises the first workfunction layers and fills metal level.
3. manufacture method as claimed in claim 2; wherein this substrate also comprises transistor seconds; this transistor seconds has the second conduction type; and this second conduction type and the complementation of this first conduction type, this transistor seconds comprises this protective layer of the sidewall of the second metal gates and this second metal gates of covering.
4. manufacture method as claimed in claim 3, also comprises:
While forming this first groove, remove this second metal gates of part in removing this first metal gates of part, to form one the 3rd groove, and the 3rd groove goes out this protective layer of part cruelly; And
This protective layer of part of exposure is removed, to form one the 4th groove while forming this second groove.
5. manufacture method as claimed in claim 2, wherein this first workfunction layers is exposed in this first groove.
6. manufacture method as claimed in claim 2, wherein this filling metal level is exposed in this first groove, and this filling metal level covers this first workfunction layers completely.
7. manufacture method as claimed in claim 1, wherein this protective layer comprises at least one clearance wall.
8. manufacture method as claimed in claim 7, wherein this protective layer also comprises contact hole etching stopping layer (contact etch stop layer, CESL).
9. manufacture method as claimed in claim 1, wherein this protective layer removes wholly or in part.
10. manufacture method as claimed in claim 1, wherein this substrate also comprises internal layer dielectric (interlayer dielectric) layer, this inner layer dielectric layer is around this first transistor, and this inner layer dielectric layer is exposed to the sidewall of this second groove.
11. manufacture methods as claimed in claim 1, wherein an A/F of this second groove is greater than an A/F of this first groove.
12. manufacture methods as claimed in claim 1, wherein the degree of depth of this second groove is between 250 dusts (angstrom) ~ 400 dust.
13. 1 kinds of semiconductor elements, include:
Substrate;
Transistor, is arranged in this substrate and this transistor comprises a metal gates; And
Etching stopping layer, is arranged at the top of this metal gates, and a width of this etching stopping layer is greater than a width of this metal gates.
14. semiconductor elements as claimed in claim 13, also comprise protective layer, are arranged at the sidewall of metal gates.
15. semiconductor elements as claimed in claim 14, wherein this protective layer comprises at least one clearance wall.
16. semiconductor elements as claimed in claim 15, wherein this protective layer also comprises contact hole etching stopping layer.
17. semiconductor elements as claimed in claim 14, wherein the bottom of this etching stopping layer contacts the top of this protective layer.
18. semiconductor elements as claimed in claim 13, wherein a thickness of this etching stopping layer is between 250 dust-400 dusts.
19. semiconductor elements as claimed in claim 13, also comprise inner layer dielectric layer, and this inner layer dielectric layer is around this transistor, and the top copline (coplanar) of the top of this etching stopping layer and this inner layer dielectric layer.
20. semiconductor elements as claimed in claim 19, also comprise at least one contact plunger, are arranged within this inner layer dielectric layer.
CN201310249910.9A 2013-06-21 2013-06-21 Semiconductor structure and preparation method thereof Active CN104241359B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310249910.9A CN104241359B (en) 2013-06-21 2013-06-21 Semiconductor structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310249910.9A CN104241359B (en) 2013-06-21 2013-06-21 Semiconductor structure and preparation method thereof

Publications (2)

Publication Number Publication Date
CN104241359A true CN104241359A (en) 2014-12-24
CN104241359B CN104241359B (en) 2018-07-10

Family

ID=52229119

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310249910.9A Active CN104241359B (en) 2013-06-21 2013-06-21 Semiconductor structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN104241359B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039335A (en) * 2016-02-03 2017-08-11 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN108063120A (en) * 2016-11-07 2018-05-22 格芯公司 It is protected using the self-aligned contacts portion for strengthening grid cover and spacer portions
CN108346661A (en) * 2017-01-24 2018-07-31 三星电子株式会社 Semiconductor devices
CN109390226A (en) * 2017-08-09 2019-02-26 格芯公司 Field effect transistor and method with an air gap gate lateral wall spacer
WO2020073239A1 (en) * 2018-10-10 2020-04-16 华为技术有限公司 Field-effect transistor structure having low gate resistance, and preparation method
CN112490181A (en) * 2019-09-12 2021-03-12 夏泰鑫半导体(青岛)有限公司 Method for manufacturing semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102237271A (en) * 2010-04-30 2011-11-09 格罗方德半导体公司 Method of forming semiconductor device comprising dielectric cap layer
US20110281426A1 (en) * 2010-05-14 2011-11-17 Samsung Electronics Co., Ltd. Semiconductor device and method of forming the same
CN102347361A (en) * 2010-08-03 2012-02-08 台湾积体电路制造股份有限公司 Field effect transistor and manufacture method thereof
US8426300B2 (en) * 2010-12-02 2013-04-23 International Business Machines Corporation Self-aligned contact for replacement gate devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102237271A (en) * 2010-04-30 2011-11-09 格罗方德半导体公司 Method of forming semiconductor device comprising dielectric cap layer
US20110281426A1 (en) * 2010-05-14 2011-11-17 Samsung Electronics Co., Ltd. Semiconductor device and method of forming the same
CN102347361A (en) * 2010-08-03 2012-02-08 台湾积体电路制造股份有限公司 Field effect transistor and manufacture method thereof
US8426300B2 (en) * 2010-12-02 2013-04-23 International Business Machines Corporation Self-aligned contact for replacement gate devices

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039335A (en) * 2016-02-03 2017-08-11 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN107039335B (en) * 2016-02-03 2019-09-27 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN108063120A (en) * 2016-11-07 2018-05-22 格芯公司 It is protected using the self-aligned contacts portion for strengthening grid cover and spacer portions
CN108346661A (en) * 2017-01-24 2018-07-31 三星电子株式会社 Semiconductor devices
CN108346661B (en) * 2017-01-24 2024-04-09 三星电子株式会社 Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
CN109390226A (en) * 2017-08-09 2019-02-26 格芯公司 Field effect transistor and method with an air gap gate lateral wall spacer
CN109390226B (en) * 2017-08-09 2023-09-15 格芯(美国)集成电路科技有限公司 Field effect transistor with air gap grid side wall spacer and method
WO2020073239A1 (en) * 2018-10-10 2020-04-16 华为技术有限公司 Field-effect transistor structure having low gate resistance, and preparation method
CN112640128A (en) * 2018-10-10 2021-04-09 华为技术有限公司 Structure and manufacturing method of field effect transistor with low grid resistance
CN112640128B (en) * 2018-10-10 2022-10-04 华为技术有限公司 Structure and manufacturing method of field effect transistor with low grid resistance
CN112490181A (en) * 2019-09-12 2021-03-12 夏泰鑫半导体(青岛)有限公司 Method for manufacturing semiconductor device
CN112490181B (en) * 2019-09-12 2023-03-24 夏泰鑫半导体(青岛)有限公司 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
CN104241359B (en) 2018-07-10

Similar Documents

Publication Publication Date Title
TWI668744B (en) Semiconductor devices and methods for forming the same
CN104835838B (en) Gate structure and its manufacturing method with different in width
US9064814B2 (en) Semiconductor structure having metal gate and manufacturing method thereof
US9006091B2 (en) Method of forming semiconductor device having metal gate
TWI701727B (en) Semiconductor device and manufacturing method thereof
US10068797B2 (en) Semiconductor process for forming plug
CN103378153A (en) Structure and method for finfet integrated with capacitor
US9870951B2 (en) Method of fabricating semiconductor structure with self-aligned spacers
KR20120036185A (en) Semiconductor device and method for manufacturing the same
KR101994820B1 (en) Semiconductor with stacked silicon containing layer and metal containing layer and method for fabricating the same
CN104241359B (en) Semiconductor structure and preparation method thereof
US11289478B2 (en) Semiconductor device including fin field effect transistor
TWI408809B (en) Semiconductor device
KR20120057818A (en) Method of manufacturing semiconductor devices
US9147746B2 (en) MOS transistors and fabrication method thereof
TW201611282A (en) Semiconductor structure and process thereof
TW201820483A (en) FinFET devices and methods of forming
US20150255564A1 (en) Method for manufacturing a semiconductor device
TW201911385A (en) Semiconductor device and method for fabricating the same
JP2008103613A (en) Semiconductor device and manufacturing method thereof
US20220231023A1 (en) Finfet device and method
CN108807521A (en) Semiconductor devices and its manufacturing method
TWI827115B (en) Semiconductor device and method of forming the same
TWI579928B (en) Method for forming interdielectric layer
TW202401573A (en) Semiconductor device and method for fabricating the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant