JP2007059660A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method for improving wiring reliability and for preventing a wiring from being highly-resistive, and to provide a semiconductor device. <P>SOLUTION: An interlayer insulating film 21 having an oxygen-containing insulating layer 21a on the lower layer side is formed on a substrate 11. Next, a wiring groove 22 is formed to the upper layer side of the interlayer insulating film 21. A connection hole 23 is formed to the oxygen-containing insulating layer 21a. Then, a first barrier film 24 is formed on the interlayer insulating film 21 in a state of covering the inner wall of the wiring groove 22 so as to expose the side wall of the connection hole 23. Next, a CuMn alloy film 25 is formed in a state of covering the inner walls of the wiring groove 22 and connection hole 23. Subsequently, a conductive layer 26 including copper is formed on the CuMn alloy film 25 in a state of filling the wiring groove 22 and connection hole 23. After that, Mn in the CuMn alloy film 25 is diffused by executing heat treatment and made to react with oxygen in the oxygen-containing insulating layer 21a. Consequently, a second barrier film 27 composed of a metal-containing oxide is formed to the side wall of the connection hole 23. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for forming a multilayer wiring structure having copper (Cu) wiring and a semiconductor device obtained thereby.

  In recent years, in a semiconductor integrated circuit of silicon (Si), a Cu wiring structure using a copper (Cu) wiring and a low dielectric constant insulating film has been developed for high speed and high integration. In order to form this Cu wiring structure, since dry etching of Cu is generally not easy, so-called trench wiring methods such as a single damascene method and a dual damascene method are considered promising. In particular, in the dual damascene method, after forming a wiring groove and a connection hole communicating with the bottom of the wiring groove in an insulating film provided on the substrate, the wiring groove and the connection hole are embedded with a Cu layer in the same process. . Accordingly, since the wiring and the via are formed in the same process, the manufacturing process can be simplified, and thus attention has been paid.

  However, when realizing the Cu wiring structure, Cu in the wiring is likely to diffuse into the surrounding insulating layer during various heat treatments performed in the manufacturing process of the integrated circuit. In particular, when a wiring structure is manufactured by the trench wiring method such as the dual damascene method described above, the Cu layer is embedded after forming the wiring groove or the connection hole in the insulating film. It becomes more prominent.

  For this reason, prior to the formation of the Cu layer, a barrier film for preventing the diffusion of Cu such as tantalum (Ta) or tantalum nitride (TaN) is formed in a state of covering the wiring groove contacting the Cu layer and the inner wall of the connection hole. Has been. The barrier film is usually formed by a sputtering method so as to cover the wiring grooves and the inner walls of the connection holes.

  In order to ensure the reliability of the Cu wiring structure described above, the current process technology requires a barrier film having a thickness of about 5 nm. In order to reduce the wiring resistance accompanying the reduction in the wiring width in the future, In addition, it is required to reduce the thickness of the barrier film for each generation.

  On the other hand, a barrierless process has been proposed in which the barrier film forming step is omitted. As a barrierless process, a recess is formed in an insulating film containing oxygen, and an alloy element made of, for example, manganese (Mn) is added to the Cu layer embedded in the recess. Next, this alloy element is diffused to the interface with the insulating film by heat treatment and reacted with the insulating layer containing oxygen to form a highly stable self-diffusion barrier layer made of a metal oxide (for example, non- Patent Document 1).

Proceedings of the 65th JSAP Academic Lecture Meeting, 2004, p. 711,2p-M-19

  However, in the Cu wiring structure by the dual damascene method described above, it is difficult to deposit the barrier film uniformly and uniformly on the inner walls of the wiring grooves and connection holes by the conventional barrier film forming method by sputtering. In particular, it is difficult for the film forming component to reach the side wall of the connection hole communicating with the bottom of the wiring groove, and it is difficult to form a barrier film. For this reason, not only Cu diffuses from the via formed in the connection hole into the insulating film, but also the adhesion between the insulating film and the via is poor, so that the electromigration resistance cannot be secured. The problem has become apparent. In particular, when the insulating film in which the connection hole is formed contains oxygen, Cu is oxidized by oxygen in the insulating layer due to contact with the via, and the wiring resistance is increased.

  An object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device that improve wiring reliability and prevent an increase in resistance of the wiring.

  In order to achieve the above-described object, a semiconductor device manufacturing method according to the present invention includes a semiconductor device manufacturing method in which a conductive layer containing copper is embedded in a recess provided in an insulating film on a substrate. The process is performed sequentially. First, in the first step, a recess reaching the substrate is formed in an insulating film having an oxygen-containing insulating layer provided on the substrate. Next, in the second step, a first barrier film for preventing copper diffusion from the conductive layer is formed on the insulating film so as to cover the inner wall of the recess so as to partially expose the oxygen-containing insulating layer. To do. Next, in the third step, an alloy film of copper and a metal other than copper is formed in a state of covering the inner wall of the recess provided with the first barrier film. Subsequently, in the fourth step, a conductive layer containing copper is formed on the alloy film in a state in which the recess is embedded, and heat treatment is performed, and an oxygen-containing insulating material in which the metal other than copper in the alloy film is exposed on the inner wall of the recess A second barrier film made of a metal oxide that prevents diffusion of copper from the conductive layer is formed while reacting with oxygen in the layer to cover the inner wall of the recess exposed from the first barrier film.

  According to such a method for manufacturing a semiconductor device, the first heat treatment is performed by diffusing a metal other than copper in the alloy film and reacting with oxygen in the oxygen-containing insulating layer exposed on the inner wall of the recess. A second barrier film made of a metal oxide is formed so as to cover the inner wall of the recess exposed from the barrier film. As a result, the second barrier film is formed in a state of complementing the unformed region of the first barrier film, so that the first barrier film or the second barrier film is surely provided between the insulating film and the conductive layer. Intervene in. Therefore, diffusion of Cu from the conductive layer containing Cu embedded in the recess is prevented.

  In addition, the semiconductor device of the present invention includes an insulating film having an oxygen-containing insulating layer provided over a substrate, a conductive layer including copper filling a recess reaching the substrate provided in the insulating film, an insulating film, and a conductive layer. And a first barrier film that prevents diffusion of copper from the conductive layer, and an unformed region of the first barrier film is supplemented between the oxygen-containing insulating layer and the conductive layer. And a second barrier film made of a metal-containing oxide that prevents diffusion of copper from the conductive layer.

  According to such a semiconductor device, the second barrier film is provided between the oxygen-containing insulating layer and the conductive layer containing Cu embedded in the recess so as to complement the unformed region of the first barrier film. Therefore, the first barrier film or the second barrier film is surely interposed between the insulating film and the conductive layer. Therefore, diffusion of Cu from the conductive layer containing Cu embedded in the recess is prevented.

  As described above, according to the method of manufacturing a semiconductor device and the semiconductor device of the present invention, since the diffusion of Cu from the conductive layer embedded in the recess is prevented, the recess is a wiring groove or a connection hole. In some cases, the electromigration of the semiconductor device formed by this method can be ensured and the wiring reliability can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each embodiment, the configuration of a semiconductor device will be described in the order of manufacturing steps.

(First embodiment)
An example of an embodiment relating to a method for manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process sectional views of FIGS. Here, an example of manufacturing a multilayer wiring structure of Cu by, for example, a dual damascene method will be described.

As shown in FIG. 1A, on a substrate 11 on which a semiconductor element such as a transistor is formed, an interlayer insulation made of, for example, methyl silsesquioxane (MSQ) is interposed via a base insulating film 12 made of silicon oxide. A film 13a and an interlayer insulating film 13b made of, for example, silicon oxide (SiO ₂ ) are sequentially stacked. It is assumed that a wiring groove 14 is provided in the interlayer insulating films 13 a and 13 b, and a lower layer wiring 16 made of copper is provided in the wiring groove 14 through a barrier film 15. In addition, a protective insulating film 17 made of, for example, SiOCN is provided in a thickness of 10 nm to 35 nm so as to cover the interlayer insulating film 13b including the lower wiring 16. The configuration so far corresponds to the substrate of the claims.

Subsequently, an interlayer insulating film 21 is formed on the protective insulating film 17. Here, an insulating layer (oxygen-containing insulating layer) 21a containing oxygen is formed with a film thickness of 70 nm to 120 nm as a wiring interlayer insulating film on the lowermost layer side of the interlayer insulating film 21. As the oxygen-containing insulating layer 21a, for example, an inorganic material film having a lower dielectric constant than that of SiO ₂ such as MSQ, hydrosilsesquioxane (HSQ), porous MSQ, porous HSQ, or the like made porous is used. To do. As will be described later, connection holes are formed in the oxygen-containing insulating layer 21a.

Next, on the oxygen-containing insulating layer 21a, an insulating layer (oxygen-free insulating layer) 21b that does not contain oxygen is formed to a thickness of 60 nm to 120 nm as an inter-wiring insulating film. As the non-oxygen-containing insulating layer 21b, for example, an organic polymer such as polytetrafluoroethylene and an organic material film such as a porous film, or an SiO _{2 made} of an α-carbon film and an inorganic material film such as a porous film is used. A low dielectric constant film having a low rate is used. A wiring trench is formed in the oxygen-free insulating layer 21b in a later step.

Next, a protective insulating layer 21c made of, for example, SiO ₂ is formed with a film thickness of 100 nm to 140 nm on the oxygen-free insulating layer 21b. This protective insulating layer 21c is connected to an interlayer insulating film 21 in which an oxygen-containing insulating layer 21a, an oxygen-free insulating layer 21b, and a protective insulating layer 21c are sequentially stacked in a later process so as to communicate with the wiring groove and the bottom of the wiring groove. When holes are formed, these are filled with a conductive layer, and then polished by the CMP method, they are formed as a protective film for the oxygen-free insulating layer 21b having low CMP resistance. Therefore, a wiring groove is also formed in the protective insulating layer 21c. As described above, the interlayer insulating film 21 having a hybrid structure is formed.

  Next, by performing multistage dry etching, the wiring groove 22 is formed in the protective insulating layer 21c and the oxygen-free insulating layer 21b, and the oxygen-containing insulating layer 21a and the protective insulating film 17 communicate with the bottom of the wiring groove 22 Then, the connection hole 23 reaching the lower layer wiring 16 is formed.

  Next, as shown in FIG. 1B, a first barrier film 24 is formed by a physical vapor deposition (PVD) method such as a long-distance sputtering method. At this time, since it is formed by the sputtering method, it is difficult for the film forming component to reach the side wall of the connection hole 23 communicating with the bottom of the wiring groove 22, and the inner wall of the wiring groove 22 is formed so as to expose the side wall of the connection hole 23. In a state of covering, the first barrier film 24 is formed on the protective insulating layer 21c. At this time, the first barrier film 24 is also formed at the bottom of the connection hole 23.

  Here, since the second barrier film formed in a later step is formed by reacting with oxygen in the interlayer insulating film 21, the first barrier film 24 exposes the oxygen-free insulating layer 21b. The inner wall of the wiring groove 22 is sufficiently covered with a thickness of, for example, about 5 nm. At this time, the first barrier film 24 is formed so that the lower layer side of the side wall of the wiring trench 22 is sufficiently covered.

  Here, the first barrier film 24 is formed by a normal long-distance sputtering method. However, the film-forming component is formed from a shallow angle in a state inclined with respect to the normal direction of the substrate 11 by the sputtering method. The first barrier film 24 is preferably formed only on the inner wall of the wiring groove 22. In this case, the side wall of the connection hole 23 can be reliably exposed, and the first barrier film 24 is hardly formed on the bottom of the connection hole 23.

  Here, as will be described later, since Cu wiring is formed in the wiring groove 22, the first barrier film 24 is made of a material that prevents diffusion of Cu and has excellent adhesion to Cu. Used. As such a material, titanium (Ti), titanium nitride (TiN), titanium nitride silicide (TiSiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), or the like can be applied. . Further, the first barrier film 24 may be formed of a laminated film in which two or more of these films are combined.

  Here, the first barrier film 24 is formed by a long distance sputtering method, but may be formed by other PVD methods such as an ionization sputtering method, a long distance ionization sputtering method, and a high pressure ionization sputtering method. .

  Subsequently, as shown in FIG. 1C, an alloy film of Cu and manganese (Mn) (covering the inner wall of the wiring groove 22 provided with the first barrier film 24 and the connection hole 23 ( CuMn alloy film) 25 is formed. Here, as a metal material for forming an alloy film with Cu, a metal material having a diffusion rate in Cu higher than that of Cu, an oxide having an effect of preventing diffusion of Cu, and high adhesion to Cu is used. And Thereby, in a later step, Mn is diffused before Cu is diffused into the oxygen-containing insulating layer 21a exposed on the side wall of the connection hole 23 by heat treatment after the Cu layer is embedded in the wiring groove 22 and the connection hole 23. Diffused. Then, when Mn reacts with oxygen in the oxygen-containing insulating layer 21a, a second barrier film made of an Mn-containing oxide is formed.

  Here, although Mn is used as a metal material other than Cu constituting the alloy film, the diffusion rate in Cu is faster than that of Cu, and the oxide has an effect of preventing diffusion of Cu and adheres to Cu. The metal material is not limited to this as long as it is a highly metallic material. Examples of such metal materials include niobium (Nb), zirconium (Zr), chromium (Cr), vanadium (V), yttrium (Y), technetium (Tc), rhenium (Re) and the like in addition to Mn. Can be mentioned.

  Since this CuMn alloy film 25 also functions as a seed layer for electroplating, which will be described later, the film thickness is adjusted to a thickness of 5 nm to 80 nm suitable for achieving embedded wiring according to the wiring dimensions. Here, the CuMn alloy film 25 having a thickness of 60 nm is formed. At this time, the CuMn alloy film 25 is formed so as to cover the side wall of the connection hole 23. However, in the subsequent step, Mn in the CuMn alloy film 25 is diffused by heat treatment and reacted with oxygen in the oxygen-containing insulating layer 21a to form a second barrier film made of Mn-containing oxide. The CuMn alloy film 25 covering the inner wall of the connection hole 23 may not have a uniform film thickness.

  Here, a film is formed by a sputtering method using a CuMn alloy target in which Mn is added to Cu so as to have an atomic concentration of 0.5% to 20%. By containing Mn in the CuMn alloy target at an atomic concentration within the above range, Mn can be present in a solid solution state in Cu. In addition, it is preferable that Mn is contained at a high concentration within the above-mentioned range because the second barrier film made of Mn-containing oxide can be reliably formed even when the seed layer is thinned with miniaturization. . Here, for example, a 2 atm% Mn target is used. Here, the CuMn alloy film 25 is formed by the sputtering method, but it is formed by the chemical vapor deposition (CVD) method or the atomic layer deposition (ALD) method. Also good.

  Next, as shown in FIG. 2D, a conductive layer 26 made of 0.5 μm to 1.2 μm of Cu is deposited by electrolytic plating while filling the wiring groove 22 and the connection hole 23. Here, the conductive layer 26 made of Cu is formed. However, the conductive layer 26 may be an alloy film of Cu with a metal other than Cu, and the metal other than Cu is contained in Cu. A material that does not increase the resistance of the wiring even when the wiring is used is used.

  Next, as shown in FIG. 2 (e), heat treatment is performed at 200 ° C. to 400 ° C. for 5 minutes to 30 minutes, for example, 300 ° C. for 5 minutes. At this time, this heat treatment is preferably performed in an inert gas atmosphere containing oxygen. Here, the heat treatment is performed in a nitrogen atmosphere containing 1 ppm to 10% by volume of oxygen.

As a result, Mn is diffused from the CuMn alloy film 25 (see FIG. 2D) and reacts with oxygen in the oxygen-containing insulating layer 21 a exposed on the inner wall of the connection hole 23. Then, a second barrier film 27 made of Mn-containing oxide is formed with a film thickness of 2 nm to 4 nm on the side wall of the connection hole 23 exposed from the first barrier film 24. Here, since the oxygen-containing insulating layer 21a is formed of MSQ, and Mn also reacts with Si, the composition of the Mn-containing oxide constituting the second barrier film 27 is Mn _x Si _y O _z (x : Y: z is represented by 1: 1: 3 to 1: 3: 5).

  Further, by performing the heat treatment in an atmosphere containing oxygen, excess Mn other than Mn necessary for forming the second barrier film 27 reacts with oxygen in the atmosphere on the surface of the conductive layer 26, and the MnO film 27 'is formed. Since the MnO film 27 ′ is removed in a later process, the increase in resistance due to Mn remaining in the wiring or via is prevented.

  Thereafter, as shown in FIG. 2 (f), the MnO film 27 ′ (see FIG. 2 (e), for example) is formed up to the middle of the protective insulating layer 21c by, for example, chemical mechanical polishing (CMP). ), The conductive layer 26 (see FIG. 2E), the first barrier film 24 and the protective insulating layer 21c are removed by polishing, so that the wiring 28 and vias made of Cu are formed in the wiring grooves 22 and the connection holes 23. 29, respectively. By repeating the steps from FIG. 1A to FIG. 2F described above, a Cu multilayer wiring structure is completed.

  According to such a method of manufacturing a semiconductor device and the semiconductor device obtained thereby, in the oxygen-containing insulating layer 21a exposed to the side wall of the connection hole 23 by performing heat treatment to diffuse Mn in the CuMn alloy film. React with oxygen. As a result, the second barrier film 27 made of Mn-containing oxide is formed in a state of covering the side wall of the connection hole 23 exposed from the first barrier film 24. Therefore, since the first barrier film 24 or the second barrier film 27 is surely interposed between the interlayer insulating film 21 and the wiring 28 and the via 29, diffusion of Cu from the wiring 28 and the via 29 is prevented. Cu oxidation is prevented. Therefore, the electromigration resistance of the semiconductor device formed by this method can be secured, the wiring reliability can be improved, and the high resistance of the wiring can be prevented.

  In addition, according to the present embodiment, since the adhesion between the second barrier film 27 made of MnO and the wirings 28 and vias 29 made of Cu is high, electromigration resistance can be ensured also by this.

  In the present embodiment, as described with reference to FIG. 2E, after the wiring groove 22 and the connection hole 23 provided with the CuMn alloy film are filled with the conductive layer 26, heat treatment is performed, Although the example of forming the barrier film 27 has been described, after the CuMn alloy film is formed, heat treatment is performed before the wiring groove 22 and the connection hole 23 are filled with the conductive layer 26, and Mn is exposed to the side wall of the connection hole 23. The second barrier film 27 made of Mn-containing oxide may be formed by reacting with oxygen in the containing insulating layer 21a. However, in this case, it is preferable to adjust the temperature and time of the heat treatment so that the seed layer does not aggregate due to the heat treatment and subsequent filling failure occurs.

  In the present embodiment, the example in which the interlayer insulating film 21 includes the oxygen-free insulating layer 21b has been described. However, the present invention can be applied even if the interlayer insulating film 21 is formed only of an insulating layer containing oxygen. is there.

  In the present embodiment, the method of forming the upper layer wiring 28 and the via 29 over the lower layer wiring 16 has been described as an example. However, the lower layer wiring 16 and a via (not shown) communicating with the bottom thereof are formed by the same method. It is also possible to form.

(Second Embodiment)
Next, a second embodiment of the present invention will be described using the manufacturing process sectional views of FIGS. The same components as those in the first embodiment are described with the same reference numerals, and the steps until the first barrier film 24 is formed are performed in the same manner.

  As shown in FIG. 3A, as in the first embodiment, the first barrier film 24 is formed on the protective insulating layer 21c so as to cover the inner wall of the wiring groove 22 and the bottom of the connection hole 23.

  Next, as shown in FIG. 3B, the first barrier film provided at the bottom of the connection hole 23 is formed by reverse sputtering using argon (Ar) or reactive ion etching (RIE). Remove. Thus, since the first barrier film 24 is not interposed between the via formed in the connection hole 23 in the later process and the lower layer wiring 16, the resistance of the wiring can be reduced as compared with the first embodiment. Is preferable.

  The subsequent steps are performed by the same method as in the first embodiment. That is, as shown in FIG. 3C, an alloy film (CuMn) of Cu and manganese (Mn) in a state of covering the inner wall of the wiring groove 22 provided with the first barrier film 24 and the connection hole 23. Alloy film) 25 is formed. Next, as shown in FIG. 4D, a conductive layer 26 made of Cu is deposited by electrolytic plating in a state where the wiring grooves 22 and the connection holes 23 are embedded. Subsequently, as shown in FIG. 4E, a second barrier film 27 made of an Mn-containing oxide is formed by performing a heat treatment so as to cover the side wall of the connection hole 23 where the oxygen-containing insulating layer 21a is exposed. Form. Thereafter, as shown in FIG. 4 (f), part of the protective insulating layer 21c is removed by polishing, thereby forming wirings 28 and vias 29 in the wiring grooves 22 and the connection holes 23, respectively. A Cu multilayer wiring structure is completed.

  Even in such a method of manufacturing a semiconductor device and the semiconductor device obtained thereby, the first barrier film 24 or the second barrier film 27 is reliably provided between the interlayer insulating film 21 and the wiring 28 and via 29. Since it is interposed, the same effect as in the first embodiment can be obtained.

  Further, according to the present embodiment, since the first barrier film 24 is not interposed between the lower layer wiring 16 and the via 29, the resistance of the wiring can be reduced.

(Modification 1)
As a first modification of the second embodiment, as shown in FIG. 5, an etching stopper made of, for example, silicon nitride (SiN) or silicon carbide (SiC) between the oxygen-containing insulating layer 21a and the oxygen-free insulating layer 21b. A structure in which the film 31 is formed and the connection hole 23 reaching the lower layer wiring 16 is formed in the etching stopper film 31, the oxygen-containing insulating layer 21a, and the protective insulating film 17 may be employed.

Even in such a method for manufacturing a semiconductor device and a semiconductor device, the first barrier film 24 or the second barrier film 27 is reliably interposed between the interlayer insulating film 21, the wiring 28, and the via 29. The same effects as in the first embodiment can be obtained. Further, by providing the etching stopper film 31 made of SiN or SiC having a relative dielectric constant higher than that of SiO ₂ , the wiring trench 22 and the connection hole 23 are formed with good process controllability although the inter-wiring capacity increases. be able to.

(Modification 2)
As a second modification of the second embodiment, as in the first modification, an etching stopper film 31 made of SiN or SiC is formed between the oxygen-containing insulating layer 21a and the oxygen-free insulating layer 21b, and the wiring 28 is formed. The inter-wiring insulating film to be formed may be formed of only the oxygen-free insulating layer 21b. In this case, a material having high CMP resistance is used for the oxygen-free insulating layer 21b.

Even in such a method for manufacturing a semiconductor device and a semiconductor device, the first barrier film 24 or the second barrier film 27 is reliably interposed between the interlayer insulating film 21, the wiring 28, and the via 29. The same effects as in the first embodiment can be obtained. Further, since the protective insulating layer 21c (see FIG. 5) made of SiO ₂ having a relatively high relative dielectric constant is not provided as compared with the semiconductor device of Modification 1, the inter-wiring capacitance can be reduced. it can.

(Modification 3)
As a third modification of the second embodiment, the inter-wiring insulating film in which the wiring 28 is formed may be formed of only the oxygen-free insulating layer 21b. In this case, a material having high CMP resistance is used for the oxygen-free insulating layer 21b.

Even in such a method for manufacturing a semiconductor device and a semiconductor device, the first barrier film 24 or the second barrier film 27 is reliably interposed between the interlayer insulating film 21, the wiring 28, and the via 29. The same effects as in the second embodiment can be obtained. As compared with the semiconductor device of the second embodiment, since the protective insulating layer 21c made of SiO ₂ (FIG. 2 (f) reference is not provided, it is possible to reduce the inter-wiring capacitance.

FIG. 6 is a manufacturing process cross-sectional view (No. 1) for describing the first embodiment of the semiconductor device manufacturing method of the present invention; FIG. 6 is a manufacturing process sectional view (No. 2) for describing the first embodiment of the manufacturing method of the semiconductor device of the invention; It is manufacturing process sectional drawing (the 1) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 2) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is sectional drawing for demonstrating the modification 1 of 2nd Embodiment which concerns on the semiconductor device of this invention. It is sectional drawing for demonstrating the modification 2 of 2nd Embodiment which concerns on the semiconductor device of this invention. It is sectional drawing for demonstrating the modification 3 of 2nd Embodiment which concerns on the semiconductor device of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 21 ... Interlayer insulating film, 21a ... Oxygen-containing insulating layer, 21b ... Oxygen-free insulating layer, 22 ... Wiring groove, 23 ... Connection hole, 24 ... First barrier film, 25 ... CuMn alloy film, 27 ... second barrier film, 28 ... wiring, 29 ... via

Claims (8)

In a method for manufacturing a semiconductor device in which a conductive layer containing copper is embedded in a recess provided in an insulating film on a substrate,
A first step of forming the recess reaching the substrate in the insulating film having an oxygen-containing insulating layer provided on the substrate;
Forming a first barrier film for preventing copper diffusion from the conductive layer on the insulating film so as to cover the inner wall of the recess so as to partially expose the oxygen-containing insulating layer; Process,
A third step of forming an alloy film made of copper and a metal other than copper in a state of covering an inner wall of the recess provided with the first barrier film;
In the oxygen-containing insulating layer in which the conductive layer containing copper is formed on the alloy film in a state of embedding the recess, and heat treatment is performed to expose a metal other than copper in the alloy film on the inner wall of the recess. A fourth step of forming a second barrier film made of a metal-containing oxide for preventing copper diffusion from the conductive layer on the inner wall of the recess exposed from the first barrier film by reacting with oxygen A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the metal is manganese. In the manufacturing method of the semiconductor device according to claim 1,
In the fourth step, the second barrier film is formed after the conductive layer is formed. A method of manufacturing a semiconductor device, wherein: In the manufacturing method of the semiconductor device according to claim 1,
Before the first step, performing a step of forming the insulating film at least on the lower layer side of the oxygen-containing insulating layer on the substrate,
In the first step, a wiring groove is formed on the upper layer side of the insulating film, and a connection hole that communicates with the bottom of the wiring groove is formed in the oxygen-containing insulating layer on the lower layer side. Forming the recess comprising the connection hole;
In the second step, the first barrier film is formed so as to cover the inner wall of the wiring groove so as to expose the side wall of the connection hole,
In the fourth step, a second barrier film is formed on a side wall of the connection hole exposed from the first barrier film. A method of manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 4,
Between the second step and the third step,
A process for removing the first barrier film formed on the bottom of the connection hole is performed. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 4,
An upper layer side of the insulating film has an oxygen-free insulating layer. A method of manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 6.
The oxygen-containing insulating layer is made of an inorganic material,
The method for manufacturing a semiconductor device, wherein the oxygen-free insulating layer is made of an organic material. An insulating film having an oxygen-containing insulating layer provided on the substrate;
A conductive layer containing copper that fills a recess reaching the substrate provided in the insulating film;
A first barrier film provided between the insulating film and the conductive layer and preventing diffusion of copper from the conductive layer; and the first barrier film between the oxygen-containing insulating layer and the conductive layer. And a second barrier film made of a metal-containing oxide that prevents diffusion of copper from the conductive layer, and is provided in a state of complementing the unformed region of the first barrier film. .

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