JP2010103162A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress formation of a void in a pattern of a via, wiring, etc. <P>SOLUTION: After a via hole 33 reaching lower-layer wiring 30 is formed and a barrier metal layer 34 and a seed layer 35a are formed, a plating layer is buried in the via hole 33 by an electrolytic plating method. At this time, assuming that an overhang 101b is formed at a frontage of the via hole 33 after the seed layer 35a is formed, the via hole 33 when having, for example, an opening diameter ≤70 nm is made to have an opening diameter W2 of ≥20 nm after the seed layer 35a is formed. Consequently, when electrolytic plating using the seed layer 35a is performed, the frontage is closed before the plating layer is buried in the via hole 33 to avoid the formation of a void. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a process of forming wirings or vias.

  In recent semiconductor devices, copper (Cu) is widely used as a material for wiring and vias. Wiring and vias using Cu are mainly formed using a damascene method (see, for example, Patent Documents 1 to 6).

In the formation of wiring or vias by the damascene method using Cu, for example, first, wiring grooves or via holes (recesses) are formed in the insulating layer, and a barrier using a refractory metal or the like is formed on the insulating layer surface including the inner walls of the recesses. A metal layer is formed. Then, a seed layer using Cu is formed on the barrier metal layer by using a PVD (Physical Vapor Deposition) method, a CVD (Chemical Vapor Deposition) method, a sputtering method, etc., and electroplating using the seed layer By this method, a Cu plating layer is embedded in the recess. Thereafter, unnecessary Cu and barrier metal layers formed on the insulating layer are removed by CMP (Chemical Mechanical Polishing), thereby forming wirings or vias using Cu.
JP 2001-244216 A JP 2004-014816 A JP 2005-217346 A JP 2006-148074 A JP 2006-148075 A JP 2007-227819 A

  In embedding the plating layer in the recess, the generation of voids often becomes a problem. Voids can cause deterioration of electrical characteristics of wiring or vias and shortening of life. One of the causes of the generation of voids is that film formation on the inner wall of the concave portion of the seed layer before the plating layer is embedded in the concave portion tends to be non-uniform.

  For example, if the seed layer is formed in an overhang shape protruding so as to narrow the opening of the recess, the opening is closed before the recess is completely filled with the plating layer during electrolytic plating. May occur. Such voids are more likely to occur as fine wiring or vias are formed.

  In addition, if the formed seed layer has a thin portion or an unformed region such as a side wall of a recess, such a thin portion is dissolved in the plating solution or an unformed region is not formed during electrolytic plating. In some cases, the plating layer may be spread, resulting in poor filling of the plating layer and voids. Even if the recesses are sufficiently filled with the plating layer during electrolytic plating, voids are generated from the thinned or unformed regions of the seed layer after the subsequent heat treatment process. Sometimes it comes. Such voids are likely to occur when a low dielectric constant (Low-k) material is used for the insulating layer and the concave portion is formed in a bow shape by etching.

  According to one aspect of the method, a step of forming a recess having an opening size of 50 nm or more and 70 nm or less in the insulating layer, a first metal layer is formed over the inner wall of the recess and the insulating layer, and after the formation of the first metal layer And a step of forming a second metal layer filling the recess on the first metal layer, and a method of manufacturing a semiconductor device comprising: Is provided.

  According to another aspect of the method, the step of forming a concave portion having a bow shape in the insulating layer, and the film thickness in the side wall portion of the concave portion above the insulating layer including the inside of the concave portion is 10 nm or more, In addition, a method for manufacturing a semiconductor device is provided, which includes a step of forming a first metal layer leaving an opening in the recess, and a step of forming a second metal layer filling the recess on the first metal layer. Is done.

  According to the disclosed method for manufacturing a semiconductor device, generation of voids can be effectively suppressed, and a high-performance and highly reliable semiconductor device can be realized.

Hereinafter, it will be described in detail with reference to the drawings.
First, the first embodiment will be described.
First, an example of a semiconductor device provided with wirings and vias will be described.

FIG. 1 is a schematic partial sectional view of an example of a semiconductor device.
In a semiconductor device 1 illustrated in FIG. 1, a MOS (Metal Oxide Semiconductor) transistor 4 is formed in an element region defined by an element isolation insulating film 3 formed on a semiconductor substrate 2 by an STI (Shallow Trench Isolation) method or the like. Have a structure.

  The MOS transistor 4 includes a gate electrode 4b formed through a gate insulating film 4a, a sidewall insulating film 4c formed on the sidewall of the gate electrode 4b, and a source / drain formed in the semiconductor substrate 2 on both sides of the gate electrode 4b. Regions 4d and 4e are provided.

On the semiconductor substrate 2 on which such a MOS transistor 4 is formed, a multilayer wiring including wirings 5, 6, 7 and vias 8 is formed.
The lower wirings 5 and 6 are connected to the source / drain regions 4d and 4e of the MOS transistor 4 through conductive plugs 10 and 11 formed through the interlayer insulating film 9, respectively. Barrier metal layers 13 and 14 are formed between the wirings 5 and 6 and the interlayer insulating film 12, and a cap layer 15 is formed on the wirings 5 and 6 and the interlayer insulating film 12.

  Further, of the lower wirings 5 and 6, one wiring 6 is connected to the upper wiring 7 through a via 8 formed through the interlayer insulating film 16. A barrier metal layer 17 is formed between the via 8 and the interlayer insulating film 16. A cap layer 18 is formed on the via 8 and the interlayer insulating film 16. In addition, a barrier metal layer 20 is formed between the wiring 7 and the interlayer insulating film 19.

  In the upper layer of such a multilayer wiring, as many wiring layers having the same configuration as the number of necessary layers are formed according to the type of the semiconductor device 1, and electrode pads for external connection are formed on the uppermost layer. It becomes like this.

Here, the case where the wirings 5, 6, 7 and the via 8 are all formed by the single damascene method is illustrated.
Subsequently, a method for forming wirings and vias applicable to the semiconductor device having the above configuration will be described.

First, as an example, a method for forming a via by a single damascene method will be described. The via is formed by the following flow, for example.
2 is a schematic cross-sectional view of the main part of the via hole forming process, FIG. 3 is a schematic cross-sectional view of the main part of the barrier metal layer forming process, FIG. 4 is a schematic cross-sectional view of the main part of the seed layer forming process, and FIG. It is a principal part cross-sectional schematic diagram of an example.

  When forming the via, first, the cap layer 31 and the insulating layer 32 are formed on the lower layer wiring 30. For the cap layer 31, for example, silicon carbide (SiC), a carbon-containing silicon oxide film (SiOC), or the like can be used. Further, for example, silicon oxide (SiO), an organic or inorganic low-k material (including a porous structure), or the like can be used for the insulating layer 32 in whole or in part. After the formation of the cap layer 31 and the insulating layer 32, via holes 33 reaching the lower layer wiring 30 through the insulating layer 32 and the cap layer 31 are formed using photolithography technology and etching technology as shown in FIG. Form.

  After the formation of the via hole 33, as shown in FIG. 3, the barrier metal layer 34 is left on the surface of the insulating layer 32 including the wall surface of the via hole 33 by using, for example, a sputtering method so as to leave an opening leading to the via hole 33. Form. For the barrier metal layer 34, a refractory metal such as tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), ruthenium (Ru), or the like can be used. For the barrier metal layer 34, one of Ta, Ti, W, Zr, and Ru, an alloy containing at least one of these metals, or a nitrogen compound of these metals or alloys can be used. Furthermore, the barrier metal layer 34 can be a single layer of these metals, alloys, nitrogen compounds, or a laminated structure combining them.

  After the formation of the barrier metal layer 34, as shown in FIG. 4, the seed layer 35a is formed on the barrier metal layer 34 so as to leave an opening leading to the via hole 33 by using, for example, a sputtering method. When forming a via using Cu, for example, Cu or Cu and aluminum and aluminum (Al), Ti, Zr, nickel (Ni), silver (Ag), palladium (Pd), manganese (Mn) are used as the seed layer 35a. ), A Cu alloy containing at least one of magnesium (Mg) is used. The seed layer 35a can be a single layer of Cu or Cu alloy, a laminated structure of Cu and Cu alloy, or a laminated structure of Cu alloy and Cu alloy.

  After the seed layer 35a is formed, a plating layer 35b of a wiring material such as Cu is formed in the via hole 33 by an electrolytic plating method using the seed layer 35a. After the formation of the plating layer 35b, the unnecessary plating layer 35b, seed layer 35a, and barrier metal layer 34 on the insulating layer 32 are usually removed by CMP.

  Here, when forming the plating layer 35b by the electrolytic plating method, as shown in FIG. 5, a void 100 may be generated in the plating layer 35b. The void 100 may cause deterioration of electrical characteristics such as an increase in resistance of a via finally obtained, an increase in capacitance, a signal delay, a shortened life, and the like. The generation of the void 100 is affected by the formation state of the barrier metal layer 34 and the seed layer 35a formed prior to the plating layer 35b.

  That is, in the barrier metal layer 34 and the seed layer 35a, as shown in FIGS. 3 and 4, overhangs 101a and 101b may be formed at the openings of the via holes 33, respectively. The overhang 101b of the seed layer 35a is easily promoted by the overhang 101a of the barrier metal layer 34 formed before the seed layer 35a. When such overhangs 101a and 101b are formed in the barrier metal layer 34 and the seed layer 35a, the opening size (diameter) of the front opening leading to the via hole 33 is reduced accordingly. Therefore, at the time of electrolytic plating using the seed layer 35a, before the plating layer 35b is sufficiently embedded in the via hole 33, the gap is closed and the phenomenon that the void 100 is generated easily occurs.

Moreover, FIG. 6 is a principal part cross-sectional schematic diagram of another example after plating layer formation.
In the via hole 33 after the step of forming the barrier metal layer 34 or the seed layer 35a, particularly in the side wall thereof, the unformed region 102 or the extremely thin region 103 in which they are hardly formed may be formed. Furthermore, the seed layer 35a once formed may be dissolved in the plating solution at the time of subsequent electrolytic plating, and an unformed region 102 may be formed. If the unformed region 102 or the ultrathin region 103 exists, the plating layer 35b is not sufficiently embedded in the via hole 33, and the void 104 is likely to be generated. Even if the via hole 33 appears to be sufficiently filled with the plating layer 35b, voids may be generated when the subsequent process (heat treatment process or the like) is performed.

  In recent years, patterns of vias, wirings, and the like have been miniaturized, but as the pattern size is reduced, the generation of voids 100 due to the blockage of the pattern openings as described above, and the generation of voids 104 due to poor coverage of the pattern inner walls. Is more likely to occur. In particular, when a via having a diameter of 70 nm or less or a wiring having a width of 70 nm or less is to be formed, such voids 100 and 104 are more likely to occur.

Therefore, here, the plating layer 35b as described above is formed under various conditions, and the filling state of the via hole 33 by the plating layer 35b is verified.
In order to verify the buried state of the via hole 33, first, as shown in FIG. 2, a plurality of via holes 33 having an opening diameter (diameter) W of 70 nm and a predetermined depth, for example, a depth of 250 nm, are formed in the insulating layer 32. .

  Next, as shown in FIGS. 3 and 4, a barrier metal layer 34 and a seed layer 35a are sequentially formed on the entire surface of the insulating layer 32 in which a plurality of via holes 33 are formed, using a sputtering method. At that time, the barrier metal layer 34 and the seed layer 35a are formed under various conditions, and the opening diameter W1 of the via hole 33 after the formation of the barrier metal layer 34 and the opening diameter W2 of the via hole 33 after the formation of the seed layer 35a are adjusted. . The opening diameters W1 and W2 are the diameters of the portions where the opening of the via hole 33 is the narrowest due to the overhangs 101a and 101b.

Thus, after forming the barrier metal layer 34 with the opening diameter W1 and the seed layer 35a with the opening diameter W2 under each condition, the plating layer 35b is formed under certain conditions by electrolytic plating.
And the presence or absence of the void in the formed plating layer 35b is confirmed by cross-sectional observation using a high resolution SEM (Scanning Electron Microscope). From the cross-sectional observation result, the number of via holes 33 in which no void is generated among the plurality of via holes 33 is obtained, and the ratio (embedding achievement rate) is obtained from the following equation (1).

Embedding achievement rate (%) = number of void-free via holes / total number of via holes × 100 (1)
Table 1 shows an example of the results of examining the formation conditions of the barrier metal layer 34 and the seed layer 35a, the opening diameters W1 and W2 after the formation, and the filling achievement rate after the formation of the plating layer 35b. Table 2 shows the conditions for forming the barrier metal layer 34 and the seed layer 35a used in the investigation of Table 1.

  Note that, as described above, there is a case in which a void is generated by closing the opening of the via hole 33 before being sufficiently filled with the plating layer 35b, as described above (FIG. 5). Further, as another form of the filling failure, as described above, there is a case where voids are generated due to the covering failure of the barrier metal layer 34 and the seed layer 35a on the inner wall of the via hole 33 (FIG. 6). Here, an embedding defect caused by closing the opening of the via hole 33 at the time of electrolytic plating is investigated, and in order to selectively detect such embedding defect, the barrier metal layer 34 and the seed layer 35a are covered on the inner wall of the via hole 33. The conditions that can be secured are set.

  As shown in Table 2, the barrier metal layer 34 is formed under two types of conditions BRM (a) and (b). In both conditions BRM (a) and (b), the barrier metal layer 34 is subjected to two steps of the target power and the bias power of the substrate (the substrate after the formation of the via hole 33 and before the formation of the barrier metal layer 34) during the formation thereof. (The multi-step sputtering method). Under the condition BRM (a), a barrier metal layer 34 having a total thickness of 15 nm, which is 10 nm in the first step and 5 nm in the second step, is formed. Further, under the condition BRM (b), the barrier metal layer 34 having a total thickness of 7 nm, which is 5 nm in the first step and 2 nm in the second step, is formed. The film thickness is a value in the field portion on the surface of the insulating layer 32.

  On the other hand, as shown in Table 2, the seed layer 35a is formed with a film thickness of 60 nm in all three types of target power and bias power conditions Seed (a) to (c). The film thickness is a value in the field portion on the surface of the insulating layer 32.

  A combination of conditions BRM (a) and (b) and conditions Seed (a) to (c) as shown in Table 2, and opening diameters W1 and W2 in a range as shown in Table 1 for a plurality of via holes 33. Thus, samples A to F in which the barrier metal layer 34 and the seed layer 35a are formed are obtained. And about each sample A-F, electrolytic plating is performed on fixed conditions, the plating layer 35b is formed, the cross-sectional observation using SEM is performed, and an embedding achievement rate is calculated | required.

  From Table 1, it is samples D and E that the filling achievement rate is 100%, that is, the plurality of via holes 33 are filled with the plating layer 35b without any voids. In Samples D and E, the opening diameter W2 of all the via holes 33 after the formation of the seed layer 35a (before the formation of the plating layer 35b) is 20 nm or more.

  On the other hand, in samples A to C and F in which the filling achievement rate is less than 100%, as shown in Table 1, the opening diameter W2 after the seed layer 35a is formed in the plurality of via holes 33 is less than 20 nm. Things are included. However, in Samples A to C and F, generation of voids is not observed in the plurality of via holes 33 in which the opening diameter W2 after formation of the seed layer 35a is 20 nm or more.

Thus, by setting the opening diameter W2 after forming the seed layer 35a to 20 nm or more, generation of voids in the via hole 33 can be effectively suppressed.
Further, from Table 1, when the barrier metal layer 34 is formed under the condition BRM (a) and the opening diameter W1 after the formation is less than 50 nm, the seed layer of all the via holes 33 regardless of the formation conditions of the seed layer 35a. The opening diameter W2 after the formation of 35a does not become 20 nm or more.

Here, the relationship between the opening diameter W1 after forming the barrier metal layer 34 and the opening diameter W2 after forming the seed layer 35a will be described.
Table 3 shows an example of the results of examining the formation conditions of the barrier metal layer 34 and the seed layer 35a and the opening diameters W1 and W2 after the formation. Table 4 shows the conditions for forming the barrier metal layer 34 and the seed layer 35a used in the investigation of Table 3.

  Here, as shown in Table 4, the barrier metal layer 34 is formed under the condition BRM (c) in which the target power and the bias power are changed in two steps during the formation thereof. Under the condition BRM (c), a barrier metal layer 34 having a total thickness of 6 nm is formed, with a film thickness of 5 nm in the first step and a film thickness of 1 nm in the second step. The film thickness is a value in the field portion on the surface of the insulating layer 32. When the barrier metal layer 34 is formed under this condition BRM (c), the opening diameter W1 after the formation can be set to 50 nm or more.

  On the other hand, as shown in Table 4, the seed layer 35a is formed with a film thickness of 60 nm in all three different target power and bias power conditions Seed (d) to (f). The film thickness is the film thickness in the field portion on the surface of the insulating layer 32.

  By combining the condition BRM (c) and the conditions Seed (d) to (f), the barrier metal layer 34 and the seed layer 35a are formed with the opening diameters W1 and W2 in the range shown in Table 3 for the plurality of via holes 33. Samples GI were obtained.

  From Table 3, even if the opening diameter W1 after the formation of the barrier metal layer 34 is 50 nm or more, the opening diameter W2 after the formation of the seed layer 35a of all the via holes 33 should be 20 nm or more depending on the formation conditions of the seed layer 35a. It can be seen that there are cases where it is not possible. Therefore, when the opening diameter W2 after forming the seed layer 35a is set to 20 nm or more, it is important to set the opening diameter W1 after forming the barrier metal layer 34 to 50 nm or more and to optimize the formation conditions of the seed layer 35a. It can be said that it will come.

  Note that, here, the case where vias are formed by a single damascene method has been described as an example, but wiring formation by a single damascene method can also be performed in the same manner as the above via formation flow.

  In addition, here, the result of investigating the filling state of the via hole 33 having a diameter of 70 nm as an example has been described. The same result as that obtained for the via hole 33 can be obtained also when a wiring groove having a width of 70 nm is formed by the same formation flow and the plating layer is embedded in the wiring groove through the barrier metal layer and the seed layer. In the case of a wiring groove having an opening width W of 70 nm, the opening width W2 after forming the seed layer is set to 20 nm or more, the opening width W1 after forming the barrier metal layer is set to 50 nm or more, and the opening width W2 after forming the seed layer is set to What is necessary is just to be 20 nm or more. The opening widths W, W1, and W2 of the wiring grooves are the widths of the portions where the width of the wiring groove is the narrowest.

  Thus, in the first embodiment, a pattern (via hole, wiring groove) with an opening size of 70 nm is formed, and a plating layer is formed there via the barrier metal layer and the seed layer. At that time, the opening size (opening diameter, opening width) of the pattern opening immediately before the formation of the plating layer is set to 20 nm or more. Thereby, generation | occurrence | production of a void can be suppressed effectively and a plating layer can be embedded in a pattern. As a result, it is possible to form a wiring layer that suppresses deterioration of electrical characteristics, shortening of life, signal delay, and the like, and a high-performance and highly reliable semiconductor device can be realized.

  In the above description, a pattern having an opening size of 70 nm has been described as an example. However, the opening size of a pattern to which the above method can be applied is not limited to 70 nm. In particular, for a finer pattern with an opening dimension of less than 70 nm (for example, an opening dimension of 50 nm to 70 nm), the opening diameter of the pattern opening immediately before the formation of the plating layer is set to 20 nm or more in the same manner. Generation of voids can be effectively suppressed. Even in the case of a pattern having an opening dimension exceeding 70 nm (for example, an opening dimension of 100 nm), the generation of voids in the pattern can be effectively suppressed according to the above method.

  When forming the seed layer, the seed layer may be formed so that the opening size of the pattern opening after forming the seed layer is 20 nm or more and 65% or less of the original pattern opening size. preferable. This is because in a range exceeding 65%, the seed layer becomes thin, and the seed layer is dissolved in the plating solution at the time of subsequent electrolytic plating, and the possibility of occurrence of voids due to this increases.

Hereinafter, examples using the above method will be described.
(First embodiment)
First, the first embodiment will be described. 7 to 11 are explanatory views of the via forming process of the first embodiment. Hereafter, each process is demonstrated in order with reference to FIGS.

FIG. 7 is a schematic sectional view showing an important part of a via hole forming step according to the first embodiment.
First, as shown in FIG. 7, a cap layer 41, an interlayer insulating film 42, and a hard mask 43 are sequentially formed on a lower layer wiring 40 electrically connected to an element such as a MOS transistor formed on a semiconductor substrate. To do. The cap layer 41 and the hard mask 43 are each formed of, for example, SiC, SiOC, or the like with a film thickness of several tens of nm by a CVD method. As the interlayer insulating film 42, for example, an organic or inorganic Low-k film (including a porous structure) is formed with a film thickness of 100 nm to several hundreds of nm by a coating method or a CVD method. For example, the cap layer 41, the interlayer insulating film 42, and the hard mask 43 are formed with a total film thickness of about 140 nm.

After the formation of the cap layer 41, the interlayer insulating film 42, and the hard mask 43, the photolithography technique and the etching technique are used to penetrate the hard mask 43, the interlayer insulating film 42, and the cap layer 41 to reach the lower layer wiring 40. A via hole 44 having a diameter (opening diameter W) of 70 nm is formed. For example, in forming the via hole 44, a gas containing fluorocarbon (CF gas), a gas containing ammonia (NH ₃ gas), and a gas containing nitrogen (N ₂ ) and hydrogen (H ₂ ) (N ₂ / H Plasma etching using ₂ gas) as an etching gas can be used.

FIG. 8 is a schematic cross-sectional view of the relevant part in the barrier metal layer forming step of the first embodiment.
After the formation of the via hole 44, as shown in FIG. 8, for example, a sputtering method is used to leave an opening leading to the via hole 44 on the interlayer insulating film 42 (wall surface of the via hole 44) and the hard mask 43. A metal layer 45 is formed. Here, the barrier metal layer 45 is formed so that the opening diameter W1 after the formation of the barrier metal layer 45 is 50 nm or more.

  When the barrier metal layer 45 is formed by a sputtering method, both a non-bias sputtering method that does not apply a bias to the substrate and a bias sputtering method that performs sputtering while applying a bias to the substrate can be used. it can. Further, the barrier metal layer 45 can be formed by a multi-step sputtering method in which the target power and the substrate bias power are changed during the formation, in addition to the method of forming the barrier metal layer 45 from a constant condition throughout the formation.

An example of the conditions for forming the barrier metal layer 45 in two steps is as follows.
<First step>
Film thickness (on hard mask 43): 3 nm to 5 nm
Target power: 5kW-40kW
Bias power: 0W to 500W
Pressure: 4 × 10 ⁻² Pa
<Second step>
Film thickness (on hard mask 43): 0 nm to 3 nm
Target power: 0.1 kW to 5 kW
Bias power: 0W to 500W
Pressure: 4 × 10 ⁻² Pa
By using such conditions, it is possible to make the opening diameter W1 after the formation of the barrier metal layer 45 50 nm or more without causing a coating defect on the wall surface of the via hole 44.

FIG. 9 is a schematic sectional view showing an important part of the seed layer forming step of the first embodiment.
After the formation of the barrier metal layer 45, as shown in FIG. 9, a Cu seed layer 46a is formed on the barrier metal layer 45, leaving an opening leading to the via hole 44, for example, by sputtering. Here, the seed layer 46a is formed so that the opening diameter W2 after the seed layer 46a is formed is 20 nm or more.

In addition to Cu, alloys such as copper aluminum (CuAl) and copper titanium (CuTi) can also be used for the seed layer 46a.
When the seed layer 46a is formed by a sputtering method, either a non-bias sputtering method or a bias sputtering method can be used.

An example of the conditions for forming the seed layer 46a is as follows.
Film thickness (on hard mask 43): 30 nm to 100 nm
Target power: 5kW-30kW
Bias power: 0W to 200W
Pressure: 1 × 10 ⁻⁵ Pa to 10 Pa
By using such conditions, it is possible to make the opening diameter W2 after forming the seed layer 46a 20 nm or more without causing a coating failure on the surface of the barrier metal layer 45.

The seed layer 46a can also be formed by a multi-step sputtering method.
FIG. 10 is a schematic cross-sectional view of the relevant part in the plating layer forming step of the first embodiment.

After the formation of the seed layer 46a, as shown in FIG. 10, a Cu plating layer 46b as a wiring material is embedded in the via hole 44 by an electrolytic plating method using the seed layer 46a. For example, the plating layer 46b having a film thickness of 500 nm to 1500 nm is formed under the condition of a current density of 7 A / cm ^{2 to} 30 A / cm ² by dipping in a copper sulfate bath.

  At the time of this electrolytic plating, as described above, the opening diameter W1 after forming the barrier metal layer 45 is 50 nm or more, and the opening diameter W2 after forming the seed layer 46a is 20 nm or more. Therefore, the plating layer 46 b can be embedded in the via hole 44 without generating a void in the via hole 44 due to the closing of the opening.

FIG. 11 is a schematic sectional view showing an important part of a CMP process according to the first embodiment.
After the plating layer 46b is formed, unnecessary plating layer 46b, seed layer 46a and barrier metal layer 45 on the hard mask 43 are removed by CMP as shown in FIG. Thereby, the via 46 in which the seed layer 46 a and the plating layer 46 b are formed in the via hole 44 through the barrier metal layer 45 is obtained. Note that the minimum diameter (diameter of the portion excluding the barrier metal layer 45) W3 of the via 46 after CMP is 50 nm or more.

(Second embodiment)
Next, a second embodiment will be described. In the second embodiment, since the via hole forming step (FIG. 7) described in the first embodiment is the same, the subsequent steps will be described in order with reference to FIGS. .

FIG. 12 is a schematic sectional view showing an important part of a seed layer forming step according to the second embodiment.
Here, after forming the via hole 44 as shown in FIG. 7 and without forming a barrier metal layer, as shown in FIG. 12, a seed layer 46c containing Cu and Mn, for example, copper manganese (CuMn), is formed. An alloy seed layer 46c is formed. The seed layer 46c is formed by using, for example, a sputtering method, leaving an opening leading to the via hole 44 on the interlayer insulating film 42 (wall surface of the via hole 44) and the hard mask 43. Here, the seed layer 46c is formed so that the opening diameter W2 after the seed layer 46c is formed is 20 nm or more.

When the seed layer 46c is formed by a sputtering method, either a non-bias sputtering method or a bias sputtering method can be used.
An example of the conditions for forming the seed layer 46c is as follows.

Film thickness (on hard mask 43): 30 nm to 100 nm
Target power: 5kW-30kW
Bias power: 0W to 200W
Pressure: 1 × 10 ⁻⁵ Pa to 10 Pa
Mn addition amount: 0.1 atom% to 10 atom%
By using such conditions, it is possible to make the opening diameter W2 after formation of the seed layer 46c 20 nm or more without causing a coating defect on the wall surface of the via hole 44.

The seed layer 46c can also be formed by a multi-step sputtering method.
FIG. 13 is a schematic cross-sectional view of the relevant part in the plating layer forming step of the second embodiment.

After the formation of the seed layer 46c, as shown in FIG. 13, a Cu plating layer 46b is embedded in the via hole 44 by an electrolytic plating method using the seed layer 46c.
At the time of electrolytic plating, as described above, since the opening diameter W2 after the seed layer 46c is formed is set to 20 nm or more, the plating layer 46b can be embedded in the via hole 44 without generating a void.

FIG. 14 is a schematic sectional view showing an important part of a heat treatment process according to the second embodiment.
After the formation of the plating layer 46b, heat treatment is performed to thermally diffuse Mn added to the seed layer 46c. Mn in the seed layer 46c diffuses to the interface between the seed layer 46c and the interlayer insulating film 42 by heat treatment and reacts with Si and O in the interlayer insulating film 42 to react with Mn oxides such as MnSi _x O _y and MnO _x . Form. This Mn oxide has a barrier property sufficient to block diffusion of Cu into the interlayer insulating film 42.

  In this way, by forming the seed layer 46c containing Mn without forming the barrier metal layer, and performing the heat treatment after the formation of the plating layer 46b, at the interface between the wiring material and the interlayer insulating film 42, As shown in FIG. 14, the barrier layer 50 is formed in a self-aligning manner. The barrier layer 50 is formed on the sidewall of the via hole 44 with a film thickness of about 5 nm or less, for example.

  The heat treatment for diffusing Mn in this way to form the barrier layer 50 is performed at a temperature of 150 ° C. or more and a time of 30 seconds or more in an atmosphere such as a vacuum atmosphere, an inert gas atmosphere, an air atmosphere, or a trace oxygen atmosphere, for example. Can be performed under the following conditions.

FIG. 15 is a schematic sectional view showing an important part of a CMP process according to the second embodiment.
After the heat treatment for forming the barrier layer 50, as shown in FIG. 15, the unnecessary plating layer 46b, seed layer 46c and barrier layer 50 on the hard mask 43 are removed by CMP. Thereby, the via 46 in which the seed layer 46c and the plating layer 46b are formed through the barrier layer 50 formed in a self-aligned manner in the via hole 44 is obtained. Note that the minimum diameter (diameter of the portion excluding the barrier layer 50) W3 of the via 46 after CMP is 60 nm or more when the barrier layer 50 having a film thickness of 5 nm or less is formed.

  Note that the barrier layer 50 is subjected to CMP without the heat treatment step described in FIG. 14 to form the via 46, and then subjected to heat treatment in other steps, for example, heat at the time of forming an upper insulating film. It is also possible to form by using.

(Third embodiment)
Next, a third embodiment will be described. In the third embodiment, the process up to the formation process of the via hole 44 (FIG. 7) and the formation process of the barrier metal layer 45 (FIG. 8) described in the first embodiment are the same. These will be described in order with reference to FIGS.

FIG. 16 is a schematic sectional view showing an important part of a seed layer forming step according to the third embodiment.
After forming the via hole 44 and the barrier metal layer 45 as shown in FIG. 7 and FIG. 8, sputtering is performed under predetermined conditions as shown in FIG. A seed layer 46c containing Cu and Mn is formed. The seed layer 46c is formed so that the opening diameter W2 after the seed layer 46c is formed is 20 nm or more.

FIG. 17 is a schematic cross-sectional view of the relevant part in the plating layer forming step of the third embodiment.
After the formation of the seed layer 46 c, as shown in FIG. 17, electrolytic plating is performed under predetermined conditions to embed the Cu plating layer 46 b in the via hole 44. At the time of this electrolytic plating, the opening diameter W1 after the formation of the barrier metal layer 45 is set to 50 nm or more and the opening diameter W2 after the formation of the seed layer 46c is set to 20 nm or more, so that plating is performed in the via hole 44 without generating voids. Layer 46b can be embedded.

FIG. 18 is a schematic sectional view showing an important part of a heat treatment process according to the third embodiment.
After the formation of the plating layer 46b, heat treatment is performed under predetermined conditions, and a barrier layer 50 having a thickness of about 5 nm or less is formed at the interface between the wiring material, the interlayer insulating film 42, and the barrier metal layer 45 as shown in FIG. Form in a self-aligning manner.

Here, the formation state of the barrier layer 50 in the third embodiment will be described.
FIG. 19 is an explanatory diagram of the formation state of the barrier layer on the side wall of the via hole.
After the via hole 44 is formed in the interlayer insulating film 42 and the barrier metal layer 45 is formed, an unformed region 200 of the barrier metal layer 45 may be formed on the sidewall of the via hole 44 depending on the formation conditions. Depending on the manufacturing environment and handling during manufacturing, a modified barrier metal layer 45a in which the barrier metal layer 45 is oxidized and deteriorated before the formation of the subsequent seed layer 46c is generated on the sidewall of the via hole 44. There is also a possibility of end.

  However, even in such a case, when the seed layer 46c containing Mn is formed, the reaction between the diffused Mn and Si and O in the interlayer insulating film 42 in the unformed region 200 during the subsequent heat treatment, A reaction between the diffused Mn and O on the surface of the altered barrier metal layer 45a occurs. As a result, the barrier layer 50 is formed on the unformed region 200 and the altered barrier metal layer 45a. Similarly, when a reaction between diffused Mn and O present on the surface of the barrier metal layer 45 occurs, the barrier layer 50 is also formed on the barrier metal layer 45.

  As a result, the diffusion of Cu, which is a wiring material, into the interlayer insulating film 42 can be effectively blocked by the originally formed barrier metal layer 45 and the newly formed barrier layer 50. .

  After performing the heat treatment for forming the barrier layer 50, the unnecessary plating layer 46b, seed layer 46c, barrier layer 50, and barrier metal layer 45 on the hard mask 43 are removed by CMP to thereby remove the via 46. Is obtained. Note that the minimum diameter W3 of the via 46 after CMP (the diameter of the portion excluding the barrier metal layer 45 and the barrier layer 50) W3 is 40 nm or more when the barrier layer 50 having a film thickness of 5 nm or less is formed.

  In the above description, the case where the barrier metal layer and the seed layer are formed using the sputtering method has been described as an example. However, in addition to the sputtering method, a PVD method, a CVD method, an ALD (Atomic Layer Deposition) method, or the like is used. It can also be used.

  In the above description, the pattern formation using the single damascene method has been described as an example. However, the same method as described above is also used when pattern formation is performed using the dual damascene method in which the via hole and the wiring groove are simultaneously filled. Is possible.

Next, a second embodiment will be described.
In recent years, Cu is mainly used as a pattern material for wiring and vias for the purpose of reducing resistance, and a low-k material is mainly used as an interlayer insulating film material for the purpose of reducing capacitance. It is getting more.

  However, the Low-k film has a property of weak plasma resistance. Therefore, when trying to form wiring trenches and via holes in the low-k interlayer insulating film together with other insulating materials such as a cap layer and a hard mask by plasma etching, side etching occurs in the interlayer insulating film and bowing is formed. It may be done.

  Here, FIG. 20 to FIG. 24 are diagrams for explaining an example of a wiring formation process when a low-k material is used as an interlayer insulating film material. 20 is a diagram showing an example of the state after the formation of the barrier metal layer and the seed layer, FIG. 21 is a diagram showing an example of the initial stage of the plating layer formation, FIG. 22 is a diagram showing an example of the state after the formation of the plating layer, and FIG. FIG. 24 is a diagram showing an example of a state after heat treatment, and FIG. 24 is a diagram showing an example of a state after CMP.

For example, as shown in FIG. 20, first, a SiO film (TEOS film) 70 is formed by CVD using tetraethoxysilane (TEOS) above a semiconductor substrate on which elements such as MOS transistors are formed. Subsequently, an SiC film having a thickness of about 30 nm is formed as the cap layer 71. Thereafter, an interlayer insulating film 72 of a low-k film (including a porous structure) having a thickness of about 130 nm is formed on the cap layer 71 by a coating method or a CVD method. Then, a hard mask 73 is formed by laminating a SiC film 73a and a SiO film 73b having a predetermined thickness, and then the hard mask 73, the interlayer insulating film 72, and the cap layer 71 are sequentially etched by plasma etching. A wiring groove 74 having a size is formed. For example, the wiring trench 74 having a width of 50 nm to 100 nm and a depth of about 150 nm to 400 nm (aspect ratio> 2.5) is formed. Further, CF gas, NH ₃ gas, N ₂ / H ₂ gas, or the like is used as an etching gas for the formation.

  When the interlayer insulating film 72 is formed of a low-k film during the formation of the wiring trench 74, side etching is performed on the interlayer insulating film 72 due to the difference in etching rate with the hard mask 73 and the cap layer 71. This may cause a bowing 72a.

  After the formation of the wiring trench 74, Ta or the like is deposited by sputtering, for example, to form a barrier metal layer 75, and a deposition component 76c such as Cu is deposited to form a seed layer 76a. It is formed. The barrier metal layer 75 and the seed layer 76a are easily formed thinner on the side wall portion of the wiring groove 74 than on the hard mask 73 (field portion). In particular, when the bowing 72a is generated in the wiring groove 74 as described above, depending on the formation conditions of the barrier metal layer 75 and the seed layer 76a, the barrier metal layer 75 on the side wall of the wiring groove 74 is formed due to the shape. Or the seed layer 76a becomes very thin. FIG. 20 illustrates the case where the seed layer 76a is formed to be partially thin.

  When electrolytic plating is performed from such a state, as shown in FIG. 21, a phenomenon that the seed layer 76a is dissolved in the plating solution 77 to form an unformed region (dissolved portion) 300 is likely to occur. Even if the unformed region 300 is not formed, a phenomenon may occur in which the seed layer 76a is thinned by dissolution in the plating solution 77 and adhesion with the barrier metal layer 75 is reduced.

  Electroplating proceeds even when the seed layer 76a is dissolved in the plating solution 77, and it is possible to obtain a state in which the plating layer 76b is sufficiently embedded in the wiring groove 74 as shown in FIG. However, after that, when exposed to a heat treatment atmosphere, as shown in FIG. 23, when a void 301 is generated starting from an unformed region 300 of the seed layer 76a or a portion having a weak adhesion to the barrier metal layer 75. There is. In this case, after CMP, a defective wiring 76 in which the void 301 remains is formed.

  The generation of the void 301 can also occur in the same manner not only by the heat treatment at the time of forming the wiring 76 but also by the heat treatment in another process after the formation of the wiring 76 (heat at the time of forming an upper insulating film). .

  Therefore, the following formation method of the seed layer 76a is adopted, and even if the bowing 72a is generated in the interlayer insulating film 72, the unformed region due to the dissolution of the seed layer 76a in the plating solution 77 is used. Generation | occurrence | production of 300 etc. are suppressed and generation | occurrence | production of the void 301 is suppressed.

  25 is a schematic cross-sectional view of the main part of the wiring groove forming process, FIG. 26 is a schematic cross-sectional view of the main part in the initial stage of plating layer formation, FIG. 27 is a schematic cross-sectional view of the main part of the plating layer forming process, and FIG. FIG. 29 is a partial cross-sectional schematic diagram of the CMP process.

Here, as shown in FIG. 25, after the wiring groove 74 is formed, a Ta film or the like is first formed as the barrier metal layer 75 by sputtering. In that case, for example, sputtering is performed under conditions of a target power of 1.0 kW to 20 kW, a substrate bias power of 0 W to 300 W, and a pressure of 4 × 10 ⁻² Pa, and the film thickness of the field portion is about 3 nm to 20 nm. A barrier metal layer 75 is formed so as to be.

Next, a seed layer 76a is formed on the barrier metal layer 75 thus formed by sputtering. In that case, for example, sputtering is performed under the conditions of a target power of 2.0 kW to 5.0 kW, a substrate bias power of 50 W to 150 W, and a pressure of 1 × 10 ⁻⁵ Pa to 10 Pa to form the seed layer 76a. The seed layer 76a is formed, for example, so that the film thickness of the field portion is about 3 nm to 25 nm.

  Generally, in the sputtering method, for example, argon (Ar) is turned into plasma and collided with a target, and deposition components (Cu atoms, Cu ions, etc.) generated from the target collide with the substrate due to the collision, thereby depositing components on the substrate. Will be deposited. At this time, depending on the sputtering conditions, a phenomenon (resputtering) occurs in which the deposited component is etched by Ar ion collision or the like, along with deposition of the deposited component on the substrate.

  Here, when forming the seed layer 76a, conditions are used such that such resputtering occurs along with the deposition of the deposition component 76c. Then, while depositing the seed layer 76 a on the barrier metal layer 75, a part of the deposited component 76 c of the seed layer 76 a deposited on the bottom of the wiring groove 74 is re-sputtered to form the sidewall of the wiring groove 74. Try to deposit. As a result, the seed layer 76a is secured to a certain thickness or more on the side wall portion of the wiring groove 74 where the bowing 72a is generated and the film thickness of the seed layer 76a is easily reduced. The details of the method for forming the seed layer 76a using such a sputtering method will be described later.

  By setting the film thickness of the seed layer 76a on the side wall portion of the wiring groove 74 to a certain value or more, as shown in FIG. The dissolution of 76a in the plating solution 77 is suppressed.

  In this way, by setting the film thickness of the seed layer 76a to a certain value or more and suppressing dissolution during electroplating that causes an unformed region or the like, the plating layer 76b becomes a wiring groove as shown in FIG. It is fully embedded in 74. Even if heat treatment is performed after the formation of the plating layer 76b, generation of voids is effectively suppressed as shown in FIG. 28, and good wiring without voids is also obtained after CMP as shown in FIG. 76 is obtained.

The degree of bowing 72a of the interlayer insulating film 72 can be evaluated by the following values. FIG. 30 is an explanatory view of the bowing of the interlayer insulating film.
For example, as shown in FIG. 30, a state is assumed after the barrier metal layer 75 is formed and before the seed layer 76a is formed. Here, the height from the part where the bulging to the side of the wiring groove 74 in the state where the barrier metal layer 75 is formed to the part where the bulging ends is h, and the part where the bulging starts (or the bulging is Let w be the width from the end portion) to the largest swollen portion. In this case, the value obtained by the following equation (2) is set as the bowing rate indicating the degree of the bowing 72a.

Boeing rate (%) = w / h × 100 (2)
The larger the bowing rate, the larger the degree of swelling, that is, the degree of the bowing 72a.

  Here, h and w are defined before the formation of the seed layer 76a (immediately before the formation of the plating layer 76b), but for example, h and w are similarly defined before the formation of the barrier metal layer 75. The Boeing rate may be obtained.

Next, a method for forming the seed layer 76a will be described in more detail.
Here, the seed layer 76a is formed by a bias sputtering method under such a condition that a part of the seed layer 76a deposited on the bottom of the wiring groove 74 is deposited on the side wall of the wiring groove 74 by resputtering. Therefore, first, the film thickness of the seed layer 76a obtained when the seed layer 76a is formed by the bias sputtering method and the film thickness of the seed layer 76a obtained when the seed layer 76a is formed by the non-bias sputtering method. Describe the differences.

  FIGS. 31A and 31B are diagrams for explaining the difference in the thickness of the seed layer by the sputtering method. FIG. 31A is an explanatory diagram when the non-bias sputtering method is used, and FIG. 31B is the case when the bias sputtering method is used. It is explanatory drawing of.

  When the seed layer 76a is formed by the non-bias sputtering method, as shown in FIG. 31A, the field layer is relatively thick and the side wall of the wiring groove 74 is relatively thin. It is formed. On the other hand, when the seed layer 76a is formed by bias sputtering, the seed layer 76a is relatively thin in the field portion and relatively thick in the side wall portion of the wiring groove 74 as shown in FIG. Is formed.

  In the bias sputtering method, compared to the non-bias sputtering method, the deposition components 76c and Ar ions are strongly accelerated by the bias, and re-sputtering of the seed layer 76a after deposition appears strongly. In the non-bias sputtering method, such resputtering is suppressed, and the deposition of the seed layer 76a is dominant. Due to such a re-sputtering effect, the bias sputtering method has a thinner film thickness of the seed layer 76a in the field portion than the non-bias sputtering method.

  In the case of the bias sputtering method, a part of the deposited component 76c of the resputtered seed layer 76a at the bottom of the wiring groove 74 is formed on the side wall portion of the wiring groove 74 that becomes thin by the non-bias sputtering method. accumulate. Therefore, in the bias sputtering method, the thickness of the seed layer 76a on the side wall portion of the wiring groove 74 is thicker than that in the non-bias sputtering method.

  The difference in film thickness in the field portion between the seed layer 76a formed by the non-bias sputtering method and the seed layer 76a formed by the bias sputtering method is defined as an etching amount Δd.

  FIG. 32 is a diagram showing an example of the relationship between the etching amount and the seed layer thickness on the side wall of the wiring trench. Here, an example of the relationship between the etching amount Δd and the film thickness of the seed layer 76a in the side wall portion of the wiring groove 74 obtained for a sample having a bowing rate of about 7% to 9% in the above formula (2). Show.

  As described above, when the seed layer 76a is formed by the bias sputtering method under the condition that resputtering occurs, the etching amount Δd in the field portion is smaller than that when the seed layer 76a is formed by the non-bias sputtering method. Arise. As shown in FIG. 32, as the etching amount Δd increases, the seed layer 76a on the side wall of the wiring groove 74 tends to increase in thickness.

  Thus, by forming the seed layer 76a by the bias sputtering method, the film thickness of the seed layer 76a on the side wall portion of the wiring groove 74 can be increased. Further, it can be said that the film thickness of the seed layer 76a in the side wall portion of the wiring groove 74 can be controlled by the etching amount Δd in the field portion.

  When the seed layer 76a is formed by bias sputtering, the ratio D / E between the deposition rate (formation rate) D of the seed layer 76a in the field portion and the etching rate (removal rate) E by resputtering is 2. It is preferable to set in the range of 0-5.0.

  In the case of the non-bias sputtering method, the ratio D / E is usually in a range exceeding 5.0. In the range where the ratio D / E exceeds 5.0, the deposition of the seed layer 76a becomes dominant, and a part of the seed layer 76a deposited on the bottom of the wiring groove 74 is re-sputtered to form the sidewall portion of the wiring groove 74. It is difficult to deposit the film with a certain thickness.

  In the range where the ratio D / E is less than 2.0, the seed layer 76a deposited in the wiring groove 74, particularly the seed layer 76a deposited at the bottom of the wiring groove 74 is thinned by resputtering and is not formed. There is a high possibility that the seed layer 76a is dissolved to cause a region or the like. When the ratio D / E is 1.0, the deposition of the seed layer 76a and the resputtering are balanced. However, when the seed layer 76a is formed, the bias sputtering is only performed under this condition. It is difficult to form the seed layer 76a on the entire bottom and side walls of the wiring trench 74.

  As described above, by setting the ratio D / E in the range of 2.0 to 5.0, deposition is performed on the bottom of the wiring groove 74, or on the bottom of the wiring groove 74 while performing deposition on the bottom and side walls. A part of the seed layer 76a thus deposited can be deposited on the side wall by resputtering. Thereby, a seed layer 76a having a constant film thickness can be formed on the entire bottom and side walls of the wiring trench 74.

  The film thickness of the seed layer 76a to be formed may be set within a range in which dissolution of the seed layer 76a in which the seed layer 76a is not formed, which causes generation of voids, or dissolution in the plating solution 77 that causes a decrease in adhesion force can be avoided. Next, the results of investigating the film thickness of the seed layer 76a will be described.

First, a method for evaluating the degree of dissolution of the seed layer 76a in the plating solution 77 will be described. Here, a sample having a bowing rate of the above formula (2) of about 7% to 9% is used.
FIGS. 33A and 33B are explanatory views of a method for evaluating the degree of dissolution of the seed layer, wherein FIG. 33A is a schematic cross-sectional view of a wiring groove, and FIG. 33B is a partially enlarged view of a wiring groove side wall.

  In evaluating the degree of dissolution of the seed layer 76a, after forming the wiring trench 74 and the barrier metal layer 75, the sample on which the seed layer 76a is formed is immersed in the plating solution 77 for a very short time. Thereafter, a cross-section observation using SEM of the wiring groove 74 of the sample is performed, and in a predetermined region 74 a of the cross section, a side wall portion of the wiring groove 74 and a dissolved portion in which the seed layer 76 a is dissolved by immersion in the plating solution 77 ( The ratio of the area to the (unformed region) 300 is obtained, and the seed layer dissolution rate is obtained from the following equation (3).

Seed layer dissolution rate (%) = area of seed layer dissolved portion / area of wiring trench side wall portion × 100 (3)
The seed layer 76a is formed under various conditions, and such seed layer dissolution rate is obtained for a plurality of samples having different etching amounts Δd (film thickness of the seed layer 76a in the side wall portion of the wiring groove 74).

FIG. 34 is a diagram showing an example of the relationship between the etching amount and the seed layer dissolution rate.
As shown in FIG. 34, the seed layer dissolution rate can be kept lower as the etching amount Δd is increased. For example, when the etching amount Δd is 23 nm or more, the seed layer dissolution rate can be suppressed to 5% or less.

  When the etching amount Δd is 23 nm or more, according to the knowledge shown in FIG. 32, the film thickness of the seed layer 76a in the side wall portion of the wiring groove 74 is 10 nm or more. In other words, if the seed layer 76a is formed so that the film thickness at the side wall portion of the wiring groove 74 is 10 nm or more by controlling the etching amount Δd, the seed layer dissolution rate in the plating solution 77 during electroplating is lowered. It can be said that it becomes possible to suppress.

FIG. 35 is a diagram showing an example of the relationship between the seed layer dissolution rate and the number of voids generated.
In FIG. 35, first, from the formation of the plating layer 76b to the CMP when the seed layer dissolution rate is 33.0%, the etching amount Δd is 3 nm, and the film thickness of the seed layer 76a on the side wall of the wiring groove 74 is 5 nm. It shows the number of voids generated in the sample when performed. Further, in FIG. 35, when the seed layer dissolution rate is 0%, the etching amount Δd is 23 nm, and the thickness of the seed layer 76a on the side wall of the wiring groove 74 is 10 nm, the formation from the plating layer 76b to the CMP is performed. The number of voids generated in the sample is shown.

  As shown in FIG. 35, when the thickness of the sidewall of the wiring groove 74 of the seed layer 76a is formed as thick as 10 nm, the seed layer dissolution rate is higher than that when formed as thin as 5 nm. The number of voids can be greatly reduced by keeping it low.

  Similarly, by suppressing the seed layer dissolution rate to 5% or less, it is possible to significantly reduce the number of voids generated, and by setting the film thickness in the side wall portion of the wiring groove 74 of the seed layer 76a to 10 nm or more, Similarly, the generation of voids can be effectively suppressed.

  In addition, it is preferable to set the film thickness in the side wall part of the wiring groove | channel 74 of the seed layer 76a so that it may be 15 nm or less. If the film thickness is greater than 15 nm, it depends on the opening width of the original wiring groove 74, but the opening is narrowed before the plating layer 76 b is sufficiently embedded in the wiring groove 74 during electrolytic plating. This is because the possibility of occurrence of a phenomenon such as blocking and generation of voids increases. In particular, when a minute wiring groove 74 having an opening width of 50 nm to 70 nm is formed, such a phenomenon is likely to occur. The upper limit value of the film thickness at the side wall portion of the wiring groove 74 of the seed layer 76a is preferably set in consideration of the opening width of the wiring groove 74 and the possibility of voids resulting therefrom.

  As described above, in the second embodiment, the sputtering conditions for forming the seed layer are adjusted, and deposition is performed on the bottom of the wiring groove while performing deposition on the bottom of the wiring groove, or on the bottom and side walls. A portion of the seed layer is deposited on the sidewalls by resputtering. As a result, a seed layer having a constant film thickness can be formed on the entire bottom and side walls of the wiring trench, and the dissolution of the seed layer in the plating solution that causes a decrease in the non-formed region and adhesion force is suppressed. Will be able to. As a result, it is possible to form a wiring layer that effectively suppresses the generation of voids and suppresses deterioration of electrical characteristics, shortening of life, signal delay, and the like, and a high-performance and highly reliable semiconductor device can be realized.

  In the second embodiment, the case where the wiring is formed has been described as an example. However, the above method can be similarly applied to the case where the via is formed. The width of the wiring and the diameter of the via to which the above method can be applied are not particularly limited. For example, the present invention can be applied to a pattern with a relatively small opening size such as a wiring formed from a wiring groove having an opening width of 50 nm to 70 nm and a via formed from a via hole having an opening diameter of 50 nm to 70 nm.

  Further, in the second embodiment, the case where the wiring is formed by the single damascene method has been described as an example, but the present invention can be similarly applied to the case where the wiring and the via are simultaneously formed by using the dual damascene method. .

In the second embodiment, as described in the first embodiment, the seed containing Cu and Mn is formed without forming the barrier metal layer or after forming the barrier metal layer. A layer may be formed. In this case, the method as described in the second embodiment can be used to form such a seed layer containing Cu and Mn. By forming the seed layer containing Cu and Mn, a barrier layer such as MnSi _x O _y is formed in a self-aligned manner at the interface with the wiring groove or the barrier metal layer by heat treatment.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Additional remark 1) The process of forming the recessed part of opening dimension 50nm or more and 70nm or less in an insulating layer,
Forming a first metal layer above the inner wall of the recess and the insulating layer so that the opening size of the recess after the formation of the first metal layer is 20 nm or more;
Forming a second metal layer filling the recess on the first metal layer;
A method for manufacturing a semiconductor device, comprising:

  (Supplementary Note 2) The first metal layer is formed so that the opening size of the recess after forming the first metal layer is 20 nm or more and 65% or less of the opening size of the recess formed in the insulating layer. The method of manufacturing a semiconductor device according to appendix 1, wherein:

(Additional remark 3) Before forming the said 1st metal layer, it further includes the process of leaving an opening in the said recessed part on the said insulating layer containing the inside of the said recessed part, and forming a barrier layer,
Forming the first metal layer on the barrier layer;
3. The method of manufacturing a semiconductor device according to appendix 1 or 2, wherein the first metal layer is formed so that an opening size of the recess after forming the barrier layer and the first metal layer is 20 nm or more.

  (Additional remark 4) When forming the said recessed part with an opening dimension of 70 nm in the said insulating layer, the said barrier layer is formed so that the opening dimension of the said recessed part after formation of the said barrier layer and before the said 1st metal layer formation may be 50 nm or more. The method of manufacturing a semiconductor device according to attachment 3, wherein the method is formed.

(Supplementary Note 5) The first metal layer includes a plurality of elements.
The method further includes a step of performing a heat treatment for diffusing a predetermined element of the plurality of types of elements included in the first metal layer to an interface with another layer adjacent to the first metal layer. 5. A method for manufacturing a semiconductor device according to any one of 1 to 4.

(Additional remark 6) The said 1st metal layer contains Cu and Mn, The manufacturing method of the semiconductor device of Additional remark 5 characterized by the above-mentioned.
(Supplementary Note 7) The first metal layer is formed by a sputtering method, a PVD method, a CVD method, or an ALD method,
The method for manufacturing a semiconductor device according to any one of appendices 1 to 6, wherein the second metal layer is formed by an electrolytic plating method using the first metal layer.

(Appendix 8) Forming the first metal layer by a bias sputtering method,
The method for manufacturing a semiconductor device according to any one of appendices 1 to 7, wherein the second metal layer is formed by an electrolytic plating method using the first metal layer.

(Additional remark 9) The process of forming the recessed part which has a bow shape in an insulating layer,
Forming a first metal layer above the insulating layer including the inside of the recess, the film thickness of the side wall of the recess being 10 nm or more, and leaving an opening in the recess;
Forming a second metal layer filling the recess on the first metal layer;
A method for manufacturing a semiconductor device, comprising:

(Additional remark 10) The manufacturing method of the semiconductor device of Additional remark 9 characterized by forming the said 1st metal layer whose film thickness in the side wall part of the said recessed part is 10 nm or more and 15 nm or less.
(Additional remark 11) When forming the said 1st metal layer, using the sputtering method, forming the said 1st metal layer in the bottom part of the said recessed part, the said 1st metal layer formed in the bottom part of the said recessed part 11. The method of manufacturing a semiconductor device according to appendix 9 or 10, wherein a part of the semiconductor device is removed and attached to the side wall of the recess.

  (Additional remark 12) When forming the said 1st metal layer, ratio of the formation rate of the said 1st metal layer with respect to the removal rate of the formed said 1st metal layer is 2.0 or more and 5.0 or less A method for manufacturing a semiconductor device according to appendix 11, wherein:

(Appendix 13) Forming the first metal layer by bias sputtering,
13. The method of manufacturing a semiconductor device according to any one of appendices 9 to 12, wherein the second metal layer is formed by an electrolytic plating method using the first metal layer.

  (Additional remark 14) The said insulating layer is formed using the low dielectric constant material, The manufacturing method of the semiconductor device in any one of Additional remark 9 thru | or 13 characterized by the above-mentioned.

It is a partial cross section schematic diagram of an example of a semiconductor device. It is a principal part cross-sectional schematic diagram of a via-hole formation process. It is a principal part cross-sectional schematic diagram of a barrier metal layer formation process. It is a principal part cross-sectional schematic diagram of a seed layer formation process. It is a principal part cross-sectional schematic diagram of an example after plating layer formation. It is a principal part cross-sectional schematic diagram of another example after plating layer formation. It is a principal part cross-sectional schematic diagram of the via-hole formation process of 1st Example. It is a principal part cross-sectional schematic diagram of the barrier metal layer formation process of 1st Example. It is a principal part cross-sectional schematic diagram of the seed layer formation process of 1st Example. It is a principal part cross-sectional schematic diagram of the plating layer formation process of 1st Example. It is a principal part cross-sectional schematic diagram of the CMP process of 1st Example. It is a principal part cross-sectional schematic diagram of the seed layer formation process of 2nd Example. It is a principal part cross-sectional schematic diagram of the plating layer formation process of 2nd Example. It is a principal part cross-sectional schematic diagram of the heat processing process of 2nd Example. It is a principal part cross-sectional schematic diagram of the CMP process of 2nd Example. It is a principal part cross-sectional schematic diagram of the seed layer formation process of 3rd Example. It is a principal part cross-sectional schematic diagram of the plating layer formation process of 3rd Example. It is a principal part cross-sectional schematic diagram of the heat processing process of 3rd Example. It is explanatory drawing of the formation state of the barrier layer in a via-hole side wall part. It is a figure which shows an example of the state after barrier metal layer and seed layer formation. It is a figure which shows an example of a plating layer formation initial stage. It is a figure which shows an example of the state after plating layer formation. It is a figure which shows an example of the state after heat processing. It is a figure which shows an example of the state after CMP. It is a principal part cross-sectional schematic diagram of a wiring groove | channel formation process. It is a principal part cross-sectional schematic diagram of the plating layer formation initial stage. It is a principal part cross-sectional schematic diagram of a plating layer formation process. It is a principal part cross-sectional schematic diagram of a heat processing process. It is a principal part cross-sectional schematic diagram of a CMP process. It is explanatory drawing of the bowing of an interlayer insulation film. It is a figure explaining the difference in the film thickness of the seed layer by sputtering method, (A) is explanatory drawing at the time of using a non-bias sputtering method, (B) is explanatory drawing at the time of using a bias sputtering method. It is. It is a figure which shows an example of the relationship between the etching amount and the seed layer film thickness of a wiring groove side wall part. It is explanatory drawing of the method of evaluating the grade of melt | dissolution of a seed layer, Comprising: (A) is a cross-sectional schematic diagram of a wiring groove | channel, (B) is the elements on larger scale of a wiring groove side wall part. It is a figure which shows an example of the relationship between an etching amount and a seed layer dissolution rate. It is a figure which shows an example of the relationship between a seed layer melt | dissolution rate and the number of void generation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Element isolation insulating film 4 MOS transistor 4a Gate insulating film 4b Gate electrode 4c Side wall insulating film 4d, 4e Source / drain region 5, 6, 7, 76 Wiring 8, 46 Via 9, 9, 16, 19, 42, 72 Interlayer insulating film 10, 11 Conductive plug 13, 14, 17, 20, 34, 45, 75 Barrier metal layer 15, 18, 31, 41, 71 Cap layer 30 Lower layer wiring 32 Insulating layer 33, 44 Via hole 35a, 46a, 46c, 76a Seed layer 35b, 46b, 76b Plating layer 40 Lower layer wiring 43, 73 Hard mask 45a Altered barrier metal layer 50 Barrier layer 70 TEOS film 72a Boeing 73a SiC film 73b SiO film 74 Wiring groove 74a Predetermined region 76c Deposited component 77 Plating solution 100, 104, 01 void 101a, 101b overhang 102,200,300 free area 103 ultrathin region h Height w width W, W1, W2, W3 opening diameter W3 minimum diameter Δd-etching

Claims (8)

Forming a recess having an opening size of 50 nm to 70 nm in the insulating layer;
Forming a first metal layer above the inner wall of the recess and the insulating layer so that the opening size of the recess after the formation of the first metal layer is 20 nm or more;
Forming a second metal layer filling the recess on the first metal layer;
A method for manufacturing a semiconductor device, comprising: Before forming the first metal layer, further comprising a step of forming a barrier layer on the insulating layer including the inside of the recess, leaving an opening in the recess.
Forming the first metal layer on the barrier layer;
2. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal layer is formed so that an opening size of the recess after forming the barrier layer and the first metal layer is 20 nm or more.   When forming the concave portion having an opening size of 70 nm in the insulating layer, forming the barrier layer so that the opening size of the concave portion after forming the barrier layer and before forming the first metal layer is 50 nm or more. The method of manufacturing a semiconductor device according to claim 2, wherein: The first metal layer includes a plurality of types of elements,
The method further includes a step of performing a heat treatment for diffusing a predetermined element among the plurality of types of elements included in the first metal layer to an interface with another layer adjacent to the first metal layer. Item 4. A method for manufacturing a semiconductor device according to any one of Items 1 to 3. Forming the first metal layer by sputtering, PVD, CVD, or ALD;
5. The method of manufacturing a semiconductor device according to claim 1, wherein the second metal layer is formed by an electrolytic plating method using the first metal layer. 6. Forming a recess having a bowing shape in the insulating layer;
Forming a first metal layer above the insulating layer including the inside of the recess, the film thickness of the side wall of the recess being 10 nm or more, and leaving an opening in the recess;
Forming a second metal layer filling the recess on the first metal layer;
A method for manufacturing a semiconductor device, comprising:   When forming the first metal layer, a part of the first metal layer formed at the bottom of the recess is removed while forming the first metal layer at the bottom of the recess using a sputtering method. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is attached to the side wall of the recess.   When forming the first metal layer, the ratio of the formation rate of the first metal layer to the removal rate of the formed first metal layer is set to 2.0 or more and 5.0 or less. A method for manufacturing a semiconductor device according to claim 7.

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