JP2006073792A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve wiring reliability by improvement in SIV resistance, improvement in interface adhesive strength, etc., by forming a titanium-aluminum alloy layer between a barrier layer and a copper layer wherein a recess composed of a wiring groove and a connection hole is buried. <P>SOLUTION: A semiconductor device 1 is disclosed having a conductive layer 16 buried in the recess 12 formed in an insulating film 11. The conductive layer 16 comprises the barrier layer 13 formed on the internal surface of the recess 12, the titanium-aluminum alloy layer 14 formed on the top surface of the barrier layer 13, and the copper layer 15 in which the recess 12 is buried and wherein aluminum is solved. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which fine groove wiring and contacts can be easily formed, and a method for manufacturing the semiconductor device.

  Conventionally, aluminum or an aluminum alloy has been used as a metal material for forming a wiring circuit on a semiconductor substrate. However, in recent years, the direction has been changed to using copper. The reason for this is that the electrical resistivity of copper is 1.72 μΩcm, which is about 40% lower than that of aluminum, the electromigration resistance is much higher than that of aluminum, and more than that of aluminum. Since it is easy to adopt a multilayer groove wiring process (for example, dual damascene process), a complicated and fine multilayer wiring structure can be processed relatively inexpensively. A typical method for embedding copper by the dual damascene method is to form copper or a copper alloy as a plating seed layer by sputtering, and to embed copper by a plating method. The main purpose of the seed layer is to supply a current sufficient to reduce the metal ions in the liquid and deposit them as metal solids using the surface of the seed layer as an electrical cathode.

  Along with the miniaturization of wiring due to miniaturization of semiconductor devices, as the aspect ratio of trenches, trenches, contacts, and connection holes (via holes) of the wiring to be buried increases, the recesses (trench, hole) by the conventional sputtering method become higher. It is becoming difficult to form a sufficient continuous seed layer in (1). At present, in order to ensure the coverage (coverage) of the film in such a recess, compared to the conventional sputtering method, there are long-distance sputtering method, collimation sputtering method, ionization sputtering method and the like. Developed and widely used.

  On the other hand, in order to improve the reliability of copper wiring, it has been studied to add a small amount of impurities (Al, Ag, Zr, Mg, B, etc.) to copper (for example, Patent Documents 1, 2, and 3). reference.).

  However, in future semiconductor miniaturization and device rules of 65 nm, 45 nm, and 45 nm or less, sufficient seed layer coverage cannot be obtained in the recess even by the directional sputtering method mentioned above. Then, the filling in the plating of the next process is not achieved. Also, if sufficient coverage is to be obtained, the opening of the recess is narrowed or blocked by the seed layer, making it difficult to fill the recess by plating. As a method of adding impurities to the Cu wiring for the purpose of improving reliability, a Cu alloy sputter target to which impurities are added is prepared, and the impurities are added to the Cu seed layer formed by sputtering. Although it is the easiest and most common, if it is difficult to form a seed by conventional sputtering in the future, other methods may be considered for adding impurities to Cu.

Japanese Patent Laid-Open No. 11-54458 JP-A-11-102909 JP 2000-252278 A

  The problem to be solved is that it is difficult to form a seed layer that can provide sufficient coverage with respect to the recesses (for example, trench wiring and connection holes) of device rules of 65 nm, 45 nm, and 45 nm or less. In addition, it is difficult to add impurities into the copper seed layer for the purpose of improving the reliability of the copper wiring by the conventional film forming method.

  The semiconductor device of the present invention is a semiconductor device having a conductive layer embedded in a recess formed in an insulating film, the conductive layer being formed on a barrier layer formed on the inner surface of the recess and on the surface of the barrier layer. The main feature is that it is formed of a titanium aluminum alloy layer formed and a copper layer in which the recess is embedded and in which aluminum is dissolved.

  The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a step of embedding a conductive layer in a recess formed in an insulating film, wherein the step of forming the conductive layer includes a barrier layer on the inner surface of the recess. Forming a plating seed layer made of aluminum on the surface of the barrier layer, filling the recess with copper, and removing excess copper, aluminum and the barrier layer on the insulating film, The main feature is that it has

  The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a step of embedding a conductive layer in a recess formed in an insulating film, wherein the step of forming the conductive layer includes a barrier layer on the inner surface of the recess. A step of forming a titanium layer on the surface of the barrier layer, a step of forming a plating seed layer made of aluminum on the surface of the titanium layer, a step of filling the recess with copper, and a step on the insulating film And a step of removing excess copper, aluminum, and a barrier layer.

  In the semiconductor device of the present invention, since the titanium aluminum alloy layer is formed between the barrier layer and the copper layer, the interfacial adhesion between the copper layer and the barrier layer can be improved, so that the SIV (Stress-Induced Voiding) resistance is achieved. There is an advantage that the reliability of wiring and the like can be improved.

  In the method for manufacturing a semiconductor device of the present invention, a plating seed layer is formed using aluminum on the surface of the barrier layer, so that a CVD method or an ALD method can be employed as a film forming method. For this reason, since the plating seed layer can be formed in a conformal manner with good coverage on the inner surface of the recess, there is an advantage that it is possible to prevent a filling failure due to the occurrence of voids when copper is embedded in the recess thereafter. . Furthermore, since the aluminum alloy layer of the plating seed layer aluminum and the barrier layer is formed between the barrier layer and the copper layer, the interfacial adhesion between the copper and the barrier layer can be improved. -Induced voiding) The resistance can be improved, and the reliability of wiring and the like can be improved.

  In the method for manufacturing a semiconductor device of the present invention, a plating seed layer is formed using aluminum on the surface of the barrier layer, so that a CVD method or an ALD method can be employed as a film forming method. For this reason, since the plating seed layer can be formed in a conformal manner with good coverage on the inner surface of the recess, there is an advantage that it is possible to prevent a filling failure due to the occurrence of voids when copper is embedded in the recess thereafter. . Also, since the underlying titanium layer was formed before forming the plating seed layer made of aluminum, the diffusion of aluminum into copper was controlled by the titanium layer so that excess aluminum did not diffuse into copper. Therefore, there is an advantage that an increase in electrical resistance of copper can be suppressed. Furthermore, since a titanium aluminum alloy layer is formed between the barrier layer and the copper layer, the interface adhesion between the copper and the barrier layer can be improved, so that the SIV (Stress-Induced voiding) resistance is improved. There is an advantage that the reliability of wiring and the like can be improved.

  By using aluminum for the plating seed layer and further providing a titanium layer between the barrier layer and the plating seed layer, the purpose of improving reliability by improving SIV resistance, interfacial adhesion, etc. Realized without using a process.

  A first embodiment of the semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG.

  As shown in FIG. 1, for example, semiconductor elements, wirings, and the like are formed on a substrate (not shown) (for example, a semiconductor substrate, an insulating substrate, etc.), and an insulating film 11 covering them is formed. A concave portion (for example, a wiring groove or a connection hole) 12 is formed in the insulating film 11. Although not shown, the recess 12 may be a wiring groove formed by a so-called dual damascene method and a connection hole formed in the wiring groove. A barrier layer 13 is formed on the inner surface of the recess 12. The barrier layer 13 is made of, for example, tantalum, tungsten, tantalum nitride, tungsten nitride, tungsten nitride silicide, or titanium nitride. Or it is good also as a laminated film which combined the said 2 or more types of film | membrane.

  A titanium aluminum alloy layer 14 is formed on the surface of the barrier layer 13. Further, a copper layer 15 is formed so as to fill the recess 12. As described above, the conductive layer 16 composed of the copper layer 15 with the barrier layer 13 and the titanium aluminum alloy layer 14 interposed therebetween is formed in the recess 12. Further, a protective film (not shown) for preventing copper oxidation and copper diffusion may be formed on the surface of the copper layer 15.

  In the semiconductor device 1, since the titanium aluminum alloy layer 14 is formed between the barrier layer 13 and the copper 15, the interface adhesion between the copper 15 and the barrier layer 13 can be improved, so that SIV (Stress-Induced voiding). ) It is possible to improve the durability, and there is an advantage that the reliability of the wiring and the like can be improved.

  Next, a first embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional views of FIGS.

  As shown in FIG. 2A, for example, semiconductor elements, wirings, and the like are formed on a substrate (not shown) (for example, a semiconductor substrate, an insulating substrate, etc.), and a first insulating film 21 covering them is formed. In the first insulating film 21, a first wiring 24 is formed in the wiring groove 22 through a barrier layer 23. A protective layer 25 is formed on the first insulating film 21 so as to cover the trench wiring 24. The protective layer 25 is made of, for example, silicon nitride.

  A second insulating film 31 is formed on the ground with the above configuration, that is, on the protective layer 25. The second insulating film 31 is made of, for example, silicon oxide and has a thickness of 0.3 μm. Next, recesses (for example, wiring grooves and connection holes) 32 are formed in the second insulating film 31 by a normal lithography technique, an etching technique, and the like. The connection hole portion of the recess 32 is formed so as to penetrate the protective layer 25 and reach the first wiring 24.

  Next, as shown in FIG. 2B, a barrier layer 33 is formed on the surface of the second insulating film 31 so as to cover the inner surface of the recess 32. The barrier layer 33 is formed of a material layer that prevents diffusion of copper having a thickness of about 5 nm to 15 nm by, for example, a PVD (Physical Vapor Deposition) method. For example, tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium nitride silicide (TiSiN), titanium nitride (TiN), or the like can be used as the material layer. Or it is good also as a laminated film which combined the said 2 or more types of film | membrane. For example, the titanium nitride layer and the titanium layer are sequentially laminated from the inner surface side of the recess 32, the titanium layer, the titanium nitride layer and the titanium layer are sequentially laminated, the tantalum layer and the titanium layer are sequentially laminated, A tantalum nitride layer and a titanium layer are sequentially stacked, a tantalum nitride layer, a tantalum layer and a titanium layer are sequentially stacked, a tungsten nitride layer and a titanium layer are sequentially stacked, a tungsten nitride silicide layer and a titanium layer Are laminated in order. As a method for forming the barrier layer 33, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or the like can be used in addition to the PVD method.

  Next, as shown in FIG. 2C, after the barrier layer 33 is formed, a plating seed layer 34 made of aluminum is formed in-situ without opening to the atmosphere. The plating seed layer 34 made of aluminum is preferably formed by a film forming method capable of forming a film conformally with a high coverage such as a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. The barrier layer 33 is formed with a film thickness of, for example, 5 nm or more and not embedding the recess 32.

  When the plating seed layer 34 is formed by a chemical vapor deposition method, MPA (methylpyrrolidine alane) is used as a reaction gas. Alternatively, DMAH (dimethylaluminum hydride), TMA (trimethylaluminum), DMEAA (dimethylethylamine alane), or the like can be used as the reaction gas. For example, the film forming conditions are such that the pressure of the film forming atmosphere is set to 30 Pa, the substrate temperature is set to 90 ° C. to 120 ° C., and the film thickness is, for example, 5 nm or more and the recessed portion 32 is not embedded.

  Next, as shown in FIG. 2 (4), a copper layer 35 is formed on the entire surface of the plating seed layer 34 so as to fill the recess 32 by electrolytic plating. The copper layer 35 is formed by being deposited to a thickness of 0.8 μm, for example.

  Next, as shown in FIG. 3 (5), after the copper layer 35 is formed, heat treatment is performed. This heat treatment is performed at a temperature of 350 ° C. to 400 ° C. for about 60 minutes, for example. By this heat treatment, a part of the aluminum in the plating seed layer 34 (see FIG. 2 (4)) is dissolved in the copper layer 35. An alloy layer 36 is formed by the plating seed layer 34 (see FIG. 2 (4)) and a part of the barrier layer 33, and copper and aluminum are formed at the interface between the alloy layer 36 and the copper layer 35. A ternary alloy layer (not shown) with the constituent elements of the barrier layer is formed. By forming these alloy layers, adhesion at the interface between the copper layer 35 and the barrier layer 33 is improved.

  Next, as shown in FIG. 3 (6), the excess copper layer 35, alloy layer 36, barrier layer 33, etc. on the second insulating film 31 (see FIG. 3 (5)) are subjected to chemical mechanical polishing (CMP). ) To remove. As a result, the second wiring 37 having a groove wiring structure made of the copper layer 35 in which aluminum is solid-solved via the barrier layer 33 and the alloy layer 36 is formed only inside the recess 32. Therefore, the surface of the second insulating film 31 is planarized. Next, although not shown, a protective layer 38 that covers the second wiring 37 is formed on the second insulating film 31. As the protective layer 38, a silicon nitride layer can be used as an example, similarly to the protective layer 25. Furthermore, when the wiring layer is multi-layered, the process described with reference to FIG. 3 may be repeated.

  In the method for manufacturing a semiconductor device of the present invention, the plating seed layer 34 is formed on the surface of the barrier layer 33 by using a film forming method such as a CVD method or an ALD method. Since the film can be formed conformally with a good coverage, there is an advantage that it is possible to prevent a defective filling due to the occurrence of voids when copper is buried in the recesses thereafter. Furthermore, since the alloy layer 36 is formed between the barrier layer 33 and the copper layer 35, the interface adhesion between the copper layer 35 and the barrier layer 33 can be improved, so that SIV (Stress-Induced voiding) resistance is achieved. There is an advantage that the reliability of wiring and the like can be improved.

  Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional views of FIGS.

  As shown in FIG. 4A, for example, semiconductor elements, wirings, and the like are formed on a substrate (not shown) (for example, a semiconductor substrate, an insulating substrate, etc.), and a first insulating film 21 is formed to cover them. In the first insulating film 21, a first wiring 24 is formed in the wiring groove 22 through a barrier layer 23. A protective layer 25 is formed on the first insulating film 21 so as to cover the first wiring 24. This protective layer 25 is formed of, for example, a silicon nitride layer.

  A second insulating film 41 is formed on the ground of the above configuration, that is, on the protective layer 25. The second insulating film 41 is made of, for example, silicon oxide and has a thickness of 0.3 μm. Next, recesses (for example, wiring grooves and connection holes) 42 are formed in the second insulating film 41 by a normal lithography technique, an etching technique, and the like. The connection hole portion of the recess 42 is formed so as to penetrate the protective layer 25 and reach the first wiring 24.

  Next, as illustrated in FIG. 4B, the barrier layer 43 is formed so as to cover the inner surface of the recess 42. The barrier layer 43 is formed of a material layer that prevents diffusion of copper having a thickness of about 5 nm to 15 nm by, for example, a PVD (Physical Vapor Deposition) method. For example, tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium nitride silicide (TiSiN), titanium nitride (TiN), or the like can be used as the material layer. Or it is good also as a laminated film which combined the said 2 or more types of film | membrane. For example, the titanium nitride layer and the titanium layer are sequentially laminated from the inner surface side of the recess 32, the titanium layer, the titanium nitride layer and the titanium layer are sequentially laminated, the tantalum layer and the titanium layer are sequentially laminated, A tantalum nitride layer and a titanium layer are sequentially stacked, a tantalum nitride layer, a tantalum layer and a titanium layer are sequentially stacked, a tungsten nitride layer and a titanium layer are sequentially stacked, a tungsten nitride silicide layer and a titanium layer Are laminated in order. As a method for forming the barrier layer 43, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or the like can be used in addition to the PVD method.

  Next, as shown in FIG. 4C, after forming the barrier layer 43, a titanium layer 44 is formed on the surface of the barrier layer 43 in-situ without opening to the atmosphere. The titanium layer 44 is preferably formed by a film forming method capable of forming a film conformally with a high coverage such as a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. The titanium layer 44 is formed with a film thickness of about 3 nm to 10 nm, for example. By the subsequent heat treatment, the titanium layer 44 forms an alloy with the upper aluminum layer. The amount of aluminum dissolved (diffused) in copper can be controlled by the thickness of the titanium layer 44. The specific resistance of the copper-aluminum alloy is increased by the amount of aluminum solid solution in copper, and as a result, the wiring resistance is increased. Therefore, excessive solid solution of aluminum in copper is not preferable. Therefore, as described above, the solid solution of aluminum in copper is controlled by allowing the titanium layer to absorb aluminum.

  Next, as shown in FIG. 4D, after the titanium layer 44 is formed, a plating seed layer 45 made of aluminum is formed on the surface of the titanium layer 44 in-situ without opening to the atmosphere. The plating seed layer 45 made of aluminum is preferably formed by a film forming method capable of forming a film conformally with a high coverage, such as a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. The aluminum layer is formed with a thickness of, for example, about 20 nm to 30 nm as a smooth continuous film by using the titanium layer 44 as a base.

  When the aluminum film is formed by a chemical vapor deposition method, MPA (methylpyrrolidine alane) is used as a reaction gas. Alternatively, DMAH (dimethylaluminum hydride), TMA (trimethylaluminum), DMEAA (dimethylethylamine alane), or the like can be used as the reaction gas. For example, the film forming conditions are such that the pressure of the film forming atmosphere is set to 30 Pa, the substrate temperature is set to 90 ° C. to 120 ° C., and the film thickness is, for example, 5 nm or more and the recessed portion 32 is not embedded.

  Next, as shown in FIG. 5 (5), a copper layer 46 is formed on the entire surface of the plating seed layer 45 so as to fill the recess 42 by electrolytic plating. For example, the copper layer 46 is deposited to a thickness of 0.8 μm.

  Next, as shown in FIG. 5 (6), after the copper layer 46 is formed, heat treatment is performed. This heat treatment is performed at a temperature of 350 ° C. to 400 ° C. for about 60 minutes, for example. By this heat treatment, a part of aluminum in the plating seed layer 45 and the titanium layer 44 [see FIG. 4 (4)] are alloyed to form an aluminum titanium alloy layer 47. A part of aluminum in the plating seed layer 45 is dissolved in the copper layer 46. A ternary alloy layer (not shown) of copper, aluminum, and titanium is formed at the interface between the alloy layer 47 and the copper layer 46. By forming these alloy layers, adhesion at the interface between the copper layer 46 and the barrier layer 43 is improved.

  Next, as shown in FIG. 5 (7), the excessive copper layer 46, alloy layer 47, barrier layer 43, and the like on the second insulating film 41 are removed by chemical mechanical polishing (CMP). As a result, the second wiring 48 having the groove wiring structure formed of the copper layer 46 in which aluminum is solid-solved is formed only in the recess 42 through the barrier layer 43, the alloy layer 47, etc. [see FIG. 5 (6)]. Is done. Therefore, the surface of the second insulating film 41 is planarized. Next, although not shown, a protective layer 49 that covers the second wiring 48 is formed on the second insulating film 41. As the protective layer 49, silicon nitride can be used as an example, similarly to the protective layer 49. Furthermore, when the wiring layer is multi-layered, the process described with reference to FIG. 5 may be repeated.

In the manufacturing method of the semiconductor device of the present invention, the plating seed layer 45 is formed on the surface of the titanium layer 44 by using a film forming method such as a CVD method or an ALD method. In particular, since the film can be formed conformally with good coverage, there is an advantage that it is possible to prevent a filling failure due to the occurrence of voids when copper is buried in the recesses thereafter. Furthermore, since the titanium layer 44 as a base is formed before the plating seed layer 45 made of aluminum is formed, the diffusion of aluminum into the copper layer 46 is controlled by the titanium layer 44, so that excess aluminum is contained in the copper layer 46. Therefore, there is an advantage that an increase in electrical resistance of the copper layer 46 can be suppressed. Furthermore, since the aluminum titanium alloy layer 47 is formed between the barrier layer 43 and the copper layer 46, the interface adhesion between the copper layer 46 and the barrier layer 43 can be improved, so that SIV (Stress Induce void) The resistance can be improved, and there is an advantage that the reliability of wiring and the like can be improved. Further, by adjusting the film thickness of the titanium layer 44, the amount of aluminum dissolved in the copper layer 46 is controlled by controlling the proportion of aluminum consumed in the reaction between titanium and aluminum (for example, Ti + 3Al → TiAl ₃ ). There is an advantage that an increase in the electrical resistance of the copper layer 46 can be suppressed by adjusting. This makes it possible to form fine wiring capable of high-speed signal transmission.

  Further, in each of the above manufacturing methods, it is possible to use a CVD method or an ALD method for film formation of aluminum of the plating seed layer 44. Therefore, with a further fine wiring structure (65 nm process, 45 nm process or lower process). Even if it exists, there exists an advantage that formation of the plating seed layer 44 of aluminum is attained.

  The semiconductor device and the method for manufacturing the semiconductor device according to the present invention can be applied to wiring of various semiconductor devices using a trench wiring, a plug formed in a connection hole, and the like, particularly a multilayer wiring.

1 is a schematic cross-sectional view showing a first embodiment of the semiconductor device of the present invention. It is manufacturing process sectional drawing which showed 1st Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 1st Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 2nd Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 2nd Example which concerns on the manufacturing method of the semiconductor device of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Insulating film, 12 ... Recessed part, 13 ... Barrier layer, 14 ... Titanium aluminum alloy layer, 15 ... Copper layer, 16 ... Conductive layer

Claims (16)

A semiconductor device having a conductive layer embedded in a recess formed in an insulating film,
The conductive layer is
A barrier layer formed on the inner surface of the recess;
A titanium aluminum alloy layer formed on the surface of the barrier layer;
A semiconductor device comprising: a copper layer in which the recess is embedded and in which aluminum is dissolved. The semiconductor device according to claim 1, wherein the recess includes a wiring groove, a connection hole, or a wiring groove and a connection hole communicated with the wiring groove. The semiconductor device according to claim 1, wherein the barrier layer is made of tantalum, tungsten, tantalum nitride, tungsten nitride, tungsten nitride silicide, or titanium nitride. A method for manufacturing a semiconductor device comprising a step of embedding a conductive layer in a recess formed in an insulating film,
The step of forming the conductive layer includes
Forming a barrier layer on the inner surface of the recess;
Forming a plating seed layer made of aluminum on the barrier layer surface;
Filling the recess with copper;
And a step of removing excess copper, aluminum, and the barrier layer on the insulating film. 5. The method of manufacturing a semiconductor device according to claim 4, wherein after forming the copper, a part of aluminum is reacted with a part of the barrier layer by heat treatment to form an alloy. The method of manufacturing a semiconductor device according to claim 4, wherein the recess includes a wiring groove, a connection hole, or a wiring groove and a connection hole communicated with the wiring groove. The method for manufacturing a semiconductor device according to claim 4, wherein the barrier layer is made of tantalum, tungsten, tantalum nitride, tungsten nitride, tungsten nitride silicide, or titanium nitride. The method for manufacturing a semiconductor device according to claim 4, wherein the barrier layer is formed by a directional sputtering method, a chemical vapor deposition method, or an atomic layer deposition method. The method for manufacturing a semiconductor device according to claim 4, wherein the plating seed layer made of aluminum is formed by chemical vapor deposition or atomic layer deposition. The method of manufacturing a semiconductor device according to claim 4, wherein the film forming process in each step is continuously performed without being exposed to the atmosphere. A method for manufacturing a semiconductor device comprising a step of embedding a conductive layer in a recess formed in an insulating film,
The step of forming the conductive layer includes
Forming a barrier layer on the inner surface of the recess;
Forming a titanium layer on the barrier layer surface;
Forming a plating seed layer made of aluminum on the surface of the titanium layer;
Filling the recess with copper;
And a step of removing excess copper, aluminum, and the barrier layer on the insulating film. The method for manufacturing a semiconductor device according to claim 11, wherein after forming the copper, a part of aluminum is reacted with Ti to be alloyed by heat treatment. The method for manufacturing a semiconductor device according to claim 11, wherein the barrier layer is made of tantalum, tungsten, tantalum nitride, tungsten nitride, tungsten nitride silicide, or titanium nitride. The method for manufacturing a semiconductor device according to claim 11, wherein the barrier layer is formed by a directional sputtering method, a chemical vapor deposition method, or an atomic layer deposition method. The method for manufacturing a semiconductor device according to claim 11, wherein the plating seed layer made of aluminum is formed by a chemical vapor deposition method or an atomic layer deposition method. The method of manufacturing a semiconductor device according to claim 11, wherein the film formation process in each step is continuously performed without being exposed to the atmosphere.

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