JP2008047719A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2008047719A
JP2008047719A JP2006222194A JP2006222194A JP2008047719A JP 2008047719 A JP2008047719 A JP 2008047719A JP 2006222194 A JP2006222194 A JP 2006222194A JP 2006222194 A JP2006222194 A JP 2006222194A JP 2008047719 A JP2008047719 A JP 2008047719A
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layer
conductive layer
film
plating
wiring
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Yoshiyuki Oba
義行 大庭
Toshihiko Hayashi
利彦 林
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Sony Corp
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Sony Corp
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Priority to JP2006222194A priority Critical patent/JP2008047719A/en
Priority to US11/832,931 priority patent/US20080173547A1/en
Priority to TW096128890A priority patent/TW200816379A/en
Priority to KR1020070080096A priority patent/KR20080016463A/en
Publication of JP2008047719A publication Critical patent/JP2008047719A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method capable of preventing the film of a conductor layer from peeling in a state where a load on a plating process is suppressed, raising embedding uniformity in the conductive layer in a substrate surface, and suppressing the increase of wiring resistance. <P>SOLUTION: In the semiconductor device manufacturing method; first, a process is performed, where a wiring groove 16 is formed in an inter-layer insulating film 15 arranged on a substrate 11, and secondly, a process is performed in a state to cover the inner wall of the wiring groove 16 for forming a plating seed layer 17 where an alloy layer 17a composed of a CuMn alloy and a conductive layer 17b composed of pure Cu are laminated in the order. Then, a process is performed where the conductive layer 18 composed of pure Cu is embedded in the wiring groove 16 with the plating seed layer 17 arranged therein by a plating method. Then, a process is performed where a heat treatment is performed, and Mn in the alloy layer 17a is reacted with the configuration components of the inter-layer insulating films 12, 15, and then, a self-formation barrier film 19 composed of an Mn compound with Cu diffusion barrier property is formed on an interface between the alloy layer 17a and the inter-layer insulating films 12, 15. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置の製造方法に関し、さらに詳しくは、配線またはヴィアと層間絶縁膜との間に自己形成バリア膜が設けられたダマシン構造を有する半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a damascene structure in which a self-formed barrier film is provided between a wiring or a via and an interlayer insulating film.

半導体装置の銅（Ｃｕ）配線形成プロセスにおいては、一般的に、層間絶縁膜に設けられた配線溝を埋め込むことで、配線パターンを形成するダマシン法が行われている。ダマシン法によるＣｕ配線の形成の際には、層間絶縁膜へのＣｕの拡散を防止するため、通常Ｃｕを埋め込む前に、配線溝の内壁を覆う状態で、タンタル(Ｔａ)、もしくはタンタル窒化膜(ＴａＮ)等のバリア膜を１０ｎｍ程度の膜厚で成膜する。その後、電解めっき法により、バリア膜が設けられた配線溝内にＣｕ層を埋め込む。   In a copper (Cu) wiring formation process of a semiconductor device, a damascene method for forming a wiring pattern by embedding wiring grooves provided in an interlayer insulating film is generally performed. When forming a Cu wiring by the damascene method, in order to prevent Cu from diffusing into the interlayer insulating film, the tantalum (Ta) or tantalum nitride film is usually covered with the inner wall of the wiring trench before embedding Cu. A barrier film such as (TaN) is formed to a thickness of about 10 nm. Thereafter, a Cu layer is embedded in the wiring trench provided with the barrier film by electrolytic plating.

しかし、配線ピッチの微細化に伴い、Ｃｕの埋め込み難易度が上がっていること、配線の総体積に占めるバリア膜の割合が増加し、配線抵抗が上昇していること等の理由により、バリア膜を成膜せずに、Ｍｎを含有したＣｕ層からなるシード層を形成し、その後の熱処理によりＭｎを拡散させて、層間絶縁膜とＣｕ配線との界面にＭｎ化合物からなる自己形成バリア膜を２〜３ｎｍ程度の膜厚で形成する技術が提案されている（例えば、非特許文献１参照）。   However, with the miniaturization of the wiring pitch, the difficulty of embedding Cu has increased, the ratio of the barrier film to the total wiring volume has increased, and the wiring resistance has increased. A seed layer made of a Cu layer containing Mn is formed without forming a film, and Mn is diffused by a subsequent heat treatment to form a self-formed barrier film made of a Mn compound at the interface between the interlayer insulating film and the Cu wiring. A technique for forming a film with a thickness of about 2 to 3 nm has been proposed (see Non-Patent Document 1, for example).

上記自己形成バリアプロセスについて、図７を用いて説明する。まず、図７（ａ）に示すように、シリコンウェハからなる基板１１上に、酸化シリコン（ＳｉＯ2）からなる層間絶縁膜１２を形成した後、この層間絶縁膜１２に基板１１に達する状態の接続孔１３を形成し、接続孔１３内に例えばタングステン（Ｗ）からなるヴィア１４を埋め込み形成する。 The self-forming barrier process will be described with reference to FIG. First, as shown in FIG. 7A, an interlayer insulating film 12 made of silicon oxide (SiO 2 ) is formed on a substrate 11 made of a silicon wafer, and then the interlayer insulating film 12 reaches the substrate 11. A connection hole 13 is formed, and a via 14 made of, for example, tungsten (W) is embedded in the connection hole 13.

次に、ヴィア１４上を含む層間絶縁膜１２上に、ＳｉＯ2からなる層間絶縁膜１５を形成する。次いで、層間絶縁膜１５に、層間絶縁膜１２およびヴィア１４に達する状態の配線溝１６を形成した後、配線溝１６の内壁を覆う状態で、層間絶縁膜１５上に、ＣｕＭｎ層からなるめっきシード層１７’を形成する。 Next, an interlayer insulating film 15 made of SiO 2 is formed on the interlayer insulating film 12 including the vias 14. Next, after forming a wiring groove 16 reaching the interlayer insulating film 12 and the via 14 in the interlayer insulating film 15, a plating seed made of a CuMn layer is formed on the interlayer insulating film 15 so as to cover the inner wall of the wiring groove 16. Layer 17 'is formed.

次いで、図７（ｂ）に示すように、電解めっき法により、配線溝１６を埋め込む状態で、めっきシード層１７’上に、純Ｃｕからなる導電層１８を形成する。   Next, as shown in FIG. 7B, a conductive layer 18 made of pure Cu is formed on the plating seed layer 17 ′ in a state where the wiring groove 16 is embedded by electrolytic plating.

次に、図７（ｃ）に示すように、熱処理を行い、めっきシード層１７’中に含まれるＭｎを層間絶縁膜１２、１５の構成成分と反応させて、めっきシード層１７’と層間絶縁膜１２、１５との界面に、Ｍｎ化合物からなる自己形成バリア膜１９を形成する。この自己形成バリア膜１９は、２ｎｍ〜３ｎｍの膜厚で形成される。この際、導電層１８の表面側にもＭｎが偏析し、酸化マンガン（ＭｎＯ）層Ｍが形成される。   Next, as shown in FIG. 7C, heat treatment is performed to cause Mn contained in the plating seed layer 17 ′ to react with the constituent components of the interlayer insulating films 12 and 15, so that the plating seed layer 17 ′ and the interlayer insulation are reacted. A self-forming barrier film 19 made of a Mn compound is formed at the interface with the films 12 and 15. The self-forming barrier film 19 is formed with a film thickness of 2 nm to 3 nm. At this time, Mn is segregated also on the surface side of the conductive layer 18, and a manganese oxide (MnO) layer M is formed.

その後、ここでの図示は省略したが、化学的機械的研磨(Chemical Mechanical Polishing（ＣＭＰ））法により、配線パターンとして不要な部分の導電層１８および自己形成バリア膜１９を除去し、露出された層間絶縁膜１５の表面側を削り込むことで、上記配線溝１６に配線を形成する。   Thereafter, although not shown in the figure, the conductive layer 18 and the self-formed barrier film 19 which are not necessary as a wiring pattern are removed and exposed by a chemical mechanical polishing (CMP) method. Wiring is formed in the wiring groove 16 by cutting the surface side of the interlayer insulating film 15.

上述したような製造方法により形成された配線構造においては、通常のＴａ、ＴａＮからなるバリア膜を用いた埋め込みプロセスに比べて、めっきシード層１７’中のＭｎと層間絶縁膜１２、１５の構成成分とを反応させて、薄膜化された自己形成バリア膜１９を形成するため、導電層１８の埋め込み特性に優れている。また、Ｔａ、ＴａＮからなるバリア膜と比較して自己形成バリア膜１９は膜厚が薄いため、配線の低抵抗化が図れる、という利点もある。   In the wiring structure formed by the manufacturing method as described above, the structure of Mn in the plating seed layer 17 ′ and the interlayer insulating films 12 and 15 is compared with the embedding process using the barrier film made of ordinary Ta and TaN. Since the thin film self-forming barrier film 19 is formed by reacting with the component, the embedding property of the conductive layer 18 is excellent. Further, since the self-formed barrier film 19 is thinner than a barrier film made of Ta or TaN, there is an advantage that the resistance of the wiring can be reduced.

Low Resistive and Highly Reliable Cu Dual-Damascene Interconnect Technology using Self-Formed MnSixOy Barrier Layer,「2005年 Symposium on VLSI Technology」p.188-190Low Resistive and Highly Reliable Cu Dual-Damascene Interconnect Technology using Self-Formed MnSixOy Barrier Layer, `` 2005 Symposium on VLSI Technology '' p.188-190

しかし、上述したような製造方法では、図７（ｃ）を用いて説明した工程において、めっきシード層１７’中のＭｎ濃度が十分でないと、図８に示すように、連続的な自己形成バリア膜１９が形成されず、熱処理の初期の段階における急激な応力変化により、導電層１８と層間絶縁膜１２、１５との密着性が低下することで、導電層１８の膜剥がれが生じてしまう。そして、これを防ぐためには、自己形成バリア膜１９の形成を促進させるために、めっきシード層１７’（前記図７（ｃ）参照）中のＭｎを高濃度化することが有効であるが、Ｍｎの抵抗値はＣｕよりも高いため、Ｍｎを高濃度化すると、めっきシード層１７’のシート抵抗が増大し、高電流をかける必要がある等、めっき工程への負荷が増大してしまう。このため、基板１１面内における導電層１８のメッキ成長が不均一となり、導電層１８の埋め込み均一性が低下する。また、めっきシード層１７’の表面側のＭｎはめっき液中に溶出し易く、めっき液中に溶出されたＭｎが導電層１８とともに配線溝１６内に埋め込まれることで、配線抵抗が増大する、という問題がある。   However, in the manufacturing method as described above, if the Mn concentration in the plating seed layer 17 ′ is not sufficient in the step described with reference to FIG. 7C, as shown in FIG. Since the film 19 is not formed and the adhesiveness between the conductive layer 18 and the interlayer insulating films 12 and 15 decreases due to a rapid stress change in the initial stage of the heat treatment, the conductive layer 18 is peeled off. In order to prevent this, it is effective to increase the concentration of Mn in the plating seed layer 17 ′ (see FIG. 7C) in order to promote the formation of the self-forming barrier film 19, Since the resistance value of Mn is higher than that of Cu, when the concentration of Mn is increased, the sheet resistance of the plating seed layer 17 ′ increases, and it is necessary to apply a high current, which increases the load on the plating process. For this reason, the plating growth of the conductive layer 18 in the surface of the substrate 11 becomes non-uniform, and the filling uniformity of the conductive layer 18 decreases. Further, Mn on the surface side of the plating seed layer 17 ′ is easily eluted in the plating solution, and the Mn eluted in the plating solution is embedded in the wiring groove 16 together with the conductive layer 18, thereby increasing the wiring resistance. There is a problem.

以上のことから、本発明は、めっき工程への負荷を抑制した状態で、導電層の膜剥がれを防止するとともに、基板面内における導電層の埋め込み均一性を向上し、配線抵抗の増大を抑制する半導体装置の製造方法を提供することを目的としている。   As described above, the present invention prevents the peeling of the conductive layer while suppressing the load on the plating process, improves the uniformity of the conductive layer in the substrate surface, and suppresses the increase in wiring resistance. An object of the present invention is to provide a method for manufacturing a semiconductor device.

上記目的を達成するために、本発明の半導体装置の製造方法は、次のような工程を順次行うことを特徴としている。まず、基板上に設けられた絶縁膜に凹部を形成する工程を行う。次に、凹部の内壁を覆う状態で、銅（Ｃｕ）とＣｕ以外の金属とからなる合金層と、Ｃｕを主成分とする導電層とを順次積層してなるめっきシード層を形成する工程を行う。次いで、めっき法により、めっきシード層が設けられた凹部に、Ｃｕを主成分とする導電層を埋め込む工程を行う。続いて、熱処理を行い、合金層中の金属を絶縁膜の構成成分と反応させて、合金層と絶縁膜との界面に、Ｃｕの拡散バリア性を有する金属化合物からなるバリア膜を形成する工程を行うことを特徴としている。   In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is characterized by sequentially performing the following steps. First, a step of forming a recess in an insulating film provided on the substrate is performed. Next, a step of forming a plating seed layer formed by sequentially laminating an alloy layer made of copper (Cu) and a metal other than Cu and a conductive layer containing Cu as a main component in a state of covering the inner wall of the recess. Do. Next, a step of embedding a conductive layer containing Cu as a main component in the recess provided with the plating seed layer is performed by plating. Subsequently, a heat treatment is performed to react a metal in the alloy layer with a component of the insulating film to form a barrier film made of a metal compound having a Cu diffusion barrier property at the interface between the alloy layer and the insulating film. It is characterized by performing.

このような半導体装置の製造方法によれば、合金層を構成するＣｕ以外の金属の抵抗値が高くても、合金層とＣｕを主成分とする導電層とを順次積層してなるめっきシード層を形成することから、合金層のみでめっきシード層を形成する場合と比較して、めっきシード層のシート抵抗が低くなる。このため、連続的なバリア膜が形成される程度に、合金層中の上記金属を高濃度化したとしても、めっきシード層のシート抵抗が抑制されるため、めっき工程の際に高電流をかけなくてもよく、めっき工程への負荷が抑制される。これにより、めっき工程への負荷を抑制した状態で、合金層中の上記金属を高濃度化して合金層と絶縁膜との界面に連続的なバリア膜を形成することができるため、導電層と絶縁膜との密着性が向上し、導電層の膜剥がれを防止することができる。また、めっきシード層のシート抵抗が低くなることで、基板面内における導電層のめっき成長が不均一になることが抑制され、導電層の埋め込み均一性が向上する。また、さらに、めっき工程を行う際に、めっきシード層の合金層がＣｕを主成分とする導電層で覆われていることから、めっき液中に合金層の表面側の上記金属が溶出することが防止される。これにより、めっき法により、凹部に導電層を埋め込む際に、めっき液中に溶出された金属が導電層とともに埋め込まれることによる、導電層の抵抗の増大が防止される。   According to such a method of manufacturing a semiconductor device, even if the resistance value of a metal other than Cu constituting the alloy layer is high, the plating seed layer is formed by sequentially laminating the alloy layer and a conductive layer mainly composed of Cu. Therefore, the sheet resistance of the plating seed layer is lower than that in the case where the plating seed layer is formed only by the alloy layer. For this reason, even if the concentration of the metal in the alloy layer is increased to such an extent that a continuous barrier film is formed, the sheet resistance of the plating seed layer is suppressed, so that a high current is applied during the plating process. There is no need, and the load on the plating process is suppressed. As a result, it is possible to form a continuous barrier film at the interface between the alloy layer and the insulating film by increasing the concentration of the metal in the alloy layer while suppressing the load on the plating process. Adhesiveness with the insulating film is improved and peeling of the conductive layer can be prevented. In addition, since the sheet resistance of the plating seed layer is reduced, the plating growth of the conductive layer in the substrate surface is suppressed from being uneven, and the filling uniformity of the conductive layer is improved. Further, when the plating process is performed, the alloy layer of the plating seed layer is covered with a conductive layer mainly composed of Cu, so that the metal on the surface side of the alloy layer is eluted in the plating solution. Is prevented. Thereby, when the conductive layer is embedded in the recess by plating, an increase in resistance of the conductive layer due to the metal eluted in the plating solution being embedded together with the conductive layer is prevented.

以上説明したように、本発明の半導体装置の製造方法によれば、導電層の膜剥がれを防止することができるため、半導体装置の歩留まりを向上させることができる。また、基板面内における導電層の埋め込み均一性が向上するため、例えばＣＭＰ法により導電層を研磨する際のディッシングやエロージョンを抑制することができる。さらには、導電層の抵抗の増大を防止することができる。したがって、凹部が配線溝、導電層が配線である場合には、配線抵抗の増大を防止し、配線信頼性を向上させることができる。   As described above, according to the method for manufacturing a semiconductor device of the present invention, the peeling of the conductive layer can be prevented, so that the yield of the semiconductor device can be improved. In addition, since the filling uniformity of the conductive layer in the substrate surface is improved, dishing and erosion when the conductive layer is polished by, for example, CMP can be suppressed. Furthermore, an increase in resistance of the conductive layer can be prevented. Therefore, when the recess is a wiring groove and the conductive layer is a wiring, an increase in wiring resistance can be prevented and wiring reliability can be improved.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

（第１実施形態）
本実施形態例は、本発明にかかる半導体装置の製造方法の実施形態の一例であり、シングルダマシン配線構造の形成に係わる。以下、図１〜図２の製造工程断面図を用いて本発明の第１実施形態を説明する。なお、背景技術と同様の構成には、同一の番号を付して説明することとする。 (First embodiment)
The present embodiment is an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention, and relates to the formation of a single damascene wiring structure. The first embodiment of the present invention will be described below with reference to the cross-sectional views of the manufacturing steps shown in FIGS. In addition, the same number is attached | subjected and demonstrated to the structure similar to a background art.

まず、図１（ａ）に示すように、トランジスタ等の素子が形成されたシリコンウェハからなる基板１１上に、例えばＳｉＯ2からなる層間絶縁膜１２を形成した後、基板１１に達する状態の接続孔１３を形成し、接続孔１３内に例えばＷからなるヴィア１４を埋め込み形成する。 First, as shown in FIG. 1A, after an interlayer insulating film 12 made of, for example, SiO 2 is formed on a substrate 11 made of a silicon wafer on which elements such as transistors are formed, connection in a state of reaching the substrate 11 A hole 13 is formed, and a via 14 made of, for example, W is embedded in the connection hole 13.

次に、例えばプラズマ励起化学的気相成長（Plasma Enhanced Chemical Vapor Deposition（ＰＥＣＶＤ））法により、成膜ガスにシラン（ＳｉＨ4）を用いて、ヴィア１４上を含む層間絶縁膜１２上に、例えばＳｉＯ2からなる層間絶縁膜１５を形成する。 Next, by using, for example, plasma enhanced chemical vapor deposition (PECVD), silane (SiH 4 ) is used as a film forming gas, on the interlayer insulating film 12 including the via 14, for example, An interlayer insulating film 15 made of SiO 2 is formed.

次いで、層間絶縁膜１５上に、配線溝パターンを有するレジストパターン（図示省略）を形成し、このレジストパターンをマスクに用いたエッチングにより層間絶縁膜１５に、配線溝１６（凹部）を形成する。この配線溝１６の開口幅は、７５ｎｍであることとする。   Next, a resist pattern (not shown) having a wiring groove pattern is formed on the interlayer insulating film 15, and a wiring groove 16 (concave portion) is formed in the interlayer insulating film 15 by etching using this resist pattern as a mask. The opening width of the wiring groove 16 is 75 nm.

続いて、図１（ｂ）に示すように、例えばＣｕＭｎからなる合金ターゲットを用いて、スパッタリング法等の物理的気相成長（Physical Vapor Deposition（ＰＶＤ））法により、配線溝１６の内壁を覆う状態で、層間絶縁膜１５上に、ＣｕＭｎからなる合金層１７ａを形成する。ここで、ＭｎはＣｕよりも抵抗値が高く、また、合金層１７ａ中のＭｎは、後工程で熱処理を行うことにより、層間絶縁膜１２、１５の構成成分と反応して自己形成バリア膜を形成する。   Subsequently, as shown in FIG. 1B, the inner wall of the wiring trench 16 is covered by a physical vapor deposition (PVD) method such as sputtering using an alloy target made of, for example, CuMn. In this state, an alloy layer 17 a made of CuMn is formed on the interlayer insulating film 15. Here, Mn has a higher resistance value than Cu, and Mn in the alloy layer 17a reacts with the constituent components of the interlayer insulating films 12 and 15 by performing a heat treatment in a later process to form a self-formed barrier film. Form.

このため、合金層１７ａ中のＭｎ濃度および合金層１７ａの膜厚は、後工程で行う熱処理により、合金層１７ａと層間絶縁膜１２、１５の界面に連続的な自己形成バリア膜を形成可能なＭｎ濃度および膜厚以上で、かつ配線溝１６内に形成する配線中にＭｎが残存した場合の配線抵抗と、この合金層１７ａ上に後述するＣｕを主成分とする導電層を積層してなるめっきシード層のシート抵抗とが、許容範囲内となるＭｎ濃度および膜厚以下の範囲で規定される。   Therefore, the Mn concentration in the alloy layer 17a and the film thickness of the alloy layer 17a can be formed as a continuous self-forming barrier film at the interface between the alloy layer 17a and the interlayer insulating films 12 and 15 by a heat treatment performed in a later step. A wiring resistance in the case where Mn concentration and film thickness or more and Mn remains in the wiring formed in the wiring groove 16 is laminated on the alloy layer 17a with a conductive layer mainly composed of Cu to be described later. The sheet resistance of the plating seed layer is defined in the range of the Mn concentration and the film thickness within the allowable range.

具体的には、合金層１７ａ中のＭｎ濃度は１atomic％以上１０atomic％以下であり、好ましくは２atomic％以上６atomic％以下であることとする。また、合金層１７ａの膜厚は、上記範囲の上限に加えて、その後のめっき法による導電層の埋め込み特性が悪化しない程度の膜厚以下となるように規定する。具体的には、合金層１７ａの膜厚は、配線溝パターンのない平滑部で１０ｎｍ以上５０ｎｍ以下であり、ここでは、例えば３０ｎｍの膜厚で形成することとする。   Specifically, the Mn concentration in the alloy layer 17a is 1 atomic% or more and 10 atomic% or less, and preferably 2 atomic% or more and 6 atomic% or less. In addition to the upper limit of the above range, the thickness of the alloy layer 17a is defined to be not more than a thickness that does not deteriorate the filling characteristics of the conductive layer by the subsequent plating method. Specifically, the film thickness of the alloy layer 17a is 10 nm or more and 50 nm or less in a smooth portion without a wiring groove pattern, and here, for example, it is formed with a film thickness of 30 nm.

次に、図１（ｃ）に示すように、合金層１７ａ上に、例えば純Ｃｕからなる導電層１７ｂを例えば３０ｎｍの膜厚で形成することで、合金層１７ａと導電層１７ｂとがこの順に積層されためっきシード層１７が形成される。これにより、合金層１７ａの表面側が純Ｃｕからなる導電層１７ｂで覆われるため、めっきシード層１７がＣｕＭｎからなる合金層１７ａのみで形成される場合と比較して、めっきシード層１７のシート抵抗が低くなる。これにより、後述する配線溝１６内に導電層を埋め込むめっき工程への負荷が抑制される。   Next, as shown in FIG. 1C, by forming a conductive layer 17b made of, for example, pure Cu with a film thickness of, for example, 30 nm on the alloy layer 17a, the alloy layer 17a and the conductive layer 17b are in this order. A laminated plating seed layer 17 is formed. Thereby, since the surface side of the alloy layer 17a is covered with the conductive layer 17b made of pure Cu, the sheet resistance of the plating seed layer 17 is compared with the case where the plating seed layer 17 is formed only of the alloy layer 17a made of CuMn. Becomes lower. Thereby, the load to the plating process which embeds a conductive layer in the wiring groove | channel 16 mentioned later is suppressed.

なお、ここでは、導電層１７ｂが純Ｃｕで構成される例について説明するが、上記導電層１７ｂとしては、Ｃｕを主成分として含んでいればよく、例えば比抵抗の上昇が少ないＣｕＡｇ合金を用いてもよい。   Here, an example in which the conductive layer 17b is made of pure Cu will be described. However, as the conductive layer 17b, it is only necessary to contain Cu as a main component, and for example, a CuAg alloy with a small increase in specific resistance is used. May be.

ここで、上記導電層１７ｂの膜厚は、上述したように、めっきシード層１７のシート抵抗を許容範囲内に抑制するとともに、めっき法による導電層１８の埋め込み特性を悪化させない程度の膜厚とする。具体的には、導電層１７ｂの膜厚は、配線溝パターンのない平滑部で１０ｎｍ以上５０ｎｍ以下であり、ここでは、例えば３０ｎｍの膜厚で形成することとする。   Here, as described above, the film thickness of the conductive layer 17b is such that the sheet resistance of the plating seed layer 17 is suppressed within an allowable range and the embedding property of the conductive layer 18 by the plating method is not deteriorated. To do. Specifically, the film thickness of the conductive layer 17b is 10 nm or more and 50 nm or less in a smooth portion without a wiring groove pattern, and here, for example, it is formed with a film thickness of 30 nm.

次いで、図２（ｄ）に示すように、例えば電解めっき法により、配線溝１６を埋め込む状態で、上記導電層１７ｂ上に、例えば純Ｃｕからなる導電層１８を８００ｎｍ以上の膜厚で形成する。この際、上述したように、めっきシード層１７のシート抵抗が低くなることで、基板１１面内における導電層１８の埋め込み均一性が向上する。また、合金層１７ａの表面側が純Ｃｕからなる導電層１７ｂで覆われていることで、合金層１７ａの表面側のＭｎがめっき液中に溶出することが防止され、めっき液中に溶出されたＭｎが配線溝１６内に導電層１８とともに埋め込まれることが防止される。これにより、配線抵抗の増大が防止される。また、めっき液中に溶出されたＭｎがめっき工程に及ぼす悪影響が回避される。   Next, as shown in FIG. 2D, a conductive layer 18 made of, for example, pure Cu is formed with a film thickness of 800 nm or more on the conductive layer 17b in a state where the wiring groove 16 is embedded, for example, by electrolytic plating. . At this time, as described above, the sheet resistance of the plating seed layer 17 is lowered, so that the filling uniformity of the conductive layer 18 in the surface of the substrate 11 is improved. Further, since the surface side of the alloy layer 17a is covered with the conductive layer 17b made of pure Cu, the Mn on the surface side of the alloy layer 17a is prevented from being eluted into the plating solution, and is eluted into the plating solution. Mn is prevented from being embedded in the wiring trench 16 together with the conductive layer 18. This prevents an increase in wiring resistance. Further, adverse effects of Mn eluted in the plating solution on the plating process are avoided.

なお、ここでは、導電層１８が純Ｃｕで構成される例について説明するが、上記導電層１８としては、Ｃｕを主成分として含んでいればよく、例えば比抵抗の上昇が少ないＣｕＡｇ合金を用いてもよい。   Here, an example in which the conductive layer 18 is composed of pure Cu will be described. However, as the conductive layer 18, it is only necessary to contain Cu as a main component, and for example, a CuAg alloy with a small increase in specific resistance is used. May be.

その後、図２（ｅ）に示すように、例えば３００℃で３０分間の熱処理を行うことで、合金層１７ａ（前記図２（ｄ）参照）中のＭｎを層間絶縁膜１２、１５の構成成分と反応させて、合金層１７ａと層間絶縁膜１２、１５との界面に、Ｃｕの拡散防止性を有する自己形成バリア膜１９を形成する。ここで、自己形成バリア膜１９が形成される熱処理の温度範囲および処理時間は、自己形成バリア膜１９の確実な形成を促進し、熱処理によるデバイスへの悪影響を防ぐため、２００℃〜４００℃、６０秒〜２時間であることが好ましく、より好ましくは６０秒〜３０分間である。また、層間絶縁膜１２、１５の構成成分には、層間絶縁膜１２、１５の表面に吸着する大気中からの酸素または水分等も含まれることとする。   Thereafter, as shown in FIG. 2 (e), for example, heat treatment is performed at 300 ° C. for 30 minutes, so that Mn in the alloy layer 17a (see FIG. 2 (d)) is converted into constituent components of the interlayer insulating films 12 and 15. To form a self-forming barrier film 19 having a Cu diffusion preventing property at the interface between the alloy layer 17a and the interlayer insulating films 12 and 15. Here, the temperature range and the processing time of the heat treatment for forming the self-forming barrier film 19 promote the reliable formation of the self-forming barrier film 19 and prevent adverse effects on the device due to the heat treatment. It is preferably 60 seconds to 2 hours, more preferably 60 seconds to 30 minutes. The constituent components of the interlayer insulating films 12 and 15 include oxygen or moisture from the atmosphere adsorbed on the surfaces of the interlayer insulating films 12 and 15.

ここでは、層間絶縁膜１２、１５がＳｉＯ2で構成されているため、自己形成バリア膜１９は、シリコン含有Ｍｎ酸化物（ＭｎＳｉxＯy）またはＭｎ酸化物（ＭｎxＯy）等のＭｎ化合物で構成され、２ｎｍ〜３ｎｍの膜厚で形成される。ここで、合金層１７ａ中には、連続的な自己形成バリア膜１９が形成される程度に高濃度化されたＭｎが含有されているため、従来方法よりも多量のＭｎを合金層１７ａと層間絶縁膜１２、１５の界面に供給することができ、強固で密着性の高い連続的な自己形成バリア膜１９が形成される。これにより、熱処理の初期の段階における急激な応力変化により、導電層１８の膜剥がれが生じることが防止される。また、熱処理条件のマージンを広く確保することが可能となる。さらに、この熱処理により、導電層１８の表面側にもＭｎが偏析することで、ＭｎＯ層Ｍが形成される。 Here, since the interlayer insulating films 12 and 15 are made of SiO 2 , the self-forming barrier film 19 is made of Mn such as silicon-containing Mn oxide (MnSi x O y ) or Mn oxide (Mn x O y ). It is composed of a compound and is formed with a film thickness of 2 nm to 3 nm. Here, since the alloy layer 17a contains Mn that is highly concentrated to the extent that a continuous self-forming barrier film 19 is formed, a larger amount of Mn than the conventional method is added to the alloy layer 17a. A continuous self-forming barrier film 19 that can be supplied to the interface between the insulating films 12 and 15 and is strong and has high adhesion is formed. As a result, it is possible to prevent the conductive layer 18 from peeling off due to a rapid stress change in the initial stage of heat treatment. Further, it is possible to ensure a wide margin for the heat treatment conditions. Furthermore, by this heat treatment, Mn is segregated also on the surface side of the conductive layer 18, whereby the MnO layer M is formed.

続いて、図２（ｆ）に示すように、例えばＣＭＰ法により、２段階の研磨を行い、１段階目では、ＭｎＯ層Ｍ（前記図２（ｅ）参照）とともに配線パターンとして不要な部分の導電層１８（前記図２（ｅ）参照）を除去する。続いて、２段階目の研磨では、自己形成バリア膜１９を除去し、露出された層間絶縁膜１５を１００ｎｍ削り込む。これにより、配線溝１６にＣｕからなる配線１８’が形成される。この際、導電層１８と層間絶縁膜１２、１５との界面には、上述した自己形成バリア膜１９が設けられていることで、ＣＭＰ工程による導電層１８の膜剥がれが防止されるため、ＣＭＰ条件のマージンを広く確保することが可能である。   Subsequently, as shown in FIG. 2 (f), two-stage polishing is performed by, for example, CMP, and in the first stage, an unnecessary portion as a wiring pattern is formed together with the MnO layer M (see FIG. 2 (e)). The conductive layer 18 (see FIG. 2E) is removed. Subsequently, in the second stage polishing, the self-formed barrier film 19 is removed, and the exposed interlayer insulating film 15 is etched away by 100 nm. As a result, a wiring 18 ′ made of Cu is formed in the wiring groove 16. At this time, since the above-described self-formed barrier film 19 is provided at the interface between the conductive layer 18 and the interlayer insulating films 12 and 15, peeling of the conductive layer 18 due to the CMP process is prevented. It is possible to ensure a wide margin of conditions.

次いで、クエン酸水溶液やシュウ酸水溶液等を用いた有機酸洗浄を行うことで、配線１８’上の酸化膜と上記ＣＭＰ工程でＣｕ表面に残存するベンゾトリアゾール誘導体等のＣｕの防食剤を除去する。その後、トリメチルシラン（３ＭＳ）等のシリコン含有材料とアンモニア（ＮＨ3）等を成膜ガスとして用いたＣＶＤ法により、配線１８’上および層間絶縁膜１５上に、例えば炭窒化シリコン（ＳｉＣＮ）からなるキャップ膜２０を５０ｎｍの膜厚で成膜する。 Next, organic acid cleaning using an aqueous citric acid solution, an aqueous oxalic acid solution, or the like is performed to remove the oxide film on the wiring 18 ′ and the Cu anticorrosive agent such as a benzotriazole derivative remaining on the Cu surface in the CMP step. . Thereafter, a CVD method using a silicon-containing material such as trimethylsilane (3MS) and ammonia (NH 3 ) or the like as a film forming gas is performed on the wiring 18 ′ and the interlayer insulating film 15 from, for example, silicon carbonitride (SiCN). A cap film 20 is formed to a thickness of 50 nm.

このような半導体装置の製造方法によれば、図１（ｃ）を用いて説明したように合金層１７ａと純Ｃｕからなる導電層１７ｂとを順次積層してなるめっきシード層１７を形成することから、めっき工程への負荷を抑制した状態で、合金層１７ａ中のＭｎを高濃度化することができるため、合金層１７ａと層間絶縁膜１２、１５との界面に連続的な自己形成バリア膜１９を形成することができる。これにより、導電層１８と層間絶縁膜１２、１５との密着性が向上し、導電層１８の膜剥がれを防止することができる。したがって、半導体装置の歩留まりを向上させることができるとともに、自己形成バリア膜１９を形成する際の熱処理条件や導電層１８を研磨する際のＣＭＰ条件のマージンをより広く確保することができる。   According to such a method of manufacturing a semiconductor device, as described with reference to FIG. 1C, the plating seed layer 17 is formed by sequentially laminating the alloy layer 17a and the conductive layer 17b made of pure Cu. From this, it is possible to increase the concentration of Mn in the alloy layer 17a in a state where the load on the plating process is suppressed. Therefore, a continuous self-formed barrier film is formed at the interface between the alloy layer 17a and the interlayer insulating films 12 and 15. 19 can be formed. Thereby, the adhesiveness between the conductive layer 18 and the interlayer insulating films 12 and 15 is improved, and the film peeling of the conductive layer 18 can be prevented. Therefore, the yield of the semiconductor device can be improved, and a wider margin can be secured for the heat treatment conditions for forming the self-formed barrier film 19 and the CMP conditions for polishing the conductive layer 18.

また、めっきシード層１７のシート抵抗を低くすることができるため、基板１１の面内における導電層１８の埋め込み均一性を向上させることができる。したがって、ＣＭＰ法により導電層１８を研磨する際のディッシングやエロージョンを抑制することができ、配線信頼性を向上させることができる。   In addition, since the sheet resistance of the plating seed layer 17 can be reduced, the filling uniformity of the conductive layer 18 in the plane of the substrate 11 can be improved. Therefore, dishing and erosion when the conductive layer 18 is polished by the CMP method can be suppressed, and the wiring reliability can be improved.

さらに、めっき工程を行う際に、合金層１７ａが純Ｃｕからなる導電層１７ｂで覆われていることから、めっき液中へのＭｎの溶出が防止され、配線溝１６にＭｎが導電層１８とともに埋め込まれることによる配線１８’の抵抗の増大を防止することができる。   Furthermore, when the plating process is performed, the alloy layer 17a is covered with the conductive layer 17b made of pure Cu, so that elution of Mn into the plating solution is prevented, and Mn is contained in the wiring groove 16 together with the conductive layer 18. It is possible to prevent an increase in resistance of the wiring 18 ′ due to the embedding.

ここで、本発明の半導体装置の製造方法が適用されためっきシード層（１）と本発明が適用されていないめっきシード層（２）、（３）のシート抵抗値を比較した結果を表１に示す。

Figure 2008047719
Here, the results of comparing the sheet resistance values of the plating seed layer (1) to which the method of manufacturing a semiconductor device of the present invention is applied and the plating seed layers (2) and (3) to which the present invention is not applied are shown in Table 1. Shown in
Figure 2008047719

この表に示すように、膜厚３０ｎｍの２Ａ％Ｍｎ含有ＣｕＭｎ層（合金層１７ａ）上に膜厚３０ｎｍの純Ｃｕ層（導電層１７ｂ）を積層してなるめっきシード層（１）のシート抵抗値は、６０ｎｍの膜厚の２Ａ％Ｍｎ含有ＣｕＭｎ層からなるめっきシード層（２）のシート抵抗値と比較して顕著に低い値を示すことが確認された。また、その１／２のＭｎ濃度である６０ｎｍの膜厚のＡ％Ｍｎ含有ＣｕＭｎ層からなるめっきシード層（３）は、めっきシード層（１）とトータルのＭｎ濃度は同等であるが、シート抵抗値を比較すると、めっきシード層（１）の方が低い値を示すことが確認された。したがって、ＣｕＭｎからなる合金層１７ａ上に純Ｃｕからなる導電層１７ｂを積層させることで、合金層１７ａのみでめっきシード層１７を構成する場合と比較して、めっきシード層１７のシート抵抗値が顕著に抑制されることが確認された。   As shown in this table, the sheet resistance of the plating seed layer (1) formed by laminating a pure Cu layer (conductive layer 17b) with a thickness of 30 nm on a 2A% Mn-containing CuMn layer (alloy layer 17a) with a thickness of 30 nm. The value was confirmed to be significantly lower than the sheet resistance value of the plating seed layer (2) composed of the 2A% Mn-containing CuMn layer having a thickness of 60 nm. In addition, the plating seed layer (3) composed of an A% Mn-containing CuMn layer having a thickness of 60 nm, which is a ½ Mn concentration, has the same total Mn concentration as the plating seed layer (1). When the resistance values were compared, it was confirmed that the plating seed layer (1) showed a lower value. Therefore, by laminating the conductive layer 17b made of pure Cu on the alloy layer 17a made of CuMn, the sheet resistance value of the plating seed layer 17 is smaller than that in the case where the plating seed layer 17 is formed only by the alloy layer 17a. It was confirmed that it was significantly suppressed.

（第２実施形態）
次に、本発明の半導体装置の製造方法に係る第２の実施の形態を、図３〜図６の製造工程断面図を用いて説明する。ここでは、第１実施形態で説明したキャップ膜の上層に、デュアルダマシン配線構造を形成する例について、説明する。 (Second Embodiment)
Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described using the manufacturing process sectional views of FIGS. Here, an example in which a dual damascene wiring structure is formed on the cap film described in the first embodiment will be described.

まず、図３（ａ）に示すように、キャップ膜２０上に、例えばＰＥ−ＣＶＤ法により、例えばＳｉＯ2からなる層間絶縁膜２１を３５０ｎｍの膜厚で形成する。続いて、層間絶縁膜２１上に、接続孔パターンを有するレジストパターン（図示省略）を形成し、このレジストパターンをマスクに用いたエッチングにより、キャップ膜２０に達する状態の接続孔２２ａを形成する。 First, as shown in FIG. 3A, an interlayer insulating film 21 made of, for example, SiO 2 is formed to a thickness of 350 nm on the cap film 20 by, eg, PE-CVD. Subsequently, a resist pattern (not shown) having a connection hole pattern is formed on the interlayer insulating film 21, and a connection hole 22a that reaches the cap film 20 is formed by etching using the resist pattern as a mask.

次に、図３（ｂ）に示すように、接続孔２２ａを埋め込む状態で、層間絶縁膜２１上にレジストＲを塗布する。続いて、レジストＲ上にＳＯＧ（Spin On Glass)膜を形成し、ＳＯＧ膜上に配線溝パターンを有するレジストパターン（図示省略）を形成した後、このレジストパターンをマスクに用いたエッチングにより、ＳＯＧ膜を加工して、ハードマスク２３を形成する。   Next, as illustrated in FIG. 3B, a resist R is applied on the interlayer insulating film 21 in a state where the connection hole 22 a is embedded. Subsequently, an SOG (Spin On Glass) film is formed on the resist R, a resist pattern (not shown) having a wiring groove pattern is formed on the SOG film, and then SOG is performed by etching using the resist pattern as a mask. The film is processed to form a hard mask 23.

次いで、図３（ｃ）に示すように、ハードマスク２３をマスクに用いたエッチングにより、上記レジストＲ（前記図３（ｂ）参照）を加工し、配線溝パターンを有するレジストパターンＲ’を形成する。また、接続孔２２ａの底部側を覆うレジストＲは残存させる。   Next, as shown in FIG. 3C, the resist R (see FIG. 3B) is processed by etching using the hard mask 23 as a mask to form a resist pattern R ′ having a wiring groove pattern. To do. Further, the resist R covering the bottom side of the connection hole 22a is left.

続いて、図４（ｄ）に示すように、上記ハードマスク２３（前記図３（ｃ）参照）とレジストパターンＲ’とをマスクに用いたエッチングにより、層間絶縁膜２１の上層側に接続孔２２ａと連通する状態の配線溝２２ｂを形成する。これにより、配線溝２２ｂとその底部に連通する接続孔２２ａとからなるデュアルダマシン開口部２２（凹部）が形成される。この際、エッチング時間を制御することで、上記配線溝２２ｂの深さを制御する。ここで、接続孔２２ａの開口幅は７５ｎｍ、深さは１１０ｎｍ、配線溝２２ｂの開口幅は７５〜１００ｎｍ、深さは１５０ｎｍであることとする。また、接続孔２２ａの内部にレジストＲを残存させることで、接続孔２２ａの側壁がエッチングされることを防止し、側壁が垂直に維持される。   Subsequently, as shown in FIG. 4D, a connection hole is formed on the upper side of the interlayer insulating film 21 by etching using the hard mask 23 (see FIG. 3C) and the resist pattern R ′ as a mask. A wiring groove 22b in communication with 22a is formed. As a result, a dual damascene opening 22 (concave portion) is formed which includes the wiring groove 22b and the connection hole 22a communicating with the bottom thereof. At this time, the depth of the wiring trench 22b is controlled by controlling the etching time. Here, the opening width of the connection hole 22a is 75 nm, the depth is 110 nm, the opening width of the wiring groove 22b is 75 to 100 nm, and the depth is 150 nm. Further, by leaving the resist R inside the connection hole 22a, the side wall of the connection hole 22a is prevented from being etched, and the side wall is kept vertical.

その後、図４（ｅ）に示すように、アッシングおよび薬液洗浄により、上記レジストパターンＲ’（前記図４（ｄ）参照）およびレジストＲ（前記図４（ｄ）参照）を除去した後、接続孔２２ａの底部のキャップ膜２０を露出する。   Thereafter, as shown in FIG. 4E, the resist pattern R ′ (see FIG. 4D) and the resist R (see FIG. 4D) are removed by ashing and chemical cleaning, and then connected. The cap film 20 at the bottom of the hole 22a is exposed.

次に、図４（ｆ）に示すように、接続孔２２ａ底部のキャップ膜２０を除去し、配線１８’の表面を露出する。   Next, as shown in FIG. 4F, the cap film 20 at the bottom of the connection hole 22a is removed, and the surface of the wiring 18 'is exposed.

次いで、図５（ｇ）に示すように、例えばスパッタリング法により、デュアルダマシン開口部２２の内壁を覆う状態で、層間絶縁膜２１上に、ＣｕＭｎ合金からなる合金層２４ａを形成する。ここで、第１実施形態と同様に、この合金層２４ａのＭｎ濃度は、１atomic％以上１０atomic％以下であり、好ましくは２atomic％以上６atomic％以下である。また、合金層２４ａの膜厚は、配線溝パターンのない平滑部で１０ｎｍ以上５０ｎｍである   Next, as shown in FIG. 5G, an alloy layer 24a made of a CuMn alloy is formed on the interlayer insulating film 21 so as to cover the inner wall of the dual damascene opening 22 by, for example, sputtering. Here, as in the first embodiment, the Mn concentration of the alloy layer 24a is not less than 1 atomic% and not more than 10 atomic%, preferably not less than 2 atomic% and not more than 6 atomic%. Moreover, the film thickness of the alloy layer 24a is 10 nm or more and 50 nm in the smooth part without the wiring groove pattern.

続いて、図５（ｈ）に示すように、合金層２４ａ上に、例えば純Ｃｕからなる導電層２４ｂを形成する。これにより、合金層２４ａと導電層２４ｂとを順次積層してなるめっきシード層２４が形成される。ここで、第１実施形態と同様に、この導電層２４ｂの膜厚は配線溝パターンのない平滑部で１０ｎｍ以上５０ｎｍである。   Subsequently, as shown in FIG. 5H, a conductive layer 24b made of, for example, pure Cu is formed on the alloy layer 24a. Thereby, the plating seed layer 24 formed by sequentially laminating the alloy layer 24a and the conductive layer 24b is formed. Here, as in the first embodiment, the thickness of the conductive layer 24b is 10 nm or more and 50 nm in a smooth portion without a wiring groove pattern.

その後、図５（ｉ）に示すように、デュアルダマシン開口部２２を埋め込む状態で、Ｃｕ層２４ｂ上に、例えば純Ｃｕからなる導電層２５を形成する。   Thereafter, as shown in FIG. 5I, a conductive layer 25 made of pure Cu, for example, is formed on the Cu layer 24b in a state where the dual damascene opening 22 is embedded.

次に、図６（ｊ）に示すように、例えば３００℃で３０分間の熱処理を行うことで、合金層２４ａ（前記図５（ｉ）参照）中のＭｎを層間絶縁膜２１の構成成分と反応させて、合金層２４ａと層間絶縁膜２１の間にＣｕの拡散防止性を有するＭｎ化合物からなる自己形成バリア膜２６を形成する。ここで、第１実施形態と同様に、層間絶縁膜２１はＳｉＯ2で構成されているため、自己形成バリア膜２６は、シリコン含有Ｍｎ酸化物（ＭｎＳｉxＯy)またはＭｎ酸化物（ＭｎxＯy)で構成され、２ｎｍ〜３ｎｍの膜厚で形成される。 Next, as shown in FIG. 6 (j), for example, by performing a heat treatment at 300 ° C. for 30 minutes, Mn in the alloy layer 24 a (see FIG. 5 (i)) becomes a component of the interlayer insulating film 21. By reacting, a self-forming barrier film 26 made of a Mn compound having a Cu diffusion preventing property is formed between the alloy layer 24a and the interlayer insulating film 21. Here, as in the first embodiment, since the interlayer insulating film 21 is made of SiO 2 , the self-forming barrier film 26 is made of silicon-containing Mn oxide (MnSi x O y ) or Mn oxide (Mn x consists of O y), is formed in a thickness of 2 nm to 3 nm.

その後、図６（ｋ）に示すように、例えばＣＭＰ法により、２段階の研磨を行い、１段階目では、ＭｎＯ層Ｍ（前記図６（ｊ）参照）とともに配線パターンとして不要な部分の導電層２５（前記図６（ｊ）参照）を除去する。続いて、２段階目の研磨では、自己形成バリア膜２６を除去し、露出された層間絶縁膜２１を１００ｎｍ削り込む。これにより、接続孔２２ａに配線１８’と連通する状態のヴィア２５ａ’が形成されるとともに、配線溝２２ｂに配線２５ｂ’が形成される。   Thereafter, as shown in FIG. 6 (k), two-step polishing is performed by, for example, a CMP method. In the first step, unnecessary portions of the conductive pattern as a wiring pattern are formed together with the MnO layer M (see FIG. 6 (j)). The layer 25 (see FIG. 6 (j)) is removed. Subsequently, in the second stage polishing, the self-formed barrier film 26 is removed, and the exposed interlayer insulating film 21 is etched by 100 nm. As a result, vias 25a 'communicating with the wirings 18' are formed in the connection holes 22a, and wirings 25b 'are formed in the wiring grooves 22b.

次いで、クエン酸水溶液やシュウ酸水溶液等を用いた有機酸洗浄を行うことで、配線２５ｂ’上の酸化膜と上記ＣＭＰ工程でＣｕ表面に残存するＣｕの防食剤を除去する。その後、配線２５ｂ’上および層間絶縁膜２１上に、例えばＳｉＣＮからなるキャップ膜２７を５０ｎｍの膜厚で成膜する。   Next, organic acid cleaning using an aqueous citric acid solution, an oxalic acid aqueous solution, or the like is performed to remove the oxide film on the wiring 25b 'and the Cu anticorrosive remaining on the Cu surface in the CMP step. Thereafter, a cap film 27 made of, for example, SiCN is formed with a film thickness of 50 nm on the wiring 25 b ′ and the interlayer insulating film 21.

このような半導体装置の製造方法であっても、図５（ｇ）〜（ｈ）を用いて説明したように、ＣｕＭｎからなる合金層２４ａと純Ｃｕからなる導電層２４ｂとを順次積層してなるめっきシード層２４を形成することで、第１実施形態と同様の効果を奏することができる。   Even in such a method for manufacturing a semiconductor device, as described with reference to FIGS. 5G to 5H, the alloy layer 24a made of CuMn and the conductive layer 24b made of pure Cu are sequentially laminated. By forming the plating seed layer 24, the same effects as those of the first embodiment can be obtained.

なお、上述した第１実施形態および第２実施形態においては、ＣｕＭｎで合金層１７ａ、２４ａを構成する例について説明したが、合金層１７ａ、２４ａを構成するＣｕ以外の金属としては、上述したＭｎの他に、例えばアルミニウム（Ａｌ）、亜鉛（Ｚｎ）、クロム（Ｃｒ）、バナジウム（Ｖ）、チタン（Ｔｉ）、タンタル（Ｔａ）を例示することができる。例えば、合金層１７ａ、２４ａをＣｕＡｌとする場合には、自己形成バリア膜１９として、例えばシリコン含有Ａｌ酸化物（ＡｌＳｉxＯy)またはＡｌ酸化物（ＡｌxＯy)が形成され、合金層１７ａ、２４ａをＣｕＺｎとする場合には、自己形成バリア膜１９として、例えばシリコン含有Ｚｎ酸化物（ＺｎＳｉxＯy)またはＺｎ酸化物（ＺｎxＯy)が形成される。上記に例示したほかの金属に関しても同様のシリコン化合物または酸化物が形成される。 In the first embodiment and the second embodiment described above, the example in which the alloy layers 17a and 24a are made of CuMn has been described. However, as the metal other than Cu constituting the alloy layers 17a and 24a, the above-described Mn In addition, for example, aluminum (Al), zinc (Zn), chromium (Cr), vanadium (V), titanium (Ti), and tantalum (Ta) can be exemplified. For example, when the alloy layers 17a and 24a are made of CuAl, for example, silicon-containing Al oxide (AlSi x O y ) or Al oxide (Al x O y ) is formed as the self-forming barrier film 19, and the alloy layer When 17a and 24a are CuZn, as the self-forming barrier film 19, for example, silicon-containing Zn oxide (ZnSi x O y ) or Zn oxide (Zn x O y ) is formed. Similar silicon compounds or oxides are formed for the other metals exemplified above.

さらに、本実施形態では、自己形成バリア膜１９、２６を構成するＭｎ化合物として、シリコン含有Ｍｎ酸化物（ＭｎＳｉxＯy)またはＭｎ酸化物（ＭｎxＯy)を例示したが、層間絶縁膜１２、１５、２１が、例えば有機系絶縁膜等の炭素を含む絶縁膜である場合には、自己形成バリア膜１９、２６を構成するＭｎ化合物としてＭｎ炭化物（ＭｎxＣy)が形成される場合もある。なお、合金層１７ａとして、上述したＣｕＡｌまたはＣｕＴｉを用いた場合には、Ａｌ炭化物（ＡｌxＣy)またはチタン炭化物（ＴｉxＣy)が形成される場合もある。さらに、上記に例示したほかの金属に関しても同様の金属炭化物が形成される。 Further, in the present embodiment, as the Mn compound constituting the self-forming barrier films 19 and 26, silicon-containing Mn oxide (MnSi x O y ) or Mn oxide (Mn x O y ) is exemplified, but the interlayer insulating film When 12, 15, 21 is an insulating film containing carbon such as an organic insulating film, for example, Mn carbide (Mn x C y ) is formed as the Mn compound constituting the self-forming barrier films 19 and 26. In some cases. When CuAl or CuTi described above is used as the alloy layer 17a, Al carbide (Al x C y ) or titanium carbide (Ti x C y ) may be formed. Further, similar metal carbides are formed for the other metals exemplified above.

本発明の半導体装置の製造方法に係る第１実施形態を説明するための製造工程断面図（その１）である。FIG. 6 is a manufacturing process cross-sectional view (No. 1) for describing the first embodiment of the semiconductor device manufacturing method of the present invention; 本発明の半導体装置の製造方法に係る第１実施形態を説明するための製造工程断面図（その２）である。FIG. 6 is a manufacturing process sectional view (No. 2) for describing the first embodiment of the manufacturing method of the semiconductor device of the invention; 本発明の半導体装置の製造方法に係る第２実施形態を説明するための製造工程断面図（その１）である。It is manufacturing process sectional drawing (the 1) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法に係る第２実施形態を説明するための製造工程断面図（その２）である。It is manufacturing process sectional drawing (the 2) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法に係る第２実施形態を説明するための製造工程断面図（その３）である。It is manufacturing process sectional drawing (the 3) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法に係る第２実施形態を説明するための製造工程断面図（その４）である。It is manufacturing process sectional drawing for demonstrating 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention (the 4). 従来の半導体装置の製造方法を説明するための製造工程断面図である。It is manufacturing process sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法に係る課題を説明するための断面図である。It is sectional drawing for demonstrating the subject which concerns on the manufacturing method of the conventional semiconductor device.

符号の説明Explanation of symbols

１１…基板、１２，１５，２１…層間絶縁膜、１６…配線溝、１７，２４…めっきシード層１７ａ，２４ａ…合金層、１７ｂ，２４ｂ…導電層、１８，２５…導電層、１８’，２５ｂ’…配線、２５ａ’…ヴィア   DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 12, 15, 21 ... Interlayer insulation film, 16 ... Wiring groove | channel, 17, 24 ... Plating seed layer 17a, 24a ... Alloy layer, 17b, 24b ... Conductive layer, 18, 25 ... Conductive layer, 18 ', 25b '... wiring, 25a' ... via

Claims (1)

基板上に設けられた絶縁膜に凹部を形成する工程と、
前記凹部の内壁を覆う状態で、銅と銅以外の金属とからなる合金層と、銅を主成分とする導電層とを順次積層してなるめっきシード層を形成する工程と、
めっき法により、前記めっきシード層が設けられた前記凹部に、銅を主成分とする導電層を埋め込む工程と、
熱処理を行い、前記合金層中の前記金属を前記絶縁膜の構成成分と反応させて、当該合金層と前記絶縁膜との界面に、銅の拡散バリア性を有する金属化合物からなるバリア膜を形成する工程とを有する
ことを特徴とする半導体装置の製造方法。
Forming a recess in an insulating film provided on the substrate;
Forming a plating seed layer formed by sequentially laminating an alloy layer made of copper and a metal other than copper and a conductive layer mainly composed of copper in a state of covering the inner wall of the recess;
A step of embedding a conductive layer mainly composed of copper in the concave portion provided with the plating seed layer by a plating method;
Heat treatment is performed to cause the metal in the alloy layer to react with the components of the insulating film, thereby forming a barrier film made of a metal compound having a copper diffusion barrier property at the interface between the alloy layer and the insulating film. A method for manufacturing a semiconductor device.
JP2006222194A 2006-08-17 2006-08-17 Method for manufacturing semiconductor device Pending JP2008047719A (en)

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