JP2008060431A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device where wiring resistance is reduced by removing excessive Mn which does not contribute to forming of a self-forming barrier film in an alloy layer (seed layer). <P>SOLUTION: First, a wiring groove 16 is formed at an interlayer insulating film 15 prepared on a substrate 11. While covering the inner wall of the wiring groove 16, the alloy layer 17 made of CuMn is formed. On the surface of the substrate 11 provided with the alloy layer 17, a washing liquid which dissolves Mn selectively to Cu is supplied and dissolves the Mn in the alloy layer 17 which does not contribute to forming of the self-forming barrier film into the washing liquid to remove selectively. Continually, heat treatment is performed to make Mn in the alloy layer 17 react with the components of interlayer insulating films 12 and 15 to form a self-forming barrier film made of an Mn compound having diffusion prevention property of Cu on the interface of the alloy layer 17 and the interlayer insulating films 12 and 15. Continually, a conductor layer whose main component is Cu is buried in the wiring groove 16 where the self-forming barrier film is provided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a damascene structure in which a self-formed barrier film is provided between a wiring or a via and an interlayer insulating film.

  In a copper (Cu) wiring formation process of a semiconductor device, a damascene method for forming a wiring pattern by embedding wiring grooves provided in an interlayer insulating film is generally performed. When forming a Cu wiring by the damascene method, in order to prevent Cu from diffusing into the interlayer insulating film, the tantalum (Ta) or tantalum nitride film is usually covered with the inner wall of the wiring trench before embedding Cu. A barrier film such as (TaN) is formed to a thickness of about 10 nm. Thereafter, a Cu layer is embedded in the wiring trench provided with the barrier film by electrolytic plating.

  However, with the miniaturization of the wiring pitch, the difficulty of embedding Cu has increased, the ratio of the barrier film to the total wiring volume has increased, and the wiring resistance has increased. A seed layer made of a Cu layer containing Mn is formed without forming a film, and Mn is diffused by a subsequent heat treatment to form a self-formed barrier film made of a Mn compound at the interface between the interlayer insulating film and the Cu wiring. A technique for forming a film with a thickness of about 2 to 3 nm has been proposed (see Non-Patent Document 1, for example).

The self-forming barrier process will be described with reference to FIG. First, as shown in FIG. 21A, an interlayer insulating film 12 made of silicon oxide (SiO ₂ ) is formed on a substrate 11 made of a silicon wafer, and then the interlayer insulating film 12 reaches the substrate 11. A connection hole 13 is formed, and a via 14 made of tungsten (W) is embedded in the connection hole 13.

Next, an interlayer insulating film 15 made of SiO ₂ is formed on the interlayer insulating film 12 including the vias 14. Next, after forming the wiring groove 16 reaching the interlayer insulating film 12 and the via 14 in the interlayer insulating film 15, the alloy layer 17 made of CuMn is formed on the interlayer insulating film 15 so as to cover the inner wall of the wiring groove 16. Since the alloy layer 17 functions as a seed layer for an electrolytic plating method to be performed in a later step, the alloy layer 17 is formed with a certain thickness of 60 nm to 80 nm in order to form with good coverage.

  Subsequently, as shown in FIG. 21B, a conductive layer 18 made of pure Cu is formed on the alloy layer 17 in a state of embedding the wiring groove 16 by electrolytic plating.

  Next, as shown in FIG. 21 (c), heat treatment is performed to cause Mn contained in the alloy layer 17 to react with the constituent components of the interlayer insulating films 12 and 15, so that the alloy layer 17 and the interlayer insulating films 12 and 15 are reacted. A self-forming barrier film 19 made of a Mn compound having Cu diffusion preventing property is formed at the interface with the substrate. The self-forming barrier film 19 is formed with a film thickness of 2 nm to 3 nm. At this time, Mn is segregated also on the surface side of the conductive layer 18, and a manganese oxide (MnO) layer M is formed.

  Thereafter, although not shown in the figure, the conductive layer 18 and the self-formed barrier film 19 which are not necessary as a wiring pattern are removed together with the MnO layer M by a chemical mechanical polishing (CMP) method. Then, the exposed surface of the interlayer insulating film 15 is cut away to form a wiring in the wiring groove 16.

  In the wiring structure formed by the manufacturing method as described above, Mn in the alloy layer 17 and the constituent components of the interlayer insulating films 12 and 15 are compared with the embedding process using the barrier film made of ordinary Ta and TaN. To form a thinned self-formed barrier film 19, which is excellent in embedding characteristics of the conductive layer 18. Further, since the self-formed barrier film 19 is thinner than a barrier film made of Ta or TaN, there is an advantage that the resistance of the wiring can be reduced.

Low Resistive and Highly Reliable Cu Dual-Damascene Interconnect Technology using Self-Formed MnSixOy Barrier Layer, `` 2005 Symposium on VLSI Technology '' p.188-190

  However, in the manufacturing method as described above, as described with reference to FIG. 21C, when Mn in the alloy layer 17 and the constituent components of the interlayer insulating films 12 and 15 are reacted by heat treatment, Mn is reduced. Segregation occurs not only on the interface side with the interlayer insulating films 12 and 15 but also on the surface side of the conductive layer 18. At this time, if Mn that has not been segregated on the interface side with the interlayer insulating films 12 and 15 or the surface side of the conductive layer 18 remains in the wiring in the wiring groove 16, Mn has a higher resistance value than Cu. There is a problem of increasing the wiring resistance. Therefore, even if a self-formed barrier film having a thickness smaller than that of a conventional barrier film such as Ta or TaN is formed, there is no effect in improving the device performance represented by RC delay (wiring delay) as a result. become.

  From the above, the present invention provides a method for manufacturing a semiconductor device that reduces wiring resistance by removing excess Mn that does not contribute to the formation of a self-forming barrier film in an alloy layer (seed layer). It is aimed.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is characterized by sequentially performing the following steps. First, in the first step, a step of forming a recess in an insulating film provided on the substrate is performed. Next, in a 2nd process, the process of forming the alloy layer which consists of copper (Cu) and metals other than Cu in the state which covers the inner wall of a recessed part is performed. Next, in the third step, a barrier film made of a metal compound having a Cu diffusion preventing property is formed at the interface between the alloy layer and the insulating film by performing a heat treatment to react the metal in the alloy layer with the constituent components of the insulating film. The process of forming is performed. Thereafter, in the fourth step, a step of embedding a conductive layer containing Cu as a main component in the recess is performed. And between the 2nd process and the 3rd process or between the 3rd process and the 4th process, the cleaning liquid which dissolves the metal or the compound containing this metal selectively with respect to Cu is supplied to the surface of the substrate, It is characterized by performing a step of removing excess metal that does not contribute to the formation of the barrier film by dissolving it in a cleaning solution.

  According to such a method for manufacturing a semiconductor device, the cleaning liquid is supplied to the surface of the substrate, and an excess metal that does not contribute to the formation of the barrier film or a compound containing this metal is selectively removed with respect to Cu. Therefore, the remaining of the metal in the conductive layer embedded in the recess is suppressed. Thereby, when the metal has a higher resistance value than Cu, the recess is a wiring groove, and the conductive layer is a wiring, an increase in wiring resistance due to the metal remaining in the wiring is suppressed.

  As described above, according to the method for manufacturing a semiconductor device of the present invention, since an increase in wiring resistance is suppressed, RC delay can be suppressed. Therefore, a semiconductor device having high performance and high reliability can be manufactured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
The present embodiment is an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention, and relates to the formation of a single damascene wiring structure. A first embodiment of the present invention will be described below with reference to the manufacturing process sectional views of FIGS. 2 to 3 based on the flowchart of FIG. 1 showing each step (S) in the formation of the single damascene wiring structure. In addition, the same number is attached | subjected and demonstrated to the structure similar to the background art demonstrated using FIG.

First, as shown in FIG. 2A, after an interlayer insulating film 12 made of, for example, SiO ₂ is formed on a substrate 11 made of a silicon wafer on which elements such as transistors are formed, connection in a state reaching the substrate 11 is performed. A hole 13 is formed, and a via 14 made of, for example, W is embedded in the connection hole 13.

Next, by using, for example, plasma enhanced chemical vapor deposition (PECVD), silane (SiH ₄ ) is used as a film forming gas, on the interlayer insulating film 12 including the via 14, for example, An interlayer insulating film 15 made of SiO ₂ is formed to a thickness of 500 nm (S101).

  Next, a resist pattern (not shown) having a wiring trench pattern is formed on the interlayer insulating film 15, and the interlayer insulating film 15 and the via 14 are reached by etching using the resist pattern as a mask. A wiring groove 16 (concave portion) in a state is formed (S102). The opening width of the wiring groove 16 is 75 nm.

  Subsequently, as shown in FIG. 2B, on the interlayer insulating film 15 in a state of covering the inner wall of the wiring trench 16 by a physical vapor deposition (PVD) method such as a sputtering method. For example, the alloy layer 17 made of CuMn containing 2 atomic% Mn is formed (S103). Since this alloy layer 17 functions as a seed layer for the electrolytic plating method to be performed in a later step, in order to surely embed Cu by the electrolytic plating method, the alloy layer 17 has a thickness of 60 nm to 80 nm in order to form with good coverage. It is formed.

  Further, Mn in the alloy layer 17 is formed by forming a conductive layer on the alloy layer 17 in a state in which the wiring groove 16 is embedded in a subsequent process, and then performing a heat treatment, so that the constituent components of the interlayer insulating films 12 and 15 By reacting, a self-forming barrier film made of a Mn compound is formed at the interface with the interlayer insulating films 12 and 15. For this reason, the Mn concentration in the alloy layer 17 is assumed to be a concentration at which a continuous self-forming barrier film can be formed at the interface between the alloy layer 17 and the interlayer insulating films 12 and 15. However, if the Mn concentration in the alloy layer 17 is too high, the Mn concentration in the alloy layer 17 is 1 atomic because it cannot be removed even by the selective Mn cleaning process performed in the subsequent process and causes an increase in wiring resistance. % To 10 atomic%, preferably 2 atomic% to 6 atomic%.

  Next, as shown in FIG. 2 (c), a cleaning solution that selectively dissolves Mn with respect to Cu is supplied to the surface of the substrate 11 in a state where the alloy layer 17 is provided. The Mn is dissolved in the cleaning solution and removed (S104). Here, in the heat treatment performed in the post-process described above, not all Mn in the alloy layer 17 is segregated at the interface with the interlayer insulating films 12 and 15 but also segregated on the surface of the conductive layer. Therefore, Mn on the surface side of the alloy layer 17 diffuses toward the surface of the conductive layer 18 without contributing to the formation of the self-forming barrier film, but Mn that has not been segregated on the surface of the conductive layer 18 is It remains in the conductive layer in the wiring groove 16 and causes an increase in wiring resistance. For this reason, in this embodiment, the Mn on the surface side of the alloy layer 17 is removed in advance to prevent surplus Mn that does not contribute to the formation of the self-forming barrier film from remaining in the conductive layer.

  Here, as shown in the Ellingham diagram of Mn in FIG. 3, the Mn film is soluble in a wide range of neutral to acidic cleaning solutions in the absence of an electric field. On the other hand, as shown in the Cu Ellingham diagram of FIG. 4, the Cu film is oxidized from the neutral side to the alkaline side in the non-electric field state.

  Therefore, as shown in FIG. 2C again, by supplying a neutral to acidic cleaning solution, only Mn on the surface side of the alloy layer 17 is selectively dissolved in the cleaning solution. Here, for example, it is washed with a 4 vol% hydrofluoric acid aqueous solution for several seconds to several minutes (preferably 1 minute or less) to elute Mn on the surface side of the alloy layer 17. When the concentration of the hydrofluoric acid aqueous solution is 1 vol% or more, Mn on the surface side of the alloy layer 17 can be eluted.

  Here, although the hydrofluoric acid aqueous solution is used as the cleaning liquid, it is sufficient if Mn on the surface side of the alloy layer 17 can be selectively eluted with respect to Cu. For example, carbonic acid, acetic acid, citric acid, etc. An aqueous solution of The diluent, additive, treatment time, and treatment temperature can be freely selected as long as the selection ratio of Cu and Mn can be several tens of percent or more.

  Further, by eluting Mn on the surface side of the alloy layer 17, the Cu content of the surface layer 17 a of the alloy layer 17 becomes higher than that on the interlayer insulating films 12 and 15 side. For this reason, the sheet resistance of the alloy layer 17 is reduced, and the load on the plating process performed in the subsequent process is reduced.

  Next, as shown in FIG. 5D, a conductive layer 18 made of, for example, pure Cu is formed with a film thickness of 800 nm or more on the alloy layer 17 in a state where the wiring groove 16 is embedded, for example, by electrolytic plating. S105). Here, an example in which the conductive layer 18 is made of pure Cu will be described. However, the conductive layer 18 may be a film containing Cu as a main component, for example, copper silver (CuAg) with a small increase in specific resistance. ) Alloys may be used.

  Thereafter, as shown in FIG. 5 (e), for example, heat treatment is performed at 300 ° C. for 30 minutes, so that Mn in the alloy layer 17 (see FIG. 5 (d)) is converted into constituent components of the interlayer insulating films 12 and 15. To form a self-forming barrier film 19 made of a Mn compound having a Cu diffusion preventing property at the interface between the alloy layer 17 and the interlayer insulating films 12 and 15 (S106). Here, the temperature range and the processing time of the heat treatment for forming the self-forming barrier film 19 promote the reliable formation of the self-forming barrier film 19 and prevent adverse effects on the device due to the heat treatment. It is preferably 60 seconds to 2 hours, more preferably 60 seconds to 30 minutes. The constituent components of the interlayer insulating films 12 and 15 include oxygen or moisture from the atmosphere adsorbed on the surfaces of the interlayer insulating films 12 and 15.

Here, since the interlayer insulating films 12 and 15 are made of SiO ₂ , the self-forming barrier film 19 is made of Mn such as silicon-containing Mn oxide (MnSi _x O _y ) or Mn oxide (Mn _x O _y ). It is composed of a compound and is formed with a film thickness of 2 nm to 3 nm. At this time, Mn is segregated also on the surface side of the conductive layer 18 to form the MnO layer M. Moreover, Cu in the conductive layer 18 is grain-grown by this heat treatment.

  Thereafter, as shown in FIG. 5 (f), two-step polishing is performed by, for example, CMP, and in the first step, unnecessary portions of the conductive pattern as a wiring pattern are formed together with the MnO layer M (see FIG. 5 (e)). The layer 18 (see FIG. 5E) is removed. Subsequently, in the second stage polishing, the self-formed barrier film 19 is removed, and the exposed interlayer insulating film 15 is etched away by 100 nm, thereby forming a wiring 18 ′ communicating with the via 14 in the wiring groove 16 ( S107).

Then, by performing the organic acid cleaning using aqueous citric acid and oxalic acid aqueous solution or the like, a corrosion inhibitor Cu benzotriazole derivatives remaining on the surface 'wiring 18 with an oxide film and the CMP process on the' wiring 18 Remove. Thereafter, on the wiring 18 ′ and the interlayer insulating film 15, for example, from silicon carbonitride (SiCN) by a CVD method using a silicon-containing material such as trimethylsilane (3MS) and ammonia (NH ₃ ) as a film forming gas. The cap film 20 to be formed is formed with a film thickness of 50 nm.

  According to such a method of manufacturing a semiconductor device, a cleaning solution that selectively dissolves Mn with respect to Cu is supplied to the surface of the substrate 11 in a state where the alloy layer 17 is provided. Since Mn is dissolved and removed in the cleaning liquid, excess Mn that does not contribute to the formation of the self-forming barrier film 19 is removed in advance. As a result, an increase in wiring resistance due to Mn remaining in the wiring 18 ′ embedded in the wiring groove 16 is suppressed, so that RC delay can be suppressed. Therefore, a semiconductor device having a high-performance and highly reliable multilayer wiring can be manufactured.

Here, the example in which the interlayer insulating films 12 and 15 are formed of SiO ₂ has been described. However, the present invention is not limited to this. For example, the interlayer insulating films 12 and 15 are formed of a low dielectric constant film having a relative dielectric constant lower than that of SiO _2. Alternatively, a hybrid structure including an organic insulating film and an inorganic insulating film may be used.

(Second Embodiment)
Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional views of FIGS. In addition, the same number is attached | subjected and demonstrated to the structure similar to 1st Embodiment. In addition, the steps (S201 to S203) for forming an alloy layer made of CuMn are performed in the same manner as the steps described with reference to FIGS. 1A to 1B in the first embodiment.

  First, as shown in FIG. 7A, in the state where the alloy layer 17 is provided in the wiring groove 16, as shown in FIG. (See FIG. 7 (a)). Mn in the interlayer insulating films 12 and 15 is reacted with Mn in the self-formed barrier film made of a Mn compound at the interface between the alloy layer 17 and the interlayer insulating films 12 and 15. 19 is formed. At this time, Mn is segregated also on the surface of the alloy layer 17, and the MnO layer M is formed (S204). As a result, as compared with the case where the heat treatment is performed after the conductive layer is embedded in the wiring groove 16, the excess Mn that does not contribute to the formation of the self-formed barrier film 19 is reduced by the distance to the surface of the alloy layer 17. Segregated reliably on the surface. Thereby, the alloy layer 17 ′ after the heat treatment has a higher Cu content than before the heat treatment.

  Next, as shown in FIG. 7C, the MnO layer M (see FIG. 7B) is selectively formed with respect to Cu on the surface of the base substrate 11 in a state where the heat-treated alloy layer 17 ′ is provided. A cleaning solution for dissolving (see) is supplied, and the MnO layer M on the surface side of the alloy layer 17 ′ is dissolved in this cleaning solution and removed (S205). As a result, the surface of the alloy layer 17 ′ is exposed on the inner wall of the wiring groove 16. Here, as the cleaning liquid, the cleaning liquid exemplified in the first embodiment can be used. Here, the cleaning liquid is cleaned with, for example, 4 vol% hydrofluoric acid aqueous solution for several seconds to several minutes. As a result, surplus Mn that has not contributed to the formation of the self-forming barrier film 19 is segregated on the surface of the alloy layer 17 ′, so that surplus Mn can be reliably removed.

  Thereafter, as shown in FIG. 8D, a conductive layer 18 made of, for example, pure Cu is formed with a film thickness of 800 nm or more on the alloy layer 17 ′ in a state where the wiring groove 16 is embedded, for example, by electrolytic plating. (S206). At this time, since the alloy layer 17 'has a higher Cu content than the alloy layer 17 before heat treatment (see FIG. 7A), the sheet resistance is suppressed and the load applied to the plating process is reduced. Subsequently, Cu in the conductive layer 18 is grain-grown by performing heat treatment in a temperature range of 150 ° C. to 250 ° C. (S207).

  The subsequent steps are performed in the same manner as in the first embodiment. That is, as shown in FIG. 8E, two-step polishing is performed by, for example, a CMP method, and unnecessary portions of the conductive layer 18 as a wiring pattern (see FIG. 8D) and the self-formed barrier film 19 are formed. And the exposed interlayer insulating film 15 is etched away. As a result, a wiring 18 ′ communicating with the via 14 is formed in the wiring groove 16 (S 208).

  Next, by performing organic acid cleaning, the oxide film on the wiring 18 ′ and the Cu anticorrosive remaining on the surface of the wiring 18 ′ are removed. Thereafter, a cap film 20 made of, for example, SiCN is formed on the wiring 18 ′ and the interlayer insulating film 15 with a film thickness of 50 nm.

  Even in such a method of manufacturing a semiconductor device, a cleaning solution that selectively dissolves Mn in the alloy layer 17 with respect to Cu is formed on the surface of the substrate 11 in a state where the alloy layer 17 ′ after the heat treatment is provided. Since the Mn on the surface side of the alloy layer 17 is supplied and dissolved in the cleaning liquid, the excess Mn that does not contribute to the formation of the self-forming barrier film 19 can be removed. Thereby, an increase in wiring resistance due to Mn remaining in the wiring 18 ′ embedded in the wiring trench 16 is suppressed. Therefore, the same effect as the first embodiment can be obtained.

  In addition, according to the method of manufacturing a semiconductor device of this embodiment, the self-formed barrier film is closer to the surface of the alloy layer 17 than the case where the heat treatment is performed after the conductive layer 18 is embedded in the wiring groove 16. Excess Mn that does not contribute to the formation of 19 is reliably segregated on the surface of the alloy layer 17. Further, since the MnO layer M is selectively cleaned after the self-forming barrier film 19 is formed, the excess Mn can be removed more reliably.

Here, in the process described with reference to FIG. 7B in the second embodiment, the result of comparing the Mn concentration on the surface of the alloy layer 17 before and after the heat treatment is shown in FIG. FIG. 9B shows the result of comparing the Mn concentration at the interface with the insulating films 12 and 15 before and after the heat treatment. In these graphs, the horizontal axis indicates the time during which argon ion (Ar ⁺ ) sputtering is performed from the surface side of the alloy layer 17, and the vertical axis indicates the Mn concentration along the same number axis. Also from this result, it was confirmed that Mn in the alloy layer 17 segregates at the interface between the surface and the interlayer insulating films 12 and 15 after the heat treatment.

(Third embodiment)
Next, a third embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process sectional views of FIGS. 11 and 12, based on the flowchart of FIG. In addition, the same number is attached | subjected and demonstrated to the structure similar to 1st Embodiment. In addition, the steps (S301 to S303) until the alloy layer 17 is formed are performed in the same manner as the steps described with reference to FIGS. 1A to 1B in the first embodiment.

First, as shown in FIG. 11A, a sacrificial insulating film 21 made of, for example, SiO ₂ is formed on the alloy layer 17 provided so as to cover the inner wall of the wiring trench 16 (S304). Here, when the heat treatment is performed in a state where the surface of the alloy layer 17 is exposed, the surface of the alloy layer 17 and the interface between the interlayer insulating films 12 and 15 also have the interlayer insulating film 12, Since about the same amount of Mn as that of the 15 interface is segregated, about half of the Mn contained in the alloy layer 17 is deposited on the surface side unrelated to the formation of a self-forming barrier film described later. For this reason, in this embodiment, by performing heat treatment in a state where the sacrificial insulating film 21 is formed on the alloy layer 17 in a subsequent process, Mn segregated on the surface of the alloy layer 17 is suppressed, and the interlayer insulating film is further increased. Mn is segregated at the interface with 12 and 15.

Here, since the Mn is segregated at the interface between the alloy layer 17 and the interlayer insulating films 12 and 15, the insulating film used as the sacrificial insulating film 21 is preferably formed of a material that does not easily segregate Mn. In particular, the non-porous insulating film is preferably formed of a non-porous insulating film because Mn is not easily segregated because the porous insulating film (porous film) has less surface roughness. As such a film, there is an SiN film in addition to the above-described SiO ₂ film. However, it is preferable to use a SiO ₂ film as the sacrificial insulating film 21 because it can be easily removed during a cleaning process performed in a later process. In addition to the above, it is preferable to form the interlayer insulating films 12 and 15 with a material in which Mn is easily segregated. Specifically, it is preferable to use a porous insulating film.

Next, as shown in FIG. 11B, for example, by performing a heat treatment at 300 ° C. for 30 minutes, the Mn in the alloy layer 17 reacts with the constituent components of the interlayer insulating films 12 and 15, and the alloy layer 17 ( A self-forming barrier film 19 made of a Mn compound is formed at the interface between the interlayer insulating films 12 and 15 (see FIG. 11A). At this time, since Mn in the alloy layer 17 also reacts with the constituent components of the sacrificial insulating film 21, a Mn compound layer M ′ is also formed at the interface between the alloy layer 17 and the sacrificial insulating film 21 (S305). Here, since the sacrificial insulating film 21 is composed of SiO ₂ , the Mn compound film M ′ is formed of silicon-containing Mn oxide (MnSi _x O _y ) or Mn oxide (Mn _x O _y ). . Further, in the alloy layer 17 ′ after the heat treatment, Mn is segregated at the interface and the surface with the interlayer insulating films 12 and 15, so that the Cu content is higher than that in the alloy layer 17 before the heat treatment.

Next, as shown in FIG. 11C, a cleaning solution for selectively dissolving the Mn compound and the sacrificial insulating film 21 made of SiO ₂ with respect to Cu is supplied, and the sacrificial insulating film 21 (see FIG. 11B) is supplied. )) And the Mn compound layer M ′ (see FIG. 11B) are dissolved in the cleaning liquid and removed (S306). As a result, the surface of the alloy layer 17 ′ is exposed on the inner wall of the wiring groove 16. As this cleaning liquid, for example, a hydrofluoric acid aqueous solution can be used. Here, for example, by performing a cleaning process using a 4 vol% hydrofluoric acid aqueous solution for several seconds to several minutes, the sacrificial insulating film 21 and the Mn compound film M ′ can be used. Remove.

  The subsequent steps are performed in the same manner as the steps described with reference to FIGS. 8D to 8E in the second embodiment. That is, as shown in FIG. 12D, a conductive layer 18 made of pure Cu is formed with a film thickness of 800 nm or more on the alloy layer 17 ′ in a state of embedding the wiring groove 16 by electrolytic plating (S307). ). Subsequently, Cu in the conductive layer 18 is grain-grown by performing heat treatment in a temperature range of 150 ° C. to 250 ° C. (S308).

  Subsequently, as shown in FIG. 12E, two-step polishing is performed by, for example, a CMP method, and the conductive layer 18 and the self-formed barrier film 19 which are not necessary as a wiring pattern are removed and exposed. By cutting the interlayer insulating film 15, a wiring 18 ′ communicating with the via 14 is formed in the wiring groove 16 (S 309).

  Thereafter, organic acid cleaning is performed to remove the oxide film on the wiring 18 ′ and the Cu anticorrosive remaining on the surface of the wiring 18 ′. Thereafter, a cap film 20 made of, for example, SiCN is formed to a thickness of 50 nm on the wiring 18 ′ and the interlayer insulating film 15.

  Even in such a method for manufacturing a semiconductor device, by performing heat treatment in a state where the sacrificial insulating film 21 is formed on the alloy layer 17, a self-forming barrier is formed at the interface between the alloy layer 17 and the interlayer insulating films 12 and 15. After forming the film 19 and forming the Mn compound film M ′ at the interface between the alloy layer 17 and the sacrificial insulating film 21, the Mn compound layer M ′ together with the sacrificial insulating film 21 is selectively removed with respect to Cu. Thus, excess Mn that does not contribute to the formation of the self-forming barrier film 19 can be removed. Thereby, an increase in wiring resistance due to Mn remaining in the wiring 18 ′ embedded in the wiring groove 16 is suppressed. Therefore, the same effect as that of the first embodiment can be obtained.

  Further, according to the method for manufacturing a semiconductor device of the present embodiment, Mn is formed at the interface between the alloy layer 17 and the interlayer insulating films 12 and 15 by performing heat treatment in a state where the sacrificial insulating film 21 is formed on the alloy layer 17. Can be easily segregated, and the formation of the self-forming barrier film 19 can be promoted.

Here, the relationship between the type of the base insulating film and the Mn concentration segregated at the interface between the alloy layer and the base insulating film by the heat treatment is shown in the graph of FIG. In the graph, the horizontal axis indicates the time for performing argon ion (Ar ⁺ ) sputtering from the surface side of the alloy layer, and the vertical axis indicates the Mn concentration. Here, a comparison is made using a non-porous SiO ₂ film (1), a non-porous SiN film (2), and a porous polyaryl ether (porous PAE) film (3) as the base insulating film. did. As a result, it was confirmed that the segregation concentration of Mn was significantly lower in the non-porous SiO ₂ film and SiN film as compared with the segregation concentration of Mn when the porous PAE film (3) was used. Therefore, it was suggested that the sacrificial insulating film 21 (see FIG. 11A) is preferably an SiO ₂ film or an SiN film rather than a porous PAE film.

(Fourth embodiment)
Next, a fourth embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional views of FIGS. In addition, the same number is attached | subjected and demonstrated to the structure similar to 1st Embodiment. Further, the steps (S401 to S403) until the alloy layer 17 is formed are performed in the same manner as the steps described with reference to FIGS. 1A to 1B in the first embodiment.

  First, as shown in FIG. 15A, a conductive layer 18a made of pure Cu is formed on the alloy layer 17 by, for example, electrolytic plating, with the wiring groove 16 buried partway (S404). In this embodiment, since the surface cleaning of the alloy layer 17 and the heat treatment in the state where the alloy layer 17 is exposed are not performed, the morphology of the alloy layer 17 is maintained as compared with other embodiments. Here, although the conductive layer 18a is formed by the electrolytic plating method, it may be formed by the sputtering method.

  Next, as shown in FIG. 15B, for example, by performing a heat treatment at 300 ° C. for 30 minutes, Mn in the alloy layer 17 reacts with the constituent components of the interlayer insulating films 12 and 15, and the alloy layer 17 A self-forming barrier film 19 made of a Mn compound is formed at the interface between the insulating film 12 and the interlayer insulating films 12 and 15. At this time, Mn in the alloy layer 17 is also segregated on the surface of the conductive layer 18a to form the MnO layer M (S405). This contributes to the formation of the self-forming barrier film 19 on the surface of the conductive layer 18a because the distance to the surface of the conductive layer 18a is shorter than the case where the heat treatment is performed after the wiring trench 16 is completely filled with the conductive layer. Mn that is not segregated reliably.

  Next, as shown in FIG. 15C, the MnO layer M (see FIG. 15B) is selectively dissolved with respect to Cu on the surface of the substrate 11 provided with the heat-treated conductive layer 18a. The MnO layer M is dissolved and removed in the cleaning solution (S406). As this cleaning liquid, those exemplified in the first embodiment can be used. Here, for example, the MnO layer M is removed and the surface of the conductive layer 18a is exposed by performing treatment for several seconds to several minutes using a 4 vol% hydrofluoric acid aqueous solution.

  Thereafter, as shown in FIG. 16D, the conductive layer 18 made of pure Cu is formed on the conductive layer 18a in a state where the wiring groove 16 is embedded, for example, by electrolytic plating (S407). Here, the total film thickness including the conductive layer 18a is set to be 800 nm or more. Subsequently, a heat treatment is performed in a temperature range of 150 ° C. to 250 ° C., whereby Cu in the conductive layer 18 is grain-grown (S408).

  Subsequently, as shown in FIG. 16E, two-step polishing is performed by, for example, a CMP method, and the conductive layer 18 and the self-formed barrier film 19 which are not necessary as a wiring pattern are removed and exposed. By cutting the interlayer insulating film 15, a wiring 18 ′ communicating with the via 14 is formed in the wiring groove 16 (S 409).

  Thereafter, an organic acid cleaning is performed to remove the oxide film on the wiring 18 ′ and the Cu anticorrosive remaining on the surface of the wiring 18 ′. Thereafter, a cap film 20 made of, for example, SiCN is formed on the wiring 18 ′ and the interlayer insulating film 15 with a film thickness of 50 nm.

  Even in such a method of manufacturing a semiconductor device, a self-formed barrier film 19 is formed at the interface between the alloy layer 17 and the interlayer insulating films 12 and 15 by performing a heat treatment after forming the conductive layer 18a on the alloy layer 17. After forming the MnO layer M on the surface of the conductive layer 18a, the MnO layer M is selectively removed with respect to Cu, so that excess Mn that does not contribute to the formation of the self-forming barrier film 19 is removed. can do. Thereby, an increase in wiring resistance due to Mn remaining in the wiring 18 ′ embedded in the wiring groove 16 is suppressed. Therefore, the same effect as that of the first embodiment can be obtained.

  Next, a fifth embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to manufacturing process cross-sectional views of FIGS. Here, an example in which a dual damascene wiring structure is formed in the upper layer of the cap film 20 described in the first embodiment will be described.

First, as shown in FIG. 17A, an interlayer insulating film 22 made of, for example, SiO ₂ is formed to a thickness of 700 nm on the cap film 20 by, eg, PE-CVD. Subsequently, a resist pattern (not shown) having a connection hole pattern is formed on the interlayer insulating film 22, and a connection hole 23a reaching the cap film 20 is formed by etching using this resist pattern as a mask.

  Next, as illustrated in FIG. 17B, a resist R is applied on the interlayer insulating film 22 in a state where the connection hole 23 a is embedded. Subsequently, an SOG (Spin On Glass) film is formed on the resist R, a resist pattern (not shown) having a wiring groove pattern is formed on the SOG film, and then SOG is performed by etching using the resist pattern as a mask. The hard mask 24 is formed by processing the film.

  Next, as shown in FIG. 17C, the resist R (see FIG. 17B) is processed by etching using the hard mask 23 as a mask to form a resist pattern R ′ having a wiring groove pattern. To do. Further, the resist R covering the bottom side of the connection hole 23a is left.

  Subsequently, as shown in FIG. 18D, a connection hole is formed on the upper side of the interlayer insulating film 22 by etching using the hard mask 24 (see FIG. 17C) and the resist pattern R ′ as a mask. A wiring groove 23b in a state of communicating with 23a is formed. As a result, a dual damascene opening 23 (concave portion) is formed which includes the wiring groove 23b and the connection hole 23a communicating with the bottom thereof. At this time, the depth of the wiring groove 23b is controlled by controlling the etching time. Here, the opening width of the connection hole 23a is 75 nm, the depth is 110 nm, the opening width of the wiring groove 23b is 75 nm to 100 nm, and the depth is 150 nm. Further, by leaving the resist R inside the connection hole 23a, the side wall of the connection hole 23a is prevented from being etched, and the side wall is kept vertical.

  Thereafter, as shown in FIG. 18E, the resist pattern R ′ (see FIG. 18D) and the resist R (see FIG. 18D) are removed by ashing and chemical cleaning, and then connected. The cap film 20 at the bottom of the hole 23a is exposed.

  Next, as shown in FIG. 18F, the cap film 20 at the bottom of the connection hole 23a is removed to expose the surface of the wiring 18 '.

  Next, as shown in FIG. 19G, an alloy layer 25 made of CuMn is formed on the interlayer insulating film 22 so as to cover the inner wall of the dual damascene opening 23 by, eg, sputtering.

  Subsequently, as shown in FIG. 19 (h), as in the first embodiment, a cleaning solution that selectively dissolves Mn with respect to Cu is supplied to the surface of the substrate 11 in a state where the alloy layer 25 is provided. Then, Mn on the surface side of the alloy layer 25 is dissolved in this cleaning solution and removed.

  Thereafter, as shown in FIG. 19I, a conductive layer 26 made of, for example, pure Cu is formed on the alloy layer 25 in a state where the dual damascene opening 23 is embedded.

Next, as shown in FIG. 20 (j), for example, by performing a heat treatment at 300 ° C. for 30 minutes, Mn in the alloy layer 25 (see FIG. 19 (i)) is converted into a component of the interlayer insulating film 22. By reacting, a self-forming barrier film 27 made of a Mn compound is formed between the alloy layer 25 and the interlayer insulating film 22. Here, as in the first embodiment, since the interlayer insulating film 22 is made of SiO ₂ , the self-forming barrier film 27 is made of silicon-containing Mn oxide (MnSi _x O _y ) or Mn oxide (Mn _x consists of O _y), is formed in a thickness of 2 nm to 3 nm. By this heat treatment, Mn is segregated also on the surface of the conductive layer 26, and the MnO layer M is formed.

  Thereafter, as shown in FIG. 20 (k), two-step polishing is performed by, for example, CMP, and in the first step, unnecessary portions of the conductive pattern as a wiring pattern are formed together with the MnO layer M (see FIG. 20 (j)). The layer 26 (see FIG. 20J) is removed. Subsequently, in the second stage polishing, the self-formed barrier film 27 is removed, and the exposed interlayer insulating film 22 is etched by 100 nm. As a result, a via 26a 'in communication with the wiring 18' is formed in the connection hole 23a, and a wiring 26b 'is formed in the wiring groove 23b.

  Next, by performing organic acid cleaning, the oxide film on the wiring 26b 'and the Cu anticorrosive remaining on the surface of the wiring 26b' are removed. Thereafter, a cap film 28 made of, for example, SiCN is formed to a thickness of 50 nm on the wiring 26 b ′ and the interlayer insulating film 22.

  Even in such a method of manufacturing a semiconductor device, as described with reference to FIG. 19H, a cleaning solution that selectively dissolves Mn into Cu in the substrate 11 in a state where the alloy layer 25 is provided. Since the Mn on the surface side of the alloy layer 25 is removed, the same effect as in the first embodiment can be obtained.

In the above-described first to fifth embodiments, the example in which the alloy layers 17 and 25 are made of CuMn has been described. However, as the metal other than Cu constituting the alloy layers 17 and 25, the above-described Mn In addition, for example, aluminum (Al), zinc (Zn), chromium (Cr), vanadium (V), titanium (Ti), and tantalum (Ta) can be exemplified. For example, when the alloy layers 17 and 25 are made of CuAl, for example, silicon-containing Al oxide (AlSi _x O _y ) or Al oxide (Al _x O _y ) is formed as the self-forming barrier films 19 and 27, When the alloy layers 17 and 25 are made of CuZn, for example, silicon-containing Zn oxide (ZnSi _x O _y ) or Zn oxide (Zn _x O _y ) is formed as the self-forming barrier film 19. Similar silicon compounds or oxides are formed for the other metals exemplified above.

Further, in this embodiment, as the Mn compound constituting the self-forming barrier films 19 and 27, silicon-containing Mn oxide (MnSi _x O _y ) or Mn oxide (Mn _x O _y ) is exemplified, but the interlayer insulating film When 12, 15, 22 is an insulating film containing carbon such as an organic insulating film, for example, Mn carbide (Mn _x C _y ) is formed as the Mn compound constituting the self-forming barrier films 19 and 27. In some cases. When the above-described CuAl or CuTi is used as the alloy layers 17 and 25, Al carbide (Al _x C _y ) or titanium carbide (Ti _x C _y ) may be formed. Further, similar metal carbides are formed for the other metals exemplified above.

3 is a flowchart for explaining a first embodiment of the method for producing a semiconductor device of the present invention. FIG. 6 is a manufacturing process cross-sectional view (No. 1) for describing the first embodiment of the semiconductor device manufacturing method of the present invention; It is an Ellingham figure of Mn. It is an Ellingham figure of Cu. FIG. 6 is a manufacturing process sectional view (No. 2) for describing the first embodiment of the manufacturing method of the semiconductor device of the invention; It is a flowchart for demonstrating 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 1) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 2) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. These are the Mn concentration (a) on the surface of the alloy layer before and after the heat treatment and the Mn concentration (b) at the interface between the alloy layer and the interlayer insulating film before and after the heat treatment. It is a flowchart for demonstrating 3rd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing for demonstrating 3rd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention (the 1). It is manufacturing process sectional drawing (the 2) for demonstrating 3rd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is a graph which shows the relationship between the kind of base insulating film, and Mn segregation density | concentration. It is a flowchart for demonstrating 4th Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 1) for describing 4th Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 2) for describing 4th Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 1) for describing 5th Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 2) for describing 5th Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 3) for demonstrating 5th Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 4) for demonstrating 5th Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 12, 15, 22 ... Interlayer insulation film, 16, 23b ... Wiring groove, 17, 25 ... Alloy layer, 17 '... Alloy layer (after heat processing), 18, 26 ... Conductive layer, 19, 27 ... Self Forming barrier film, 21 ... Sacrificial insulating film

Claims (3)

A first step of forming the recess in the insulating film provided on the substrate;
A second step of forming an alloy layer made of copper and a metal other than copper in a state of covering the inner wall of the recess;
Heat treatment is performed to cause the metal in the alloy layer to react with the constituent components of the insulating film, thereby forming a barrier film made of a metal compound having copper diffusion preventing properties at the interface between the alloy layer and the insulating film A third step to perform,
And a fourth step of embedding a conductive layer containing copper as a main component in the recess provided with the barrier film,
Between the second step and the third step or between the third step and the fourth step,
Supplying a cleaning solution that selectively dissolves the metal or a compound containing the metal with respect to copper on the surface of the substrate, and dissolving and removing the metal that does not contribute to the formation of the barrier film in the cleaning solution; A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
Performing a step of forming a sacrificial insulating film on the alloy layer between the second step and the third step;
In the third step, the barrier film is formed, and the metal in the alloy layer is reacted with a component of the sacrificial insulating film, so that a metal compound layer is formed at the interface between the alloy layer and the sacrificial insulating film. And forming
A cleaning solution that selectively dissolves the sacrificial insulating film and the metal compound layer with respect to copper is supplied to the surface of the substrate between the third step and the fourth step, together with the sacrificial insulating film. A process for removing the metal compound layer by dissolving the metal compound layer in the cleaning solution. In the manufacturing method of the semiconductor device according to claim 1,
Between the second step and the third step, a step of embedding a conductive layer mainly composed of copper in the concave portion halfway,
A method of manufacturing a semiconductor device, wherein a step of removing the metal is performed between the third step and the fourth step.

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