JP2007335578A - Semiconductor device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having high reliability, and to provide a manufacturing method of the semiconductor device with a good yield. <P>SOLUTION: The manufacturing method of the semiconductor device comprises a process (a) for forming a wiring material film 5 buried in a first interlayer insulating film 1, and provided with a first cap metal 6 on the upper surface thereof; a process (b) for forming a groove 10 and a via hole 9 on a second interlayer insulating film 8 provided above the wiring material film 5; a process (c) for forming a barrier metal 11 in the inner surfaces of the groove 10 and the via hole 9; a process (d) for removing the part of the barrier metal 11 positioned on the bottom of the via hole 9, and a part of the wiring material film 5 and the first cap metal 6; and a process (f) for forming a second cap metal 21 on the upper surface of the wiring material film 5. Even when the oxide film of a metal strong in a coupling force with oxygen is formed on the upper surface of the wiring material film 5, the oxide of the metal can be removed in the process (d). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a metal wiring having a trench filling structure and an interlayer insulating film, and a method for manufacturing the same.

  In recent years, the wiring pitch of devices has been reduced, and it has become increasingly important to ensure the reliability of wiring. For this reason, studies have been made to improve the reliability by forming a cap metal on the upper surface of the wiring, and to improve the reliability by adding various elements to the copper wiring.

  Hereinafter, a conventional method for forming a buried wiring will be described with reference to FIGS. 4A to 4E and FIGS. 5A to 5E are cross-sectional views showing a conventional wiring forming method.

  First, as shown in FIG. 4A, a lithography process and an etching process are performed, and a first wiring is formed on a first interlayer insulating film 101 made of a low dielectric constant material provided on a substrate (not shown). A groove 102 is formed. Next, as a pretreatment, the substrate (semiconductor device being manufactured) is annealed in a hydrogen atmosphere at 280 ° C. for 60 seconds to reduce the oxide on the surface of the substrate, and then the first barrier metal 103 has a film thickness. A 5 nm tantalum nitride film and a 10 nm thick tantalum film are sequentially formed. Here, the first barrier metal 103 is a metal film for preventing copper as a wiring material from diffusing into the first interlayer insulating film 101 on the outer periphery thereof.

  Next, as shown in FIG. 4B, a first seed film 104 having a thickness of 40 nm is formed on the first barrier metal 103. Here, copper containing 1% aluminum (Al) is used for the first seed film 104. The reason why the metal is added to the copper is to suppress the occurrence of electromigration and stress migration and improve the reliability of the semiconductor device.

  Next, as shown in FIG. 4C, copper is buried in the first wiring trench 102 by a plating method to form a copper film 105 on the first seed film 104, and then the copper film 105 and the first seed are formed. A portion of the film 104 and the first barrier metal 103 formed outside the first wiring trench 102 is removed by a chemical mechanical polishing (CMP) method to form a first wiring.

  Subsequently, as shown in FIG. 4D, after the pretreatment of the upper surface of the wiring is performed using a chemical solution containing dilute hydrofluoric acid as a main component, the cap metal 106 is formed only on the upper surface of the wiring by selective plating. Tungsten cobalt phosphide (WCoP) having a thickness of about 10 nm is formed. The reason why the cap metal is formed on the upper surface of the first wiring is to suppress the occurrence of problems such as electromigration and stress migration and further improve the reliability of the semiconductor device.

  Next, as shown in FIG. 4E, a liner film 107 having a thickness of about 60 nm is formed on the first wiring and the first interlayer insulating film 101. Here, the liner film 107 is for preventing the copper contained in the first wiring from diffusing into the second interlayer insulating film 108 to be formed later, and the first interlayer insulating film 101. A silicon nitride film, a silicon carbide film, or the like having a relatively high relative dielectric constant compared to the above is used.

  Next, as shown in FIG. 5A, a second interlayer insulating film 108 made of a low dielectric constant material is formed on the liner film 107.

  Next, as shown in FIG. 5B, by repeating the lithography process and the etching process, the second wiring groove 110 and the cap from the bottom of the second wiring groove 110 are formed in the second interlayer insulating film 108. A via hole 109 reaching the metal 106 is formed.

  Next, as shown in FIG. 5C, after the substrate is pretreated by annealing in a hydrogen atmosphere at 280 ° C. for 60 seconds to remove the oxide on the cap metal 106, the second barrier metal 111 is removed. A tantalum nitride film having a thickness of 5 nm and a tantalum film having a thickness of 10 nm are sequentially formed.

  Subsequently, as shown in FIG. 5D, a second seed film 112 having a thickness of about 40 nm is formed on the second barrier metal 111. Here, like the first seed film 104, the second seed film 112 is made of copper containing 1% Al.

Next, as shown in FIG. 5E, copper is buried in the via hole 109 and the second wiring groove 110 by plating to form a copper film 113 on the second seed film 112. Thereafter, portions of the copper film 113, the second seed film 112, and the second barrier metal 111 that are formed outside the via hole 109 and the second wiring trench 110 are removed by a CMP method, and the plug and the second Form wiring. Here, the plug means a portion of the second barrier metal 111, the second seed film 112, and the copper film 113 embedded in the via hole 109, and the second wiring means the second barrier metal 111. This means a portion of the second seed film 112 and the copper film 113 embedded in the second wiring trench 110.
Thin Solid Films, 25 (1975) 531-544

  However, the above-described conventional semiconductor device has a problem in that the resistance value of the plug may increase, resulting in a decrease in the yield of the semiconductor device.

  FIG. 6 is a diagram showing a cumulative frequency distribution of via resistance values (resistance values between wiring and plugs) when a multilayer embedded wiring is formed by a conventional method.

By design, the via resistance values should all be 2 × 10 ⁷ Ω or less. However, the results shown in FIG. 6 show that the distribution of via resistance values is broad and the via resistance is increased. As a result of various studies on the cause by the present inventor, it has been found that the increase in via resistance is caused by insufficient removal of Al oxide formed on the copper wiring.

  FIG. 7 is a cross-sectional view for explaining an estimation mechanism in which the resistance between the wiring and the plug increases in the conventional method. When the conventional manufacturing method is used, Al contained in the first seed film 104 is diffused into the copper film 105 by heat applied after forming the first wiring, thereby forming a Cu—Al alloy. In particular, after the formation of the via hole 109 (see FIG. 5B), it combines with oxygen in the atmosphere, and not only the Cu oxide film but also the Al oxide film 114 is formed on the upper surface of the copper film 105 and the first seed film. It is estimated that it is also formed on the upper end surface of 104. Since the Al oxide has much higher intermolecular bond energy than the Cu oxide, it cannot be reduced by annealing in a hydrogen atmosphere before the second barrier metal 111 is formed. Therefore, it is considered that the Al oxide film 114 formed on the first wiring cannot be removed, and the resistance value between the wiring and the plug is increased.

  The present invention solves these problems, and an object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the semiconductor device with a high yield.

  In order to solve the above problems, the inventors of the present application have made researches. As a result, the metal added to the seed film forms an oxide on the first wiring, and the metal oxide is not sufficiently removed. It turned out to be the cause.

  Therefore, the present invention provides a structure of a semiconductor device and a manufacturing method that can suppress the formation of oxide or remove the oxide.

  That is, the semiconductor device of the present invention includes a semiconductor substrate, a first interlayer insulating film provided on the semiconductor substrate, in which the first groove is formed, and embedded in the first groove, and a recess is formed on the upper surface. A first wiring, an insulating film provided on the first interlayer insulating film, in which a via hole and a second groove are formed, a plug embedded in the via hole and in contact with at least a recess of the first wiring; A second wiring connected to the plug and embedded in the second groove, the first wiring extending along the first wiring material film in which the concave portion is formed, and the concave portion of the first wiring material film. And a cap metal film provided.

  According to this configuration, since the cap metal is provided along the concave portion of the first wiring material film, the occurrence of electromigration and stress migration is suppressed. Further, since the plug is provided so as to be fitted in the recess of the first wiring, the contact resistance between the first wiring and the plug is reduced. Therefore, high reliability is realized in the semiconductor device of the present invention.

  The first wiring covers the first barrier film covering the inner surface of the first groove, the side surface and the bottom surface of the first wiring material film, and the first seed film provided on the first barrier film Further, it is preferable that the first wiring material film can be formed by plating at the time of manufacture. If the first barrier film contains a metal (for example, Al, Mg, Zn, Fe, Sn, Ti, etc.) that has copper as a main component and has a larger binding energy with oxygen than copper, for example, Wiring resistance can be reduced and the occurrence of electromigration and stress migration can be suppressed.

  For example, copper or the like is used as the first wiring material film.

  The cap metal film is preferably a substance containing Co. For example, WCoP or WCoB is used as the material.

  The method of manufacturing a semiconductor device according to the present invention includes a step (a) of forming a wiring material film embedded in an interlayer insulating film formed on a semiconductor substrate, and forming an insulating film on the wiring material film and the interlayer insulating film. Step (b), forming a groove in the insulating film (c), forming a via hole in the insulating film (d), and forming a first barrier metal so as to cover at least the inner surface of the via hole A step (e) of removing a portion of the first barrier metal provided on the wiring material film and a part of the wiring material to form a recess in the upper portion of the wiring material film; A step (g) of forming a first cap metal on the wiring material film along the concave portion of the first wiring material film and forming a first wiring having a concave portion formed on the upper surface; and a concave portion of the first wiring And a step of forming a plug embedded in the via hole (h) It is equipped with a.

  According to this method, for example, the metal oxide film formed on the wiring material film in the step (f) is removed even when a metal having higher binding energy with oxygen than the wiring material film is added to the seed film. Therefore, a semiconductor device with reduced resistance between the wiring and the plug can be manufactured with high yield. Further, since the first cap metal formed in the step (g) suppresses the occurrence of stress migration and electromigration, the semiconductor device with improved reliability can be manufactured according to the method of the present invention. .

  In the step (g), the first cap metal can be formed relatively easily by using a selective plating method.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present invention, even if a metal having a large binding energy with oxygen is added to the seed film, an increase in resistance between the via and the plug can be prevented. . In addition, since the cap metal can be formed while removing the metal oxide film from the wiring and the occurrence of stress migration and electromigration can be suppressed, a highly reliable semiconductor device can be manufactured with a high yield. .

(Embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A to 1F and FIGS. 2A to 2G are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

  First, as shown in FIG. 1A, a resist is formed by a lithography process, and etching is performed using the resist as a mask, thereby forming a first layer made of a low dielectric constant material provided on a semiconductor substrate (not shown). A first wiring trench 2 is formed in one interlayer insulating film 1. Next, as a pretreatment, the substrate (semiconductor device) is annealed in a hydrogen atmosphere at 280 ° C. for 60 seconds to reduce the oxide generated on the surface of the semiconductor device, and then the first barrier metal 3 has a film thickness. A tantalum nitride film having a thickness of 5 nm and a tantalum film having a thickness of 10 nm are formed by sputtering or the like. Here, the first barrier metal 3 is a metal film for preventing copper as a wiring material from diffusing into the surrounding first interlayer insulating film 1. Note that titanium nitride and titanium may be used as the constituent material of the first barrier metal 3.

  Next, as shown in FIG. 1B, a first seed film 4 having a thickness of 40 nm is formed on the first barrier metal 3 by sputtering or the like. Here, as the material of the first seed film 4, copper containing 1% by weight of Al is used. The reason why the metal is added to the copper is to enhance the electromigration resistance, the stress migration resistance, etc., and improve the reliability of the semiconductor device.

  Next, as shown in FIG. 1C, a first copper film 5 filling at least the first wiring trench 2 is formed on the first seed film 4 by a plating method, and then the first copper film 5 is formed by a CMP method. The copper film 5, the first seed film 4, and the first barrier metal 3 are polished so that the first barrier metal 3, the first seed film 4, and the first copper film 5 are only in the first wiring groove 2. Leave. As a result, a first wiring constituted by the first barrier metal 3, the first seed film 4 and the first copper film 5 is formed.

  Next, as shown in FIG. 1 (d), after pretreatment of the upper surface of the first wiring using a chemical solution containing dilute hydrofluoric acid as a main component, the upper surface of the first wiring is formed by selective plating. Only a WCoP film having a thickness of about 10 nm is formed as the first cap metal 6.

  Subsequently, as shown in FIG. 1E, a liner film 7 having a film thickness of about 60 nm is formed on the first interlayer insulating film 1 and the first wiring by a chemical vapor deposition method (CVD method) or the like. . Here, the liner film 7 is for preventing the copper in the first wiring from diffusing into the second interlayer insulating film 8 (see FIG. 1 (f)) to be formed later. And a silicon nitride film or a silicon carbide film having a relatively high relative dielectric constant compared to the first interlayer insulating film 1 or the like.

  Next, as shown in FIG. 1F, a second interlayer insulating film 8 made of a low dielectric constant material is formed on the liner film 7 by a CVD method or the like.

  Next, as shown in FIG. 2A, a part of the second interlayer insulating film 8 and a part of the liner film 7 are removed by repeating the lithography process and the etching process, and the second interlayer insulating film 8 is removed. A second wiring groove 10 is formed therein, and a via hole 9 reaching the upper surface of the first cap metal 6 from the bottom of the second wiring groove 10 is formed.

  Next, as shown in FIG. 2B, as a pretreatment of the substrate, an annealing process is performed in a steam atmosphere at 280 ° C. for 60 seconds to remove oxide generated on the upper surface of the first cap metal 6. Thereafter, a tantalum nitride film having a thickness of 5 nm and a tantalum film having a thickness of 10 nm are sequentially formed as the second barrier metal 11 by sputtering or the like. Note that titanium nitride and titanium may be used as the constituent material of the second barrier metal 11.

  Next, as shown in FIG. 2C, resputtering with argon (Ar) is performed to remove portions of the second barrier metal 11 and the first cap metal 6 formed below the via holes. At this time, the upper portion of the portion of the first wiring (particularly, the first copper film 5) provided below the via hole is also removed, and the recess 20 is formed on the upper surface of the first copper film 5. .

  Next, as shown in FIG. 2D, the surface of the third barrier metal 21 is pretreated with a chemical solution containing dilute hydrofluoric acid as a main component. Thereafter, a second cap metal 21 made of WCoP having a thickness of about 10 nm is formed on the first copper film 5 along the recess 20 by selective plating. Here, the second cap metal 21 may be made of titanium.

  Next, as shown in FIG. 2E, a tantalum film having a film thickness of about 5 nm is formed as the third barrier metal 24 on the second cap metal 21 and the second barrier metal 11 by sputtering or the like.

  Next, as shown in FIG. 2F, a second seed film 12 having a thickness of about 40 nm is formed on the second barrier metal 11 and the third barrier metal 24. Here, as the material of the second seed film 12, for example, copper containing 1% of Al is used similarly to the first seed film 4. The reason why the metal is added to the copper is to improve the electromigration resistance, the stress migration resistance, and the like, thereby improving the reliability of the semiconductor device.

  Next, as shown in FIG. 2G, after forming a second copper film 13 filling at least the via hole 9 and the second wiring trench 10 by plating, the second copper film 13 and the second copper film 13 are formed by CMP. The second seed film 12, the third barrier metal 24, and the second barrier metal 11 are polished so that the second barrier metal 11, the third barrier metal 24, and the second barrier metal 11 are only in the second wiring trench 10. The seed film 12 and the second copper film 13 are left. Thereby, the plug and the second wiring are formed. Here, the plug is a portion of the second barrier metal 11, the third barrier metal 24, the second seed film 12, and the second copper film 13 embedded in the via hole 9. This wiring is a portion of the second barrier metal 11, the third barrier metal 24, the second seed film 12, and the second copper film 13 embedded in the second wiring trench 10. As described above, the semiconductor device of the present embodiment having the embedded wiring can be manufactured.

  Here, the case where the so-called dual damascene technique in which the plug and the second wiring are simultaneously formed has been described. However, the second wiring having the second copper film 13 after the plug made of, for example, tungsten is formed. May be formed.

  As shown in FIG. 2G, the semiconductor device manufactured by the method of this embodiment is provided on a substrate made of silicon or the like, and a first wiring trench 2 (see FIG. 1A) is formed. A first interlayer insulating film 1 made of a low dielectric constant material, a first wiring buried in the first wiring trench 2 and having a recess formed on the upper surface, the first interlayer insulating film 1 and the first interlayer insulating film 1 The liner film 7 formed on the wiring, the second interlayer insulating film 8 formed on the liner film 7 and having the second wiring groove 10 (see FIG. 2A) and the via hole 9, and the via hole 9 And a plug connected so as to pierce the recess of the first wiring, and a second wiring connected via the plug. The width of the second wiring groove is, for example, 0.1 μm, and the depth is, for example, 0.15 μm.

  The first wiring is provided on the inner surface of the first wiring groove 2, for example, provided on the first barrier metal 3 composed of a tantalum nitride film and a tantalum film, and the first barrier metal 3, For example, a first seed film 4 made of copper containing 1 wt% Al, and a copper film provided on the first seed film 4, embedded in the first wiring trench 2, and formed with a recess 20 in the upper surface portion. (First wiring material film) 5 and, for example, WCoP formed from the upper end surface of the first barrier metal 3 to the upper end surface of the first seed film 4 and a part of the upper surface of the first copper film 5. And a second cap metal 21 formed on the first copper film 5 along the recess 20.

  In the semiconductor device of this embodiment, the plug and the second wiring are provided integrally. The plug is constituted by a portion of the second barrier metal 11, the third barrier metal 24, the second seed film 12 and the second copper film 13 embedded in the via hole 9 and the recess 20. The second wiring is constituted by a portion of the second barrier metal 11, the third barrier metal 24, the second seed film 12, and the second copper film 13 embedded in the second wiring trench 10. Yes.

  The first seed film 4 and the second seed film 12 are made of copper containing 1 wt% Al, for example. As a result, the occurrence of electromigration and stress migration is suppressed.

  The above is the structure and manufacturing method of the semiconductor device in the embodiment of the present invention.

  Next, in the manufacturing method according to this embodiment, after removing the cap metal (first cap metal 6) once formed on the first wiring in the steps shown in FIGS. The reason for forming the cap metal (second cap metal 21) on the first copper film 5 will be described.

  As described above, in the conventional semiconductor device, insufficient removal of the Al oxide on the upper surface of the wiring is a major cause of increasing the via resistance value.

  FIG. 3 is a diagram for explaining an estimation mechanism that suppresses an increase in via resistance in the semiconductor device of this embodiment.

  Also in the method of the present embodiment, Al contained in the first seed film 4 is diffused into the first copper film 5 by thermal diffusion after the first wiring is formed in the step shown in FIG. . Then, even if the first cap metal 6 is provided, Al in the first copper film 5 is combined with oxygen in the atmosphere, and an Al oxide film 14 is formed on the upper surface of the first copper film 5.

  Therefore, in the method of this embodiment, the Al oxide film 14 is removed in the step shown in FIG. However, since the first cap metal 6 is also removed by etching in this step, the effect of the cap metal cannot be fully utilized if it is left as it is. Therefore, in the method of the present embodiment, the second cap metal 21 is formed again in the step shown in FIG. Thereby, the occurrence of electromigration and stress migration in the first copper film 5 can be prevented, and the reliability of the semiconductor device can be improved. As a result, a semiconductor device with reduced via resistance can be manufactured with high yield. In addition, in the semiconductor device manufactured by the method of the present embodiment, the via resistance value can be suppressed to the designed value, and the reliability is improved. Furthermore, in the semiconductor device of this embodiment, since the plug is formed so as to pierce the first wiring, the surface area of the portion of the second copper film 13 located at the bottom of the plug can be increased, The resistance between the first wiring and the plug is reduced.

  Note that the metal added to the first seed film 4 and the second seed film 12 is not limited to Al, but may be any metal that has a higher binding energy with oxygen than copper. For example, Mg, Zn, Fe, Sn, Ti, or the like can be added to the first seed film 4 and the second seed film 12. Further, two or more kinds of metals having higher binding energy with oxygen than copper may be added to the seed film material (copper or the like).

  In the manufacturing method of the present embodiment, the first cap metal 6 formed on the first wiring and the second cap metal 21 formed on the first copper film 5 after resputtering are made of the same material. Although configured, they do not necessarily have to be composed of the same material. For example, one of the first cap metal 6 and the second cap metal 21 may be made of WCoP, and the other may be made of WCoB or the like. The metal used as the first cap metal 6 and the second cap metal 21 may be a metal having Co as a main component, such as WCoP, WCoB, WCoPB, and Mo added thereto.

  In the above description, an example in which two embedded wirings are formed has been described. However, multilayer wiring can be formed by repeating the same wiring forming process.

  In the semiconductor device according to the present embodiment, the first wiring having a recess at least on the upper surface, and the plug and the first wiring if a cap metal is formed on the first wiring along the recess. Can be reduced, and the reliability of the semiconductor device can be improved.

  The wiring structure and the method for manufacturing a semiconductor device according to the present invention can be widely applied to semiconductor devices having embedded wirings, and are used in various electronic devices.

(A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. (A)-(g) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the presumed mechanism in which the raise of via resistance is suppressed in the semiconductor device of embodiment of this invention. (A)-(e) is sectional drawing which shows the conventional wiring formation method. (A)-(e) is sectional drawing which shows the conventional wiring formation method. It is a figure which shows the cumulative frequency distribution of the via resistance value at the time of forming a multilayer embedded wiring by the conventional method. It is sectional drawing for demonstrating the presumed mechanism in which the resistance between wiring-plug rises in the conventional method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st interlayer insulation film 2 1st wiring groove 3 1st barrier metal 4 1st seed film 5 1st copper film 6 1st cap metal 7 Liner film 8 2nd interlayer insulation film 9 Via hole 10 Second wiring trench 11 Second barrier metal 12 Second seed film 13 Second copper film 14 Al oxide 20 Recess 21 Second cap metal 24 Third barrier metal

Claims (14)

A semiconductor substrate;
A first interlayer insulating film provided on the semiconductor substrate and having a first groove formed thereon;
A first wiring embedded in the first groove and having a recess formed on the upper surface;
An insulating film provided on the first interlayer insulating film and having a via hole and a second groove;
A plug embedded in the via hole and in contact with at least a recess of the first wiring; and a second wiring connected to the plug and embedded in the second groove;
The first wiring includes a first wiring material film in which a recess is formed, and a cap metal film provided along the recess in the first wiring material film.   The first wiring covers a first barrier film that covers an inner surface of the first groove, a side surface and a bottom surface of the first wiring material film, and a first barrier film provided on the first barrier film. The semiconductor device according to claim 1, further comprising one seed film.   The plug is provided on the inner surface of the via hole and on the concave portion of the cap metal film, and on the second seed film, a second wiring material film that fills the via hole. The semiconductor device according to claim 1, wherein:   The semiconductor device according to claim 1, wherein the cap metal film contains Co.   The semiconductor device according to claim 2, wherein the cap metal film is also provided on an upper end surface of the first barrier film and an upper end surface of the first seed film.   6. The semiconductor device according to claim 2, wherein the first barrier film includes at least one of tantalum, tantalum nitride, titanium, and titanium nitride.   7. The semiconductor device according to claim 2, wherein the first seed film contains copper as a main component and a metal whose binding energy with oxygen is larger than that of copper.   8. The semiconductor device according to claim 7, wherein the metal having a binding energy with oxygen larger than that of copper is at least one of Al, Mg, Zn, Fe, Sn, and Ti.   The insulating film includes a liner film provided on the first interlayer insulating film and a second interlayer insulating film provided on the liner film. The semiconductor device according to any one of 1 to 8. A step (a) of forming a wiring material film embedded in an interlayer insulating film formed on a semiconductor substrate;
A step (b) of forming an insulating film on the wiring material film and the interlayer insulating film;
Forming a groove in the insulating film (c);
Forming a via hole in the insulating film (d);
A step (e) of forming a first barrier metal so as to cover at least the inner surface of the via hole;
A step of removing a portion of the first barrier metal provided on the wiring material film and a part of the wiring material to form a recess on the wiring material film;
Forming a first cap metal on the wiring material film along the concave portion of the first wiring material film, and forming a first wiring having a concave portion on the upper surface (g);
And a step (h) of forming a plug embedded in the recess of the first wiring and the via hole. A step (i) of forming a second cap metal on the wiring material film after the step (a) and before the step (b);
In the step (d), the via hole is formed so that the second cap metal is exposed,
The method of manufacturing a semiconductor device according to claim 10, wherein in the step (f), at least a part of the second cap metal is removed. The step (c) and the step (d) are performed continuously,
12. The method of manufacturing a semiconductor device according to claim 10, wherein in the step (h), a second wiring connected to the plug and buried in the groove is formed simultaneously with the plug.   In the step (a), a seed film to which a metal containing copper as a main component and having a larger binding energy with oxygen than copper is added, and the seed film is surrounded by a side surface and a bottom surface of the first wiring material film. The method for manufacturing a semiconductor device according to claim 10, further comprising forming an enclosing second barrier metal.   14. The method of manufacturing a semiconductor device according to claim 10, wherein in the step (g), the first cap metal is formed by a selective plating method.

Images