JP2007180313A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To raise the reliability of a semiconductor which contains copper as the composition material of wiring or via. <P>SOLUTION: The semiconductor device 100 comprises a semiconductor substrate (not shown in figure), a first insulating layer 102 formed thereon; the via 104 (a first metal film 108) formed on the first insulating layer 102 while containing copper as a principal constituent; a second barrier metal film 118 provided on the first insulating layer 102 so as to be contacted with the first metal film 108, while a fourth layer 118a containing Ru, Ta or Ti, a fifth layer 118b containing W, and a sixth layer 118c containing Ru, Ta or Ti are formed in this sequence; and a second metal film 120 provided on the second barrier metal film 118, so as to be contacted with the sixth layer 118c while containing copper as the principal constituent thereof. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In recent years, a low resistance material such as copper has been used as a wiring material due to a demand for high speed semiconductor devices. When copper is used as the wiring material, a diffusion prevention layer (barrier metal film) is formed around the copper wiring in order to prevent copper from diffusing into the insulating layer.

  As the wiring becomes finer, the ratio of the barrier metal film in the semiconductor device increases, and it is important to select the material and characteristics appropriately. In order to suppress the resistance between the wirings, it is preferable that the barrier metal film is made of a low resistance material and the thickness of the barrier metal film is made as thin as possible.

Patent Document 1 discloses a configuration in which a tantalum material, a titanium material, or a tungsten material is used for a diffusion prevention layer. Further, in this document, the diffusion prevention layer is formed of any one selected from the group consisting of Ru, Re, Ni, Pd, Os, Ir, and Pt, or an alloy containing 50% or more of this metal. A configuration in which an adhesive layer is formed is disclosed. The document describes that, when a copper material in a liquid form is used by chemical vapor deposition to form a copper layer on the diffusion prevention layer, the adhesion between the diffusion prevention layer and the copper layer formed thereon is reduced. Has been. This is because when a tantalum alloy, titanium alloy, tungsten alloy, or the like is used as the diffusion prevention layer, these metals react with impurities such as carbon existing between the layers to form carbides. ing. Therefore, it is said that the adhesiveness with a copper layer can be expected to be improved by using such a metal that does not form carbides for the adhesive layer.
Non-Patent Document 1, by using the WN _x C _y as a barrier metal film, electromigration resistance has been described to improve.
JP-T-2005-513813 S. Smith et. Al., "The Application of ALD WNxCy As a Copper Diffusion Barrier", Proceedings of the IITC2003, p.135-137

  In recent years, the occurrence of stress migration of copper wiring has become a problem. When copper is used as a wiring material, voids (cavities) may be generated due to stress migration, for example, at the interface between the lower wiring and the upper via. When such voids are formed, there is a problem that poor connection between wirings is caused and the yield of the semiconductor device is lowered, or the semiconductor device becomes unstable due to long-term use. The technique described in Patent Document 1 cannot solve such a problem.

According to the present invention,
A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
A first metal film formed on the insulating film and containing copper as a main component;
A first layer containing Ru, Ta or Ti, a second layer containing W, and a third layer containing Ru, Ta or Ti are provided on the insulating film in contact with the first metal film. A barrier metal film formed in order;
A second metal film provided on the barrier metal film in contact with the third layer and containing copper as a main component;
A semiconductor device is provided.

  By using a W-based material as the material of the barrier metal film, as described in Non-Patent Document 1, electromigration resistance can be improved. According to the present invention, the barrier metal film is composed of the second layer containing W, and the first layer containing Ru, Ta, or Ti is provided between the second layer and the first metal film. Therefore, the adhesion between the first metal film and the barrier metal film can be improved. As a result, the resistance to electromigration of the wiring can be increased and the resistance to stress migration can be increased.

  In addition, when copper is used as the wiring material and a W-based material is used as the material of the barrier metal film, there is a problem that corrosion occurs during CMP (chemical mechanical polishing) processing when forming the wiring. . When such corrosion occurs, defects in wiring formation occur, causing problems such as an increase in resistance and a decrease in yield. According to the present invention, since the third layer containing Ru, Ta, or Ti is provided on the second layer containing W, the second layer is protected during the CMP process to prevent corrosion. Can do. Thereby, defective formation of wiring can be prevented, and an increase in resistance and a decrease in yield can be prevented.

According to the present invention,
A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
A first metal film formed on the insulating film and containing copper as a main component;
A first layer provided on the insulating film in contact with the first metal film, a second layer containing W, and a third layer made of a material different from the second layer are arranged in this order. The formed barrier metal film,
A second metal film provided on the barrier metal film in contact with the third layer and containing copper as a main component;
Including
A semiconductor device is provided in which the first layer is made of a material having higher adhesion to copper than the material constituting the second layer.

  As a result, the resistance to electromigration of the wiring can be increased and the resistance to stress migration can be increased.

  In the semiconductor device of the present invention, the third layer can be made of a material having a smaller electrode potential difference with respect to copper than the material constituting the second layer.

  The phenomenon that corrosion occurs during the CMP process is considered to be caused by the following reasons. When the electrolyte is dissolved in the CMP polishing liquid, when exposed to the CMP polishing liquid in a state where the metal film made of copper and the barrier metal film made of the W-based material are in contact with each other, the standard electrode of both A local battery is formed by the difference in potential. Therefore, it is considered that a current flows through both of them and galvanic corrosion occurs. By providing a third layer made of a material having a small electrode potential difference with copper between the second metal film and the second layer of the barrier metal film, generation of galvanic corrosion can be prevented. Thereby, defective formation of wiring can be prevented, and an increase in resistance and a decrease in yield can be prevented.

According to the present invention,
Forming an insulating film on a first metal film containing copper as a main component formed on a semiconductor substrate;
Forming a recess reaching the first metal film in the insulating film;
A first layer containing Ru, Ta, or Ti, a second layer containing W, and a third layer containing Ru, Ta, or Ti are formed in this order in this order to form a part of the recess. Forming a buried barrier metal film;
Forming a second metal film containing copper as a main component on the barrier metal film so as to fill the concave portion;
Removing the second metal film and the barrier metal film exposed outside the recess by CMP;
A method for manufacturing a semiconductor device is provided.

  Thereby, the reliability of the semiconductor device can be improved.

  It should be noted that any combination of the above-described components, and a conversion of the expression of the present invention between a method and an apparatus are also effective as an aspect of the present invention.

  According to the present invention, the reliability of a semiconductor device containing copper as a constituent material for wiring and vias can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

FIG. 1 is a cross-sectional view showing a part of the structure of the semiconductor device in this embodiment.
The semiconductor device 100 includes a semiconductor substrate (not shown), a first insulating layer 102 formed thereon, an etching stopper film 110 formed thereon, a second insulating layer 112 formed thereon and A protective insulating film 114 formed thereon is included. The semiconductor device 100 further includes a via 104 formed in the first insulating layer 102 and a wiring 122 provided on the via 104 so as to be connected to the via 104. The via 104 includes a first metal film 108 and a first barrier metal film 106 formed therearound. The wiring 122 includes a second metal film 120 and a second barrier metal film 118 formed around the second metal film 120. The first metal film 108 and the second metal film 120 contain copper as a main component. Here, the first metal film can be, for example, the via 104. In this case, the second metal film can be the wiring 122. Alternatively, the first metal film can be a wiring, and the second metal film can be a via.

  In this embodiment, each of the first barrier metal film 106 and the second barrier metal film 118 has a three-layer structure. The first barrier metal film 106 includes a first layer 106a, a second layer 106b made of a material different from the first layer 106a, and a third layer 106c made of a material different from the second layer 106b. Are stacked in this order. The second barrier metal film 118 includes a fourth layer 118a provided in connection with the first metal film 108, a fifth layer 118b and a fifth layer made of a material different from those of the fourth layer 118a. A sixth layer 118c made of a material different from 118b has a structure in which the layers are stacked in this order.

  The second layer 106b and the fifth layer 118b can be formed using a material containing W (tungsten). The second layer 106b and the fifth layer 118b can be made of, for example, W, WN, or WNC. By forming the second layer 106b and the fifth layer 118b with a material containing W, the electromigration resistance of the via 104 and the wiring 122 can be increased.

  The first layer 106a can be formed using a material having higher adhesion to copper than the material forming the second layer 106b. The third layer 106c can be made of a material that is less likely to cause galvanic corrosion with copper than the material forming the second layer 106b.

  The first layer 106a and the third layer 106c can be made of a material containing Ru, Ta, or Ti, for example. The first layer 106a and the third layer 106c can be made of, for example, an alloy, nitride, or nitrided carbide of Ru, Ta, or Ti. The first layer 106a and the third layer 106c can be made of the same material or different materials.

The fourth layer 118a and the sixth layer 118c can be formed using a material similar to that of the first layer 106a and the third layer 106c. A configuration example of the second barrier metal film 118 can be as follows.
(1) Fourth layer 118a / fifth layer 118b / sixth layer 118c: Ta / WNC / Ta;
(2) Fourth layer 118a / fifth layer 118b / sixth layer 118c: Ta / WNC / Ru;
(3) Fourth layer 118a / fifth layer 118b / sixth layer 118c: Ru / WNC / Ru. These are examples, and various combinations can be made.

  The second insulating layer 112 can be composed of a low dielectric constant film. The second insulating layer 112 can be made of, for example, SiOC. The first insulating layer 102 can be composed of a silicon oxide film or a low dielectric constant film similar to the second insulating layer 112. Note that although not shown here, the first insulating layer 102 may include an etching stopper film and a protective insulating film.

  The etching stopper film 110 can be made of SiC, SiCN, SiOC, or SiON. The protective insulating film 114 has a function of protecting the second insulating layer 112 during CMP when forming the wiring 122. The protective insulating film 114 can be composed of, for example, a silicon oxide film.

Next, a manufacturing procedure of the semiconductor device 100 shown in FIG. 1 will be described. 2 and 3 are process cross-sectional views illustrating the manufacturing procedure of the semiconductor device 100.
First, the first insulating layer 102 is formed on a semiconductor substrate (not shown). Subsequently, a via hole is formed in the first insulating layer 102, and a first barrier metal film 106 is formed in the via hole. Next, a first metal film 108 is formed on the first barrier metal film 106 in the via hole. The method for forming the first barrier metal film 106 and the first metal film 108 is the same as the method for forming the second barrier metal film 118 and the second metal film 120 described later. Thereafter, the first metal film 108 and the first barrier metal film 106 exposed outside the via hole are removed by CMP to form the via 104.

Subsequently, an etching stopper film 110, a second insulating layer 112, and a protective insulating film 114 are formed on the via 104 by a CVD method. Thereby, the structure shown in FIG. 2A is obtained. Here, the etching stopper film 110 can be made of SiCN, the second insulating layer 112 can be made of SiOC, and the protective insulating film 114 can be made of SiO ₂ .

  Next, a wiring trench 116 is formed in the protective insulating film 114, the second insulating layer 112, and the etching stopper film 110 by a known lithography technique and dry etching (FIG. 2B). As a result, the via 104 is exposed.

  Thereafter, a fourth layer 118a (film thickness of about 2 to 10 nm) is formed on the entire surface of the semiconductor substrate by an ALD (Atomic Layer Deposition) method or a PVD (Physical Vapor Deposition) method. Subsequently, a fifth layer 118b (film thickness of about 2 to 10 nm) is formed on the fourth layer 118a by ALD. Next, a sixth layer 118c (having a film thickness of about 2 to 10 nm) is formed on the fifth layer 118b by ALD or PVD (FIG. 2C).

  Thereafter, a copper film is formed on the sixth layer 118c as a copper plating seed layer by a PVD method such as a sputtering method to a thickness of about 35 nm to 75 nm. Thereby, the wiring trench 116 is partially filled. Subsequently, a copper film is formed by plating to form a second metal film 120, and the wiring trench 116 is embedded (FIG. 3A). The film thickness of the copper film formed by the plating method can be about 500 nm.

  Subsequently, the second metal film 120 and the second barrier metal film 118 exposed to the outside of the wiring trench 116 are removed by CMP. Thereby, the wiring 122 is formed (FIG. 3B).

  In this embodiment, a sixth layer 118c is formed over the fifth layer 118b formed of a W-based material. Therefore, even when the electrolyte is dissolved in the CMP polishing liquid during the CMP process, the fifth layer 118b is protected by the sixth layer 118c, so that galvanic corrosion can be prevented. From this point of view, the sixth layer 118c is preferably made of a material having a smaller electrode potential difference with copper than the W-based material. The same applies to the third layer 106c.

  Next, a cap insulating film 124 is formed over the wiring 122. The cap insulating film 124 can be made of, for example, SiCN.

  By repeating the above processing, a multilayer wiring structure can be formed.

  In the present embodiment, a fourth layer 118a is formed in the first metal film 108 of the lower via 104. Thereby, the adhesiveness between the first metal film 108 and the second barrier metal film 118 of the via 104 can be improved. Therefore, the movement of copper in the via 104 can be fixed, and a void can be prevented from being generated between the via 104 and the wiring 122 during heat treatment after the wiring is formed. For this reason, the occurrence of disconnection between the wiring and the via can be prevented, and the reliability of the semiconductor device 100 can be improved.

  Furthermore, in the second barrier metal film 118, since the fifth layer 118b formed of the W-based material is protected by the sixth layer 118c, occurrence of galvanic corrosion during the CMP process can be suppressed. Thereby, the reliability of the semiconductor device 100 can be further improved.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  In the above embodiment, an example in which the wiring is formed by the single damascene method has been shown, but the present invention can also be applied to the case of forming the wiring by the dual damascene method.

  In the above embodiment, the procedure for forming the copper plating seed layer by the PVD method such as the sputtering method has been described. However, the seed layer may be formed by other methods such as the CVD method.

It is sectional drawing which shows a part of structure of the semiconductor device in embodiment of this invention. FIG. 3 is a process cross-sectional view illustrating a manufacturing procedure of the semiconductor device illustrated in FIG. FIG. 3 is a process cross-sectional view illustrating a manufacturing procedure of the semiconductor device illustrated in FIG.

Explanation of symbols

100 Semiconductor device 102 First insulating layer 104 Via 106 First barrier metal film 106a First layer 106b Second layer 106c Third layer 108 First metal film 110 Etching stop film 112 Second insulating layer 114 Protective insulating film 118 Second barrier metal film 118a Fourth layer 118b Fifth layer 118c Sixth layer 120 Second metal film 122 Wiring 124 Cap insulating film

Claims (7)

A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
A first metal film formed on the insulating film and containing copper as a main component;
A first layer containing Ru, Ta or Ti, a second layer containing W, and a third layer containing Ru, Ta or Ti are provided on the insulating film in contact with the first metal film. A barrier metal film formed in this order;
A second metal film provided on the barrier metal film in contact with the third layer and containing copper as a main component;
A semiconductor device including: A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
A first metal film formed on the insulating film and containing copper as a main component;
A first layer provided on the insulating film in contact with the first metal film, a second layer containing W, and a third layer made of a material different from the second layer are arranged in this order. A barrier metal film formed by
A second metal film provided on the barrier metal film in contact with the third layer and containing copper as a main component;
Including
The semiconductor device in which the first layer is made of a material having higher adhesion to copper than the material constituting the second layer. The semiconductor device according to claim 2,
Each of the first layer and the third layer is a semiconductor device made of a material containing Ru, Ta, or Ti. The semiconductor device according to claim 1,
The second layer is a semiconductor device composed of W, WN, or WNC. Forming an insulating film on a first metal film containing copper as a main component formed on a semiconductor substrate;
Forming a recess reaching the first metal film in the insulating film;
A first layer containing Ru, Ta, or Ti, a second layer containing W, and a third layer containing Ru, Ta, or Ti are formed in this order in this order to form a part of the recess. Forming a buried barrier metal film;
Forming a second metal film containing copper as a main component on the barrier metal film so as to fill the concave portion;
Removing the second metal film and the barrier metal film exposed outside the recess by CMP;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 5,
A method of manufacturing a semiconductor device, wherein, in the step of removing by CMP, the second metal film and the barrier metal film are removed using a polishing liquid containing an electrolyte. In the manufacturing method of the semiconductor device according to claim 5 or 6,
The step of forming the second metal film includes a step of forming a seed copper film by a PVD method and a step of forming a copper film by a plating method.

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