CN102427040A - Method for self forming barrier layer containing manganese-silicon oxide in interlayer dielectric layer - Google Patents
Method for self forming barrier layer containing manganese-silicon oxide in interlayer dielectric layer Download PDFInfo
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- CN102427040A CN102427040A CN2011101834558A CN201110183455A CN102427040A CN 102427040 A CN102427040 A CN 102427040A CN 2011101834558 A CN2011101834558 A CN 2011101834558A CN 201110183455 A CN201110183455 A CN 201110183455A CN 102427040 A CN102427040 A CN 102427040A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method for self forming a barrier layer containing manganese-silicon oxide in an interlayer dielectric layer. The method comprises the following steps of: firstly forming a plurality of copper-filled grooves on a dielectric layer of a wafer, and depositing a manganese-copper layer on the dielectric layer and the surface of copper in the groove; filling copper on the manganese-copper layer in the groove; removing surplus copper, the manganese-copper layer and the dielectric layer by chemically mechanical polishing, and depositing a second dielectric layer on the wafer after the chemically mechanical polishing; and finally carrying out annealing operation on the wafer, wherein in the process of annealing, the manganese in the manganese-copper layer and the silicon and the oxygen in the dielectric layer react to generate the barrier layer containing the manganese-silicon oxide. By the method disclosed by the invention, the barrier layer containing the manganese-silicon oxide is self formed in the interlayer dielectric layer, thus the process steps are reduced, the production efficiency is improved, and the reliability of devices is also improved at the same time; furthermore, the barrier layer containing the MnSixOy is self formed, thus no new diffusion barrier layer needs to be formed.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication technical field, more precisely, the present invention relates to a kind of in interlayer dielectric layer the method on self-forming manganese and silicon containing oxygen compound barrier layer.
Background technology
Recent decades in past, metallic aluminium is used to be used as the inner conductor material of wafer always.Along with dwindling of live width, the speed of element computing just can receive resistance value and capacitance the multiply each other increase that postpones and significant decline.In order to face more intensive circuit design, industry is selected to have more low-resistance copper and is replaced aluminium.
Because copper has low-resistance characteristic, therefore be that the element of lead can bear more intensive circuit arrangement with copper, so can significantly reduce the number of required metal level, and then reduce production costs and improve the arithmetic speed of computer.In addition, copper also has higher electromigration (Electromigration; EM) therefore resistance is that the element of lead has higher life-span and stability with copper.
Copper material in order to form metal level very easily produces diffusion phenomena under the environment of high temperature.Therefore, known, comprise deposited barrier layer with copper enchasing technology, so as to stoping the generation of copper diffusion.
In the method on traditional formation barrier layer, generally in the groove of interlayer dielectric layer, deposit copper-manganese (CuMn) through physical vaporous deposition, adopt copper to electroplate (ECP) filling groove then, self-forming MnSi subsequently between copper seed layer and dielectric layer anneals
xO
y, carry out chemico-mechanical polishing (CMP) at last.Though this method between copper seed layer and dielectric layer self-forming manganese and silicon containing oxygen compound (MnSi
xO
y) barrier layer, but do not have the barrier layer between copper and the following one deck dielectric layer, and when annealing time fell short of, part manganese can diffuse into copper, caused the increase of resistance, influenced device performance.
Based on the deficiency in the existing production technology of determining, be necessary to look for a kind of new in interlayer dielectric layer the method on self-forming manganese and silicon containing oxygen compound barrier layer.
Summary of the invention
In view of the above problems; The present invention provide a kind of in interlayer dielectric layer the method on self-forming manganese and silicon containing oxygen compound barrier layer; In first interlayer dielectric layer that a wafer is comprised, be formed with first groove of filling copper; And on said first interlayer dielectric layer, be coated with second, third interlayer dielectric layer successively, concrete, may further comprise the steps:
Step 1, in said the 3rd interlayer dielectric layer, form second groove; And etching is exposed to second interlayer dielectric layer of second channel bottom; Thereby in second interlayer dielectric layer, form the through hole be positioned at second beneath trenches, and said through hole is positioned at the top of the copper that first groove fills and contacts with it;
Step 2, deposition one deck copper-manganese layer cover on the 3rd interlayer dielectric layer; The copper-manganese layer also covers on the bottom and sidewall of second groove simultaneously; And the copper-manganese layer also covers on the bottom and sidewall of through hole, and the copper of being filled in the copper-manganese layer of via bottoms and first groove contacts;
Step 3, in bottom and sidewall are coated with second groove of copper-manganese layer and bottom and sidewall be coated with in the through hole of copper-manganese layer and fill copper;
Step 5, on the 3rd interlayer dielectric layer deposition one deck the 4th interlayer dielectric layer, the 4th interlayer dielectric layer covers on the metallic copper that is positioned at the filling of second groove simultaneously;
Above-mentioned method, wherein, in the step 1, the deposition process of said copper-manganese layer is physical vapour deposition (PVD) or atomic layer deposition method.
Above-mentioned method, wherein, in the step 2, said copper-manganese layer top copper adopts the mode of electroplating to fill.
Above-mentioned method, wherein, one deck first, second, third or the 4th interlayer dielectric layer are by SiO arbitrarily
2Or the SiCO material is formed.
Above-mentioned method, wherein, said wafer also comprises the barrier layer that is set in place between first interlayer dielectric layer and second interlayer dielectric layer, and the barrier layer between second interlayer dielectric layer and the 3rd interlayer dielectric layer.
The method on the present invention self-forming manganese and silicon containing oxygen compound barrier layer in interlayer dielectric layer, advantage is:
1. the method on the present invention self-forming manganese and silicon containing oxygen compound barrier layer in interlayer dielectric layer has reduced processing step, has improved production efficiency.
2. the method on the present invention self-forming manganese and silicon containing oxygen compound barrier layer in interlayer dielectric layer has formed manganese and silicon containing oxygen compound barrier layer around copper, has improved the reliability of device.
The too much copper-manganese chemico-mechanical polishing that will deposit of the method on the present invention self-forming manganese and silicon containing oxygen compound barrier layer in interlayer dielectric layer fall and remaining manganese can be in annealing with the dielectric layer of lower floor in Si reaction generates manganese and silicon containing oxygen compound barrier layer with O, avoided in the previous process to formation contains the drawback of the oxidation of the copper that Mn oxide causes on the surface.
Those skilled in the art reads the detailed description of following preferred embodiment, and with reference to after the accompanying drawing, of the present invention these are incited somebody to action obvious with otherwise advantage undoubtedly.
Description of drawings
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.Yet appended accompanying drawing only is used for explanation and sets forth, and does not constitute limitation of the scope of the invention.
Fig. 1-5 is the schematic flow sheet of the present invention's method on self-forming manganese and silicon containing oxygen compound barrier layer in interlayer dielectric layer.
Embodiment
Shown in Fig. 1-5, in the method on the present invention self-forming manganese and silicon containing oxygen compound barrier layer in interlayer dielectric layer, mainly may further comprise the steps:
Earlier in the groove of interlayer dielectric layer, deposit copper-manganese (CuMn) through physical vaporous deposition or atomic layer deposition method; Copper is electroplated (ECP) filling groove then, and unnecessary copper, dielectric layer deposited are removed in chemico-mechanical polishing (CMP); Anneal self-forming MnSi in interlayer dielectric layer at last
xO
yThe barrier layer.
As shown in Figure 1; At wafer (for the sake of brevity; And not shown) be formed with one or more first grooves 21 that are filled with copper 2 among the one first interlayer dielectric layer ILD5 that comprised, and on first interlayer dielectric layer 5, be coated with second interlayer dielectric layer 3 and the 3rd interlayer dielectric layer 4 successively.Optional, also between the dielectric layer between ground floor 5 and second interlayer dielectric layer 3, be provided with barrier layer 10 (for example SiCO etc.), and between dielectric layer between the second layer 3 and the 3rd interlayer dielectric layer 4, be provided with barrier layer 11 (for example SiCO etc.).Like method through etching; In the 3rd interlayer dielectric layer 4, form second groove 41; This moment, etching was exposed to second interlayer dielectric layer 3 of second groove, 41 bottoms; Thereby in second interlayer dielectric layer 3, form the through hole 31 be positioned at below second groove 41, this formed position of through hole 31 etchings is positioned at the top of the metallic copper 2 that first groove 21 filled and keeps in touch with metallic copper 2.
Afterwards, adopt physical vapour deposition (PVD) copper-manganese layer 1,, in other execution mode, copper-manganese layer 1 also can generate through atomic layer deposition method.Copper-manganese layer 1 covers on the 3rd interlayer dielectric layer 4; Copper-manganese layer 1 also covers on the bottom and sidewall of second groove 21 simultaneously; And copper-manganese layer 1 also covers on the bottom and sidewall of through hole 31; And the copper-manganese layer 1 of through hole 31 bottoms contacts with first groove, 21 interior metallic coppers 2 of being filled, and is as shown in Figure 1.Wherein, first interlayer dielectric layer 5, second interlayer dielectric layer 3 and the 3rd interlayer dielectric layer 4 are all by SiO
2Perhaps material such as SiCO is processed.
As shown in Figure 2, above formed copper-manganese layer 1, adopt and electroplate (ECP) filling copper 6 again.Consequently, metallic copper 6 is filled in the bottom and sidewall is coated with in second groove 41 of copper-manganese layer 1, and metallic copper 6 also is filled in the bottom and sidewall is coated with in the through hole 31 of copper-manganese layer 1.Also having part metals copper 6 to be deposited on surface coverage has on the 3rd interlayer dielectric layer 4 of copper-manganese layer 1.
Among Fig. 3, adopt cmp CMP technology to remove unnecessary copper 6, copper-manganese layer 1 and dielectric layer 4.Mainly be to adopt the cmp removal to cover unnecessary metallic copper 6 and copper-manganese layer 1 on the 3rd interlayer dielectric layer 4.. at this moment, metallic copper 6 unnecessary in second groove 41 is also ground away, and is positioned at same plane with the surface of the 3rd interlayer dielectric layer 4 haply with the surface of the metallic copper 6 that keeps in second groove 41 filling.Among Fig. 4, deposition the 4th dielectric layer 7 on the wafer after accomplishing cmp.Mainly be also to cover simultaneously on the metallic copper 6 that is positioned at 41 fillings of second groove, referring to Fig. 3 at the 4th interlayer dielectric layer of deposition one deck on the 3rd interlayer dielectric layer 47, the four interlayer dielectric layers 7..
At last; As shown in Figure 5; The employed wafer of this method is carried out annealing operation, and in annealing process, the silicon in the manganese in the former copper-manganese layer 1 that in Fig. 1, deposits and second interlayer dielectric layer 3, the 3rd interlayer dielectric layer 4 and the 4th dielectric layer 7, oxygen reaction self-forming are by compound MnSi
xO
yThe diffusion impervious layer of forming 8.Its main purpose is; Wafer is carried out in the annealing in process; Owing in the metallic copper 6 that the part manganese in the copper-manganese layer 1 is filled diffusion effect is arranged in second groove 41; And diffusing to the silicon, the oxygen that comprise in manganese and the 4th interlayer dielectric layer 7 of upper surface of the metallic coppers 6 of filling in second groove 41 in the copper-manganese layer 1 directly contacts; So in annealing in process, silicon, the oxygen that comprises in the manganese of the upper surface of the metallic coppers 6 of filling in second groove 41 and the 4th interlayer dielectric layer 7 reacts and generates the diffusion impervious layer 8' of manganese and silicon containing oxide.
Adopt method provided by the present invention self-forming manganese and silicon containing oxygen compound barrier layer in interlayer dielectric layer, reduced processing step, improved production efficiency, also improved the reliability of device simultaneously; And because self-forming MnSi
xO
ySo the barrier layer also need not to form again new diffusion impervious layer.
Through explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, the also conversion of available other materials of silicon dioxide that the dielectric layer among the embodiment adopts.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read above-mentioned explanation after, various variations and revise undoubtedly will be obvious.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (5)
1. the method on a self-forming manganese and silicon containing oxygen compound barrier layer in interlayer dielectric layer; In first interlayer dielectric layer that a wafer is comprised, be formed with first groove of filling copper; And on said first interlayer dielectric layer, be coated with second, third interlayer dielectric layer successively; It is characterized in that, may further comprise the steps:
Step 1, in said the 3rd interlayer dielectric layer, form second groove; And etching is exposed to second interlayer dielectric layer of second channel bottom; Thereby in second interlayer dielectric layer, form the through hole be positioned at second beneath trenches, and said through hole is positioned at the top of the copper that first groove fills and contacts with it;
Step 2, deposition one deck copper-manganese layer cover on the 3rd interlayer dielectric layer; The copper-manganese layer also covers on the bottom and sidewall of second groove simultaneously; And the copper-manganese layer also covers on the bottom and sidewall of through hole, and the copper of being filled in the copper-manganese layer of via bottoms and first groove contacts;
Step 3, in bottom and sidewall are coated with second groove of copper-manganese layer and bottom and sidewall be coated with in the through hole of copper-manganese layer and fill copper;
Step 4, employing cmp are removed and are covered unnecessary copper and the copper-manganese layer on the 3rd interlayer dielectric layer, and remove copper unnecessary in second groove;
Step 5, on the 3rd interlayer dielectric layer deposition one deck the 4th interlayer dielectric layer, the 4th interlayer dielectric layer covers on the metallic copper that is positioned at the filling of second groove simultaneously;
Step 6, wafer is carried out annealing in process, wherein, in annealing process, diffuse to the diffusion impervious layer of manganese and the silicon in the 4th interlayer dielectric layer, oxygen reaction generation manganese and silicon containing oxide of the upper surface of the metallic copper of filling in second groove in the copper-manganese layer.
2. method according to claim 1 is characterized in that, in the step 1, the deposition process of said copper-manganese layer is physical vaporous deposition or atomic layer deposition method.
3. method according to claim 1 is characterized in that, in the step 2, said copper-manganese layer adopts the mode of electroplating to fill.
4. method according to claim 1 is characterized in that, one deck first, second, third or the 4th interlayer dielectric layer are by SiO arbitrarily
2Or the SiCO material is formed.
5. method according to claim 1 is characterized in that, said wafer also comprises the barrier layer that is set in place between first interlayer dielectric layer and second interlayer dielectric layer, and the barrier layer between second interlayer dielectric layer and the 3rd interlayer dielectric layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101834558A CN102427040A (en) | 2011-07-01 | 2011-07-01 | Method for self forming barrier layer containing manganese-silicon oxide in interlayer dielectric layer |
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|---|---|---|---|
| CN2011101834558A CN102427040A (en) | 2011-07-01 | 2011-07-01 | Method for self forming barrier layer containing manganese-silicon oxide in interlayer dielectric layer |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106409757A (en) * | 2015-07-31 | 2017-02-15 | 三星电子株式会社 | Methods of fabricating a semiconductor device |
| CN104009018B (en) * | 2013-02-27 | 2017-04-12 | 朗姆研究公司 | Interconnect with self-formed barrier |
| CN109216265A (en) * | 2018-08-31 | 2019-01-15 | 上海华力微电子有限公司 | A method of forming metal diffusion barrier layer |
| CN110459502A (en) * | 2018-05-08 | 2019-11-15 | 国际商业机器公司 | The method and semiconductor devices of jump through-hole structure are formed in the semiconductor device |
| CN111566800A (en) * | 2018-01-12 | 2020-08-21 | 泰塞拉公司 | Low resistivity metal interconnect structure with self-forming diffusion barrier layer |
| US11133216B2 (en) | 2018-06-01 | 2021-09-28 | International Business Machines Corporation | Interconnect structure |
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| US20070048931A1 (en) * | 2005-08-30 | 2007-03-01 | Fujitsu Limited | Semiconductor device and its manufacture method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104009018B (en) * | 2013-02-27 | 2017-04-12 | 朗姆研究公司 | Interconnect with self-formed barrier |
| CN106409757A (en) * | 2015-07-31 | 2017-02-15 | 三星电子株式会社 | Methods of fabricating a semiconductor device |
| CN111566800A (en) * | 2018-01-12 | 2020-08-21 | 泰塞拉公司 | Low resistivity metal interconnect structure with self-forming diffusion barrier layer |
| CN110459502A (en) * | 2018-05-08 | 2019-11-15 | 国际商业机器公司 | The method and semiconductor devices of jump through-hole structure are formed in the semiconductor device |
| US11133216B2 (en) | 2018-06-01 | 2021-09-28 | International Business Machines Corporation | Interconnect structure |
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| CN109216265B (en) * | 2018-08-31 | 2021-07-27 | 上海华力微电子有限公司 | Method for forming metal diffusion barrier layer |
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Application publication date: 20120425 |