CN109216265A - A method of forming metal diffusion barrier layer - Google Patents
A method of forming metal diffusion barrier layer Download PDFInfo
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- CN109216265A CN109216265A CN201811015325.1A CN201811015325A CN109216265A CN 109216265 A CN109216265 A CN 109216265A CN 201811015325 A CN201811015325 A CN 201811015325A CN 109216265 A CN109216265 A CN 109216265A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of method for forming metal diffusion barrier layer, provides substrate, and substrate successively includes metal interconnection layer, insulating layer, low k dielectric layer and hard mask layer from bottom to top；Further comprising the steps of: formation penetrates hard mask layer, the through-hole of low k dielectric layer and insulating layer, via bottoms exposing metal interconnection layer, and forms groove in the top of through-hole, and channel bottom is located in low k dielectric layer；The first metal layer is formed in the cell wall and slot bottom of hard mask layer, the hole wall of through-hole and bottom hole and groove；The first metal layer of the hole wall of through-hole and the cell wall of groove and slot bottom is set to react to form alloy barrier layer with low k dielectric layer；Metal seed layer is formed in alloy barrier layer and remaining the first metal layer surface；Metal is filled in groove and through-hole.The beneficial effects of the present invention are by forming alloy barrier layer before deposited metal seed layer, so that significantly more efficient prevent copper from spreading before forming barrier layer and being formed.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of methods for forming copper diffusion barrier layer.
Background technique
Metal interconnection layer is the structure the element being mutually isolated in integrated circuit by certain requirement interconnection at required circuit,
The problem of metal material is spread into dielectric layer can occur for metal interconnection layer process in the prior art, and metal interconnecting layer is caused to occur
Defect generallys use PVD method deposition TaN/Ta double-layer structure as metal diffusion barrier layer at present, or uses ALD TaN+
The barrier layer that PVD Ta double-layer structure is spread as metal, both methods all can make the contact resistance value in through-hole higher, and
And keep the gradient coating performance of PVD (physicalvapordeposition: physical vapor deposition) poor.
Summary of the invention
For the above-mentioned problems in the prior art, a kind of method for now providing formation metal diffusion barrier layer is intended to lead to
It crosses and forms alloy barrier layer before deposited metal seed layer, so that significantly more efficient prevent metal from forming it on formation barrier layer
Preceding diffusion.
A method of forming metal diffusion barrier layer, wherein provide a substrate, substrate successively includes metal from bottom to top
Interconnection layer, insulating layer, low k dielectric layer and hard mask layer；
It is further comprising the steps of:
Step 1: formation penetrates hard mask layer, the through-hole of low k dielectric layer and insulating layer, the interconnection of via bottoms exposing metal
Layer, and groove is formed in the top of through-hole, channel bottom is located in low k dielectric layer；
Step 2: forming the first metal layer in the cell wall and slot bottom of hard mask layer, the hole wall of through-hole and bottom hole and groove；
Step 3: the first metal layer of the hole wall of through-hole and the cell wall of groove and slot bottom being made to react to be formed with low k dielectric layer
Alloy barrier layer；
Step 4: forming metal seed layer in alloy barrier layer and remaining the first metal layer surface；
Step 5: filling metal in groove and through-hole.
Preferably, the method for metal diffusion barrier layer is formed, wherein the first metal layer is manganese Metal；And/or
Low k dielectric layer material is silica；And/or
Alloy barrier layer material is Mn-Si-O.
Preferably, the method for metal diffusion barrier layer is formed, wherein the thickness of the first metal layer is not less than 1nm.
Preferably, the method for metal diffusion barrier layer is formed, wherein the method for forming the first metal layer is chemical vapor deposition
Product.
Preferably, the method for metal diffusion barrier layer is formed, wherein make the hole wall of through-hole by annealing in step 3, and
The cell wall of groove and the first metal layer of slot bottom react to form alloy barrier layer with low k dielectric layer.
Preferably, the method for metal diffusion barrier layer is formed, wherein the annealing temperature in step 3 is arrived at 300 degrees Celsius
Between 400 degrees Celsius；And/or annealing time is between 5 minutes to 20 minutes.
Preferably, the method for metal diffusion barrier layer is formed, wherein before step 4 further include:
When the first metal layer of the hole wall of through-hole and the cell wall of groove and slot bottom reacts completely, in alloy barrier layer and
Remaining the first metal layer surface forms second metal layer.
Preferably, the method for metal diffusion barrier layer is formed, wherein the thickness of second metal layer is not less than 1nm.
Preferably, the method for metal diffusion barrier layer is formed, wherein second metal layer is in manganese, tantalum, titanium, cobalt and ruthenium
It is a kind of；And/or
Second metal layer is formed by chemical vapor deposition.
Preferably, the method for metal diffusion barrier layer is formed, wherein the material of the metal seed layer in step 4 is fine copper
Or copper alloy.
Above-mentioned technical proposal has the following advantages that or the utility model has the advantages that by forming alloy resistance before deposited metal seed layer
Barrier, so that significantly more efficient prevent metal from spreading before forming barrier layer and being formed.
Detailed description of the invention
With reference to appended attached drawing, more fully to describe the embodiment of the present invention.However, appended attached drawing be merely to illustrate and
It illustrates, and is not meant to limit the scope of the invention.
Fig. 1 is the schematic cross-section of the composite construction for the method that the present invention forms metal diffusion barrier layer；
Fig. 2 is the corresponding schematic cross-section of step 1 of the embodiment for the method that the present invention forms metal diffusion barrier layer；
Fig. 3 is the corresponding schematic cross-section of step 2 of the embodiment for the method that the present invention forms metal diffusion barrier layer；
Fig. 4 is the corresponding schematic cross-section of step 3 of the embodiment for the method that the present invention forms metal diffusion barrier layer；
Fig. 5 is the corresponding schematic cross-section of step 4 of the embodiment for the method that the present invention forms metal diffusion barrier layer；
Fig. 6 is the corresponding schematic cross-section of step 5 of the embodiment for the method that the present invention forms metal diffusion barrier layer；
Fig. 7 is the partial enlarged view at the A of the Fig. 6 for the method that the present invention forms metal diffusion barrier layer；
Fig. 8 is the section signal that second metal layer is generated in the embodiment for the method that the present invention forms metal diffusion barrier layer
Figure.
Appended drawing reference: 10, through-hole, 11, groove, 20, substrate, 21, metal interconnection layer, 22, insulating layer, 23, low-K dielectric
Layer, 24, hard mask layer, 31, the first metal layer, 32, alloy barrier layer, 331, second metal layer, 332, metal seed layer, 34,
Metal layer.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
A method of metal diffusion barrier layer is formed, is the improvement of metal interconnection process, as shown in figs. 1-7, Fig. 1-6 is
The corresponding schematic cross-section of each step in the method provided by the invention for forming metal diffusion barrier layer, as shown in Figure 1, mentioning first
For substrate 20, substrate 20 successively includes metal interconnection layer 21, insulating layer 22, low k dielectric layer 23 and hard mask layer 24 from bottom to top,
It is further comprising the steps of:
Step 1: it is formed on the substrate and penetrates hard mask layer 24, the through-hole 10 of low k dielectric layer 23 and insulating layer 22, through-hole 10
Bottom-exposed metal interconnection layer 21, and groove 11 is formed in the top of through-hole 10,11 bottom of groove is located in low k dielectric layer 23；
The section of composite construction is as shown in Figure 2 after the completion of the step；Herein it should be noted that the content that the step is connected using " simultaneously "
And do not have the limitation of existing order, that is, it is not intended to limit the precedence to form through-hole 10 and form groove 11, it both can be first
Through-hole 10 is formed, groove 11 is re-formed, groove 11 can also be initially formed and re-form through-hole 10.There is through-hole and groove due to being formed
Metal damascene structure be technological means customary in the art, therefore repeat no more its specific forming method.
Step 2: forming the first gold medal in the cell wall and slot bottom of hard mask layer 24, the hole wall of through-hole 10 and bottom hole and groove 11
Belong to layer 31；The section of composite construction is as shown in Figure 3 after the completion of the step.
Step 3: making the first metal layer 31 of the hole wall of through-hole 10 and the cell wall of groove 11 and slot bottom and low k dielectric layer 23
Reaction forms alloy barrier layer 32.The step to form alloy resistance by reacting the first metal layer 31 with low k dielectric layer 23
Barrier 32 can prevent resistance in through-hole 10 from increasing while playing metal diffusion, composite construction after the completion of the step
Section is as shown in Figure 4.Step 4: forming metal seed layer 332 in alloy barrier layer 32 and 31 surface of remaining the first metal layer；
Composite construction section is as shown in Figure 5 after the completion of the step.
Step 5: metal is filled in groove 11 and through-hole 10, that is, forms metal layer 34, composite construction after the completion of the step
Section it is as shown in Figure 6, it should be noted that the metal of metal layer 34 is consistent with the metal of metal seed layer 332 at this time, is
Metallic copper.
It is further on the basis of above-mentioned technical proposal, the extra metal of substrate surface can be removed by polishing process.
As optional embodiment, CMP (Chemical-mechanical polish: chemical mechanical grinding) can be passed through
Realize above-mentioned polishing process.
As optional embodiment, manganese Metal is can be used in the first metal layer 31；Further, the material of low k dielectric layer 23
Matter can be used silica, in above-mentioned steps 3, can make the manganese Metal of the first metal layer 31 and the oxidation silicon material of low k dielectric layer 23
Reaction forms Mn-Si-O, i.e. 32 material of alloy barrier layer is Mn-Si-O.
In the above-described embodiments, step 3 can make the manganese Metal and low k dielectric layer of the first metal layer 31 by an annealing process
23 oxidation silicon material reacts to form Mn-Si-O, wherein can be made by controlling annealing conditions, i.e. annealing temperature and annealing time
Metal and oxidation pasc reaction form Mn-Si-O.
Further, in the above-described embodiments, the thickness of the first metal layer 31 is not less than 1nm.
Further, in the above-described embodiments, chemical vapor deposition can be used in the method for forming the first metal layer 31.
Further, in the above-described embodiments, the slot by the anneal hole wall and groove 11 that make through-hole 10 in step 3
The first metal layer 31 of wall and slot bottom reacts to form alloy barrier layer 32 with low k dielectric layer 23.Wherein, as optional embodiment party
Formula, annealing temperature are can be controlled between 300 degrees Celsius to 400 degrees Celsius；Further alternative, annealing time can be controlled in 5 points
Clock is between 20 minutes.
Further, in the above-described embodiments, before step 4 further include:
It, can be in alloy when the first metal layer 31 of the hole wall of through-hole 10 and the cell wall of groove 11 and slot bottom reacts completely
Barrier layer 32 and 31 surface of remaining the first metal layer form second metal layer 331, the section of composite construction after the completion of the step
As shown in Figure 8.
When the thickness of the first metal layer 31 is greater than 2nm, the hole wall of through-hole 10 and the cell wall of groove 11 and slot bottom are judged
Whether the first metal layer 31 reacts completely in annealing process, can be in alloy barrier layer 32 and remaining if reaction completely
31 surface of the first metal layer forms second metal layer 331, and the effect of second metal layer 331 is to enhance alloy barrier layer 32 and gold
Belong to the binding force between seed layer 332；It, need not depositing second metal layer 331 if the first metal layer 31 does not react completely.
Further, in the above-described embodiments, the thickness of second metal layer 331 is not less than 1nm.
Further, in the above-described embodiments, second metal layer 331 is one of manganese, tantalum, titanium, cobalt and ruthenium.
Further, in the above-described embodiments, second metal layer 331 is formed by chemical vapor deposition.
Further, in the above-described embodiments, the material of the metal seed layer 332 in step 4 is fine copper or copper alloy.This
Sample can not have to the sequencing that consideration forms barrier layer and copper diffusion, and operation is simpler, more efficiently avoid forming resistance
Copper diffusion occurs before being formed for barrier.
Further, in the above-described embodiments, step 5 can be used electroplating technology and complete metal filling.
The beneficial effects of the present invention are can be effectively reduced through-hole as alloy barrier layer 32 using Mn-Si-O structure
Contact resistance value in 10, further, by forming alloy barrier layer 32 before deposited metal seed layer 332, thus more
Adding effectively prevents copper from spreading before forming barrier layer and being formed.
The above is only preferred embodiments of the present invention, are not intended to limit the implementation manners and the protection scope of the present invention, right
For those skilled in the art, it should can appreciate that and all replace with being equal made by description of the invention and diagramatic content
It changes and obviously changes obtained scheme, should all be included within the scope of the present invention.
Claims (10)
1. a kind of method for forming metal diffusion barrier layer, which is characterized in that provide a substrate, the substrate is from bottom to top successively
Including metal interconnection layer, insulating layer, low k dielectric layer and hard mask layer；
It is further comprising the steps of:
Step 1: formation penetrates the hard mask layer, the through-hole of the low k dielectric layer and the insulating layer, and the via bottoms are sudden and violent
Reveal the metal interconnection layer, and form groove in the top of the through-hole, the channel bottom is located in the low k dielectric layer；
Step 2: forming one the in the cell wall and slot bottom of the hard mask layer, the hole wall of the through-hole and bottom hole and the groove
One metal layer；
Step 3: the first metal layer of the hole wall of the through-hole and the cell wall of the groove and slot bottom and the low K being made to be situated between
Electric layer reacts to form alloy barrier layer；
Step 4: forming a metal seed layer in the alloy barrier layer and the remaining the first metal layer surface；
Step 5: filling metal in the groove and the through-hole.
2. forming the method for metal diffusion barrier layer as described in claim 1, which is characterized in that the first metal layer is manganese
Metal；And/or
The low k dielectric layer material is silica；And/or
The alloy barrier layer material is Mn-Si-O.
3. forming the method for metal diffusion barrier layer as described in claim 1, which is characterized in that the thickness of the first metal layer
Degree is not less than 1nm.
4. forming the method for metal diffusion barrier layer as described in claim 1, which is characterized in that form the first metal layer
Method be chemical vapor deposition.
5. forming the method for metal diffusion barrier layer as described in claim 1, which is characterized in that passing through in the step 3
Annealing keeps the first metal layer and the low k dielectric layer of the hole wall of the through-hole and the cell wall of the groove and slot bottom anti-
Alloy barrier layer should be formed.
6. forming the method for metal diffusion barrier layer as claimed in claim 5, which is characterized in that the annealing in the step 3
Temperature is between 300 degrees Celsius to 400 degrees Celsius；And/or annealing time is between 5 minutes to 20 minutes.
7. forming the method for metal diffusion barrier layer as described in claim 1, which is characterized in that before the step 4 also
Include:
When the first metal layer of the hole wall of the through-hole and the cell wall of the groove and slot bottom reacts completely, in described
Alloy barrier layer and the remaining the first metal layer surface form a second metal layer.
8. forming the method for metal diffusion barrier layer as claimed in claim 7, which is characterized in that the thickness of the second metal layer
Degree is not less than 1nm.
9. forming the method for metal diffusion barrier layer as claimed in claim 7, which is characterized in that the second metal layer is
One of manganese, tantalum, titanium, cobalt and ruthenium；And/or
The second metal layer is formed by chemical vapor deposition.
10. forming the method for metal diffusion barrier layer as described in claim 1, which is characterized in that the metal in the step 4
The material of seed layer is fine copper or copper alloy.
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| CN201811015325.1A CN109216265B (en) | 2018-08-31 | 2018-08-31 | Method for forming metal diffusion barrier layer |
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| US20070048931A1 (en) * | 2005-08-30 | 2007-03-01 | Fujitsu Limited | Semiconductor device and its manufacture method |
| US20080173547A1 (en) * | 2006-08-17 | 2008-07-24 | Sony Corporation | Method of manufacturing semiconductor device |
| CN102427040A (en) * | 2011-07-01 | 2012-04-25 | 上海华力微电子有限公司 | Method for self forming barrier layer containing manganese-silicon oxide in interlayer dielectric layer |
| CN102446812A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnecting method |
| CN103606532A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | Method for improving filling capability of copper interconnection trench |
| CN105575798A (en) * | 2014-10-29 | 2016-05-11 | 应用材料公司 | System and method for removing contamination from surface of seed layer |
-
2018
- 2018-08-31 CN CN201811015325.1A patent/CN109216265B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070048931A1 (en) * | 2005-08-30 | 2007-03-01 | Fujitsu Limited | Semiconductor device and its manufacture method |
| US20080173547A1 (en) * | 2006-08-17 | 2008-07-24 | Sony Corporation | Method of manufacturing semiconductor device |
| CN102446812A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnecting method |
| CN102427040A (en) * | 2011-07-01 | 2012-04-25 | 上海华力微电子有限公司 | Method for self forming barrier layer containing manganese-silicon oxide in interlayer dielectric layer |
| CN103606532A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | Method for improving filling capability of copper interconnection trench |
| CN105575798A (en) * | 2014-10-29 | 2016-05-11 | 应用材料公司 | System and method for removing contamination from surface of seed layer |
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