CN103606532A - Method for improving filling capability of copper interconnection trench - Google Patents

Method for improving filling capability of copper interconnection trench Download PDF

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Publication number
CN103606532A
CN103606532A CN201310506674.4A CN201310506674A CN103606532A CN 103606532 A CN103606532 A CN 103606532A CN 201310506674 A CN201310506674 A CN 201310506674A CN 103606532 A CN103606532 A CN 103606532A
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China
Prior art keywords
hard mask
layer
metal hard
etching
copper
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Pending
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CN201310506674.4A
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Chinese (zh)
Inventor
刘斌
曾林华
任昱
吕煜坤
张旭昇
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Priority to CN201310506674.4A priority Critical patent/CN103606532A/en
Publication of CN103606532A publication Critical patent/CN103606532A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics

Abstract

The invention discloses a method for improving the copper diffusion barrier layer sputtering step coverage capability. The method comprises the steps of back-etching a metal hard mask and removing edge corners of the hard mask when etching of a dielectric layer trench is finished so as to expand the size of an opening of the trench, preparing a copper diffusion barrier layer to cover the surfaces of the trench and the hard mask and carrying out copper electroplating and chemical mechanical polishing processes. As the process of metal hard mask back-etching is added in the method, the opening pattern of the trench is increased by etching the edge corners of the metal hard mask, formation of bulges at corners can be prevented during preparation of the copper diffusion barrier layer, the filling capability is improved in the subsequent electroplating process, and the device performance is improved.

Description

Improve the method for the interconnected trench fill ability of copper
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of method that improves the interconnected trench fill ability of copper.
Background technology
Along with constantly dwindling of device size, the raising of operating frequency, especially below 90nm node, industry is generally used Damascus copper interconnection technology, in the copper interconnection technology of Damascus, need to form the interconnected groove of copper in device etching, then deposit a copper diffusion barrier layer covering groove surface, then fill metallic copper and carry out cmp and obtain desired structure.But in the technique of deposited barrier layer, during barrier layer sputter, easily at groove opening corner, form projection, and then cause patterns of openings less, at the groove for having compared with high-aspect-ratio, when filling groove, very easily because opening is insufficient compared with the little trench fill that causes, and then affect device performance.
Fig. 1～Fig. 4 is the process chart of the interconnected technique of copper in prior art, comprises the following steps:
Step 1, on barrier layer, 1 upper surface deposits the first low-dielectric constant layer 2 and the second low-dielectric constant layer 3 from bottom to top successively, and then deposits the upper surface that a metal hard mask 4 is covered in the second low-dielectric constant layer 3, forms structure shown in Fig. 1;
Step 2, adopt photoetching process, form interconnected groove, be used for the follow-up interconnected wire of filling copper, as shown in Figure 2 structure;
The upper surface of step 3, the surface of preparing a copper diffusion barrier layer covering groove and the hard mask of residual metallic, as shown in Figure 3 structure;
Step 4, carry out copper diffusion barrier layer and metal hard mask that copper plating and chemical mechanical milling tech are removed metal hard mask top, then in trench fill material layer, as shown in Figure 4 structure.
Because traditional handicraft is Direct precipitation copper diffusion barrier layer after etching forms groove, when copper diffusion barrier layer sputter, easily on the corner form projection, and then reduced patterns of openings size, as shown in Figure 3.In the larger trench fill technique of depth-to-width ratio, cause the copper of filling can not well be full of groove, and then affect device performance, as shown in Figure 4.
Therefore, how to improve packing material covers in groove integrality and endeavour the direction of studying for those skilled in the art.
Chinese patent (application number: the manufacture method that 201110274227.1) discloses a kind of metal copper Damascus interconnection structure; comprise the following steps: comprise the steps: in metal dielectric layer, to make in advance the first through hole and the first groove, and on metal dielectric layer from the bottom to top successively deposition etch barrier layer, sacrifice layer, hard mask layer, the first antireflecting coating, corresponding to patterned first photoresist of described the first through hole; In integrating, the interconnected smithcraft of back segment forms double damask structure; In double damask structure, adopt non-oxidizing acid to remove the sacrifice layer on etch stop layer; Adopt spin coating proceeding that advanced low-k materials is filled up in the region except metallic copper again in etch stop layer top, form metal copper Damascus interconnection structure.The invention provides a kind of manufacture method of metal copper Damascus interconnection structure, to stop the damage of the low-k that dry etching and/or cineration technics etc. cause in traditional handicraft.
This invention, when etching forms groove, is directly to fill, and when the higher groove of depth-to-width ratio is filled, filler may form at opening part stacking, and then causes trench fill insufficient, and then affects device performance.
Chinese patent (application number: 200910055938.2) disclose a kind of copper interconnection method, adopt etch process on dielectric layer, to form through hole, and in through hole after deposited copper diffusion impervious layer and copper seed layer, the method comprises: wafer is taken out from reative cell, before wafer enters electroplating bath, wafer frontside down and rotate; Adopt electrochemistry plating ECP growth copper interconnection layer; Adopt cmp that copper interconnection layer is polished to dielectric layer surface, form copper conductor.Adopt the method can in the process of copper-connection, avoid copper conductor to occur cavity, and avoid copper conductor to cause erosion.
This invention is by before wafer carries out copper electroplating technology, and wafer frontside and rotate, is removed VOC or particulate pollutant down, then carries out the interconnected technique of metallic copper.But this patent is by the moving wafer of special plating endless belt, to be rotated to remove the pollutant of groove, and groove opening pattern is not changed, in the higher groove of depth-to-width ratio during deposited copper diffusion impervious layer, may form at opening part stacking, and then cause follow-up filling insufficient, affect device performance.
Summary of the invention
In order to address the above problem, the invention provides a kind of method that improves copper diffusion barrier layer sputter step covering power, in etching, form after the interconnected groove of copper, again metal hard mask is returned to quarter, make metal hard mask on the corner form a turning, make the copper diffusion barrier layer of subsequent deposition can on the corner not form projection, reduce the patterns of openings size at groove top, and then packing material better covers the interconnected groove of copper in follow-up copper electroplating technology.
In order to address the above problem, the technical solution used in the present invention is:
Improve a method for trench fill ability, be applied in the interconnected technique of Damascus copper, wherein, described method comprises:
Step 1, behind the surface of a substrat structure successively barrier layer, the first low-dielectric constant layer, the second low-dielectric constant layer and metal hard mask layer, return and carve described metal hard mask layer, described the second low-dielectric constant layer to described the first low-dielectric constant layer, form interconnected groove;
Step 2, anti-reflection coating are full of described interconnected groove and cover the upper surface of remaining metal hard mask layers;
Step 3, removal are positioned at the anti-reflecting layer on described remaining metal hard mask layers upper surface and sidewall thereof, between described remaining metal hard mask layers, form a top channel;
Remaining metal hard mask layers described in step 4, etching, to expand the openend of described top channel;
Step 5, remove after remaining anti-reflecting layer, continue the preparation technology of subsequent copper diffusion impervious layer and trench fill.
Above-mentioned method, wherein, returns carving technology etching by photoresistance and removes the anti-reflecting layer that hardmask upper surface and side are positioned at groove.
Above-mentioned method, wherein, adopts wet-cleaned to remove described residue anti-reflecting layer.
Above-mentioned method, wherein, described metal hard mask layer is TiN.
Above-mentioned method, wherein, adopts remaining metal hard mask layers described in plasma etching industrial etching.
Above-mentioned method, wherein, controls width, the sidewall pattern of the metal hard mask layers after etching by adjusting the technological parameter of described plasma etching.
Above-mentioned method, wherein, described copper diffusion barrier layer is TaN.
Above-mentioned method, wherein adopts physical vapour deposition (PVD) to deposit described copper diffusion barrier layer.
Because the present invention has adopted above technical scheme, when etching forms interconnected groove, fill anti-reflecting layer in groove after and to metal hard mask layers, carry out etching, remove the corner of trench metal hard mask, and then when all needing deposited copper diffusion impervious layer, avoid on the corner forming stacking, and then when follow-up trench fill, make to fill more abundant, and then boost device performance; Simultaneously, due to before etching metal hard mask layers, be filled with anti-reflecting layer in groove, low-dielectric constant layer that can fine protection metal hard mask layers below, avoids, when etching metal hard mask layers, low-dielectric constant layer is caused to damage.
Accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.In whole accompanying drawings, identical mark is indicated identical part.Deliberately proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1～4 are the process chart of the interconnected technique of prior art Damascus copper;
Fig. 5～12 are a kind of schematic diagram that improves groove spreadability method of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 5～12, for the present invention improves the flow chart that the interconnected groove of copper covers integrality method always, comprise the following steps:
Step 1, in surface deposition one barrier layer 1 of a substrat structure (in figure do not indicate), then on barrier layer, 1 upper surface deposits the first low-dielectric constant layer 2 and the second low-dielectric constant layer 3 successively, and then deposit the surface that a metal hard mask layer 4 is covered in the second low-dielectric constant layer 3, form structure shown in Fig. 5.Wherein, in the present invention's one preferred embodiment, barrier layer 1 is SiCN, and the first low-dielectric constant layer 2 is the materials such as FSG or SiCOH, and the second low-dielectric constant layer 3 is the materials such as silicon dioxide or silicon oxide carbide, and metal hard mask layer 4 is titanium nitride.
Step 2, at metal hard mask layer 4 surface-coated one deck photoresistances, carry out in photoresistance, forming required pattern window after exposure imaging technique, then utilize this window to adopt dry etch process to be etched to the first low-dielectric constant layer downwards, form interconnected groove, be used for filling copper and form copper conductor; And remove residue photoresistance.Structure as shown in Figure 6.
Step 3, be coated with an anti-reflecting layer 7 fill up interconnected groove and cover residual metallic hard mask layers 4 ' surface, structure as shown in Figure 7.
Step 4, adopt photoresistance to return carving technology etching to remove and be positioned at the anti-reflecting layer on remaining metal hard mask layers 4 ' upper surface and sidewall thereof, in remaining metal hard mask layers 4 ' between form a top channel, as shown in Figure 8.After this step completes, only in groove, remain with residue anti-reflecting layer 7 ', the anti-reflecting layer of remainder is removed, the structure below can protecting in follow-up etching technics is avoided the damage that etching causes.
Step 5, adopt plasma etching industrial to residual metallic hard mask layers 4 ' carry out selective etch, remove residual metallic hard mask layers 4 ' be positioned at the corner at groove opening place, to expand the openend of its top channel, form structure as shown in Figure 9.As shown in the figure, after over etching, the angle position place at residual metallic hard mask layers 4 ' be positioned at groove opening place is removed, form a rounder and more smooth turning, sidewall is milder, amplified the size of groove opening, so at subsequent copper diffusion impervious layer, be more prone to deposit and can not form stacking; Simultaneously due at interconnected groove, remain with residue anti-reflecting layer 7 ', the dielectric layer below 4 ' time of etching residual metallic hard mask layers can fine protection mask layer, avoids etching to cause damage to it.Meanwhile, in an embodiment of the present invention, by adjusting the technological parameter of plasma etching, control width, the sidewall pattern of the metal hard mask layers after etching, and then control the open-topped size of groove, reach optimum technique effect.
Remaining anti-reflecting layer 7 in step 6, employing wet clean process removal groove ', this step completes and forms structure as shown in figure 10.
Step 7, adopt a copper diffusion barrier layer 5 deposited by physical vapour deposition (PVD) to cover interconnected flute surfaces and residual metallic hard mask layers structure 4 " surface.Preferably, this barrier layer 5 is titanium nitride (TaN), forms structure as shown in figure 11.Due to residual metallic hard mask layer has been carried out to etching, removed the corner of groove opening place metal hard mask layer, make edge rounder and more smooth, and then expanded groove top patterns of openings, at deposited copper diffusion impervious layer 5, be not easy to form in groove opening stacking, and then better carry out follow-up fill process.
Step 8, the follow-up copper plating trench fill technique of carrying out, because the copper diffusion barrier layer 5 depositing can not form projection in opening corner, carrying out copper electroplates after filling, can fine groove be filled up, improve the covering power of trench material, and then be conducive to boost device performance, and fill rear employing chemical mechanical milling tech and be polished to first low-dielectric constant layer 2 ' upper surface, form structure shown in Figure 12.This processing step adopts those skilled in the art's conventional techniques means, does not repeat them here.
In sum, because the present invention has increased the technique that a metal hardmask returns quarter, etching removed the metal hardmask of groove opening corner, and then makes groove opening become large, and then make can make trench fill more abundant in subsequent copper electroplating technology, and then boost device performance; Simultaneously when eat-backing metal hardmask, in trench fill have an anti-reflecting layer, low-dielectric constant layer that can fine protection metal hard mask layers below, avoids, when using plasma etching metal hardmask, low-dielectric constant layer is caused to damage.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.

Claims (8)

1. improve a method for trench fill ability, be applied to, in the interconnected technique of Damascus copper, it is characterized in that, described method comprises:
Step 1, behind the surface of a substrat structure successively barrier layer, the first low-dielectric constant layer, the second low-dielectric constant layer and metal hard mask layer, return and carve described metal hard mask layer, described the second low-dielectric constant layer to described the first low-dielectric constant layer, form interconnected groove;
Step 2, anti-reflection coating are full of described interconnected groove and cover the upper surface of remaining metal hard mask layers;
Step 3, removal are positioned at the anti-reflecting layer on described remaining metal hard mask layers upper surface and sidewall thereof, between described remaining metal hard mask layers, form a top channel;
Remaining metal hard mask layers described in step 4, etching, to expand the openend of described top channel;
Step 5, remove after remaining anti-reflecting layer, continue the preparation technology of subsequent copper diffusion impervious layer and trench fill.
2. method according to claim 1, is characterized in that, returns carving technology etching remove the anti-reflecting layer that hardmask upper surface and side are positioned at groove by photoresistance.
3. method according to claim 1, is characterized in that, adopts wet-cleaned to remove described residue anti-reflecting layer.
4. method according to claim 2, is characterized in that, described metal hard mask layer is TiN.
5. method according to claim 1, is characterized in that, adopts remaining metal hard mask layers described in plasma etching industrial etching.
6. method according to claim 5, is characterized in that, controls width, the sidewall pattern of the metal hard mask layers after etching by adjusting the technological parameter of described plasma etching.
7. method according to claim 1, is characterized in that, described copper diffusion barrier layer is TaN.
8. method according to claim 1, is characterized in that adopting physical vapour deposition (PVD) to deposit described copper diffusion barrier layer.
CN201310506674.4A 2013-10-23 2013-10-23 Method for improving filling capability of copper interconnection trench Pending CN103606532A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990216A (en) * 2015-01-29 2016-10-05 中芯国际集成电路制造(上海)有限公司 Formation method of interconnection structure
CN106033714A (en) * 2015-03-10 2016-10-19 中芯国际集成电路制造(上海)有限公司 Forming method of semiconductor structure
CN109216265A (en) * 2018-08-31 2019-01-15 上海华力微电子有限公司 A method of forming metal diffusion barrier layer
CN112635345A (en) * 2020-12-08 2021-04-09 华虹半导体(无锡)有限公司 Wafer detection device and method of single-chip process chamber
WO2022100066A1 (en) * 2020-11-10 2022-05-19 长鑫存储技术有限公司 Semiconductor structure forming method
US11410874B2 (en) 2020-11-10 2022-08-09 Changxin Memory Technologies, Inc. Method for forming semiconductor structure

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TW548789B (en) * 2002-04-19 2003-08-21 Nanya Technology Corp Method of forming metal line
US20060166484A1 (en) * 2005-01-21 2006-07-27 Yoshimitsu Ishikawa Method for Cu metallization of highly reliable dual damascene structures
KR20090053033A (en) * 2007-11-22 2009-05-27 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device
CN102339741A (en) * 2010-07-22 2012-02-01 中芯国际集成电路制造(上海)有限公司 Groove structure filled with metal and forming method thereof, and chemical mechanical polishing method

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Publication number Priority date Publication date Assignee Title
US20020030033A1 (en) * 1997-04-02 2002-03-14 Chih-Chien Liu High density plasma chemical vapor deposition process
TW548789B (en) * 2002-04-19 2003-08-21 Nanya Technology Corp Method of forming metal line
US20060166484A1 (en) * 2005-01-21 2006-07-27 Yoshimitsu Ishikawa Method for Cu metallization of highly reliable dual damascene structures
KR20090053033A (en) * 2007-11-22 2009-05-27 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device
CN102339741A (en) * 2010-07-22 2012-02-01 中芯国际集成电路制造(上海)有限公司 Groove structure filled with metal and forming method thereof, and chemical mechanical polishing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990216A (en) * 2015-01-29 2016-10-05 中芯国际集成电路制造(上海)有限公司 Formation method of interconnection structure
CN106033714A (en) * 2015-03-10 2016-10-19 中芯国际集成电路制造(上海)有限公司 Forming method of semiconductor structure
CN109216265A (en) * 2018-08-31 2019-01-15 上海华力微电子有限公司 A method of forming metal diffusion barrier layer
WO2022100066A1 (en) * 2020-11-10 2022-05-19 长鑫存储技术有限公司 Semiconductor structure forming method
US11410874B2 (en) 2020-11-10 2022-08-09 Changxin Memory Technologies, Inc. Method for forming semiconductor structure
CN112635345A (en) * 2020-12-08 2021-04-09 华虹半导体(无锡)有限公司 Wafer detection device and method of single-chip process chamber
CN112635345B (en) * 2020-12-08 2022-09-20 华虹半导体(无锡)有限公司 Wafer detection device and method of single-chip process chamber

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Application publication date: 20140226