KR20090053033A - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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Publication number
KR20090053033A
KR20090053033A KR1020070119657A KR20070119657A KR20090053033A KR 20090053033 A KR20090053033 A KR 20090053033A KR 1020070119657 A KR1020070119657 A KR 1020070119657A KR 20070119657 A KR20070119657 A KR 20070119657A KR 20090053033 A KR20090053033 A KR 20090053033A
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KR
South Korea
Prior art keywords
interlayer insulating
film
etching
hard mask
insulating film
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KR1020070119657A
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Korean (ko)
Inventor
이정웅
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주식회사 하이닉스반도체
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Priority to KR1020070119657A priority Critical patent/KR20090053033A/en
Publication of KR20090053033A publication Critical patent/KR20090053033A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a method for manufacturing a semiconductor device, comprising the steps of: sequentially forming an interlayer insulating film and a hard mask film on a semiconductor substrate; Patterning the hard mask layer; Forming a groove by first etching the interlayer insulating layer using the patterned hard mask layer as an etching mask; Second etching the interlayer insulating film under the groove so that the upper sidewall of the interlayer insulating film is inclined more than the lower sidewall while forming the contact hole; Forming a barrier metal film along a surface of the interlayer insulating film to fill a portion of the contact hole; Forming a metal layer on the barrier metal layer to fill the contact hole; And removing an upper portion of the interlayer insulating film having the sidewalls inclined.

Contact Etch, Sidewall Profile, Overhang, Void, Open Bad

Description

Method of manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a semiconductor capable of preventing open defects of a contact plug due to a chemical attack by suppressing void generation due to overhang. A method for manufacturing a device.

A cell array of a NAND flash device includes a plurality of cell blocks, and each cell block is operated by dividing a cell array into a string, unlike a general flash device. Due to this characteristic, there are drain contacts connected to bit lines at both ends of the string and source contacts for global ground, which are selected for string control. It is connected to the junction of the transistor (Select Transistor).

A drain contact plug forming process of a general flash device will be briefly described. A plurality of string structures are formed in the semiconductor substrate including a source select transistor, a plurality of memory cells, and a drain select transistor. Subsequently, a source contact plug is formed through a predetermined process, an interlayer insulating layer is formed thereon, and contact holes are formed to expose the drain of the drain select transistor. Then, a barrier metal film and a tungsten (W) film are sequentially deposited on the interlayer insulating film including the contact hole, and then drained to fill the contact hole by planarization by chemical mechanical polishing (CMP). A plug (Drain Contact Plug) is formed.

Recently, as the device becomes more integrated, the contact size becomes smaller and the opening becomes narrower due to overhang during barrier metal film deposition after contact etching, thereby creating voids during subsequent tungsten film deposition. In the CMP process, a chemical attack results in loss of the tungsten film, thereby increasing the appearance of the tungsten film being opened. This lowers the process yield and the reliability of the device.

According to the present invention, the interlayer insulating film etching process is performed twice in contact etching to make the upper sidewall of the interlayer insulating film more inclined than the lower sidewall, thereby increasing the critical dimension of the upper contact hole, thereby reducing the occurrence of overhang during barrier metal film deposition. The present invention provides a method of manufacturing a semiconductor device capable of suppressing void formation of a metal layer to prevent an open defect of a contact plug after a subsequent chemical mechanical polishing process.

A method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention may include sequentially forming an interlayer insulating film and a hard mask film on a semiconductor substrate, patterning the hard mask film, and using the patterned hard mask film as an etch mask. First etching to form a groove, forming a contact hole, and secondly etching the interlayer insulating film under the groove so that the upper sidewall of the interlayer insulating film is inclined more than the lower sidewall, and a part of the contact hole is filled. Forming a barrier metal film along with forming the barrier metal film, forming a metal layer on the barrier metal film so as to fill the contact hole, and removing an upper portion of the interlayer insulating film on which sidewalls are inclined.

In the above, the interlayer insulating film is formed of an HDP oxide film or a PE-TEOS film. The interlayer insulating film is formed thicker than the target thickness of the contact plug to be formed.

The hard mask film is formed of an amorphous carbon film. The method may further include forming an anti-reflection film on the hard mask film. The hard mask film has an etching selectivity ratio of 1: 5 to 1:10 between the hard mask film and the anti-reflection film, and a mixed gas of H 2 gas and N 2 gas is used as an etching gas, or a mixture of H 2 gas and O 2 gas is used. Patterning is done using gas.

The grooves are formed by an etching process in which the etching selectivity ratio of the hard mask film to the interlayer insulating film is 1: 3 to 1: 5, and a gas in which CFx, CHFx, Ar, and O 2 gas are combined as an etching gas. When the groove is formed, the thickness of the hard mask film remaining on the interlayer insulating film is controlled to be 300 kPa or less.

The contact hole is formed by an etching process in which the etch selectivity of the interlayer insulating film to the hard mask film is 1:10 to 1:20, and a gas in which CxFy, Ar, and O 2 gases are combined as an etching gas.

The upper sidewall of the interlayer insulating film has a positive profile. The positive profile is formed from 300 to 600 microns deep from the top surface of the interlayer insulating film. The upper portion of the interlayer insulating film having the inclined sidewalls is removed by a chemical mechanical polishing (CMP) process.

The present invention has the following effects.

First, during the contact etching, the interlayer insulating film etching process is performed twice using an etch selectivity between the interlayer insulating film and the hard mask film, so that the upper sidewall of the interlayer insulating film has a positive profile inclined more than the lower sidewall. By increasing the critical dimension (CD) of the upper portion of the hole to mitigate overhang during subsequent barrier metal film deposition, it is possible to suppress the generation of voids in the metal layer for forming the contact plug.

Second, by suppressing void formation of the metal layer to prevent the metal layer from being lost due to chemical attack during the subsequent chemical mechanical polishing (CMP) process, opening of the contact plug (open) failure can be prevented.

Third, it is possible to reduce the resistive fail of the device due to the void and to prevent the open defect of the contact plug, thereby improving the reliability of the device.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

1A to 1F are cross-sectional views illustrating process steps in order to explain a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a plurality of string structures (only drains of drain select transistors are shown; 110) including a source select transistor, a plurality of memory cells, and a drain select transistor are formed in the semiconductor substrate 100. Then, a stopper during a chemical mechanical polishing (CMP) process to form a subsequent source contact plug along the surfaces of the source select transistor, the plurality of memory cells, and the drain select transistor. A SAC (Self Align Contact) nitride film (not shown) is formed for use. The SAC nitride film may be formed to a thickness of 200 to 600 kPa, and may be formed by a Low Pressure Chemical Vapor Deposition (LPCVD) method or a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. Meanwhile, a buffer insulating layer (not shown) may be further formed below the SAC nitride layer. Next, although not shown in the figure, a process for forming a source contact plug on the source of the source select transistor is performed.

Thereafter, the interlayer insulating film 120, the hard mask film 130, and the antireflection film 140 are sequentially formed on the SAC nitride film. The interlayer insulating layer 120 may be formed of any oxide-based material. For example, the interlayer insulating layer 120 may be formed of a high density plasma (HDP) oxide film or a plasma enhanced-tetra ethyl ortho silicate (PE-TEOS) film. The interlayer insulating layer 120 is formed to be thicker than a target thickness of the contact plug to be formed, and may be preferably formed to a thickness of 5000 to 10000 kPa.

The hard mask layer 130 is used as an etch mask during subsequent contact etching, and is formed of a material having a different etching selectivity from the interlayer insulating layer 130, and preferably an amorphous carbon film ( amorphous carbon layer). In this case, the amorphous carbon film may be formed to a thickness of 1000 to 3000 kPa using a chemical vapor deposition method at a temperature of 250 to 600 ℃.

The anti-reflection film 140 may be formed of a silicon oxynitride layer (SiON) to prevent diffuse reflection of light and to protect the amorphous carbon layer when forming the photoresist pattern for patterning the hard mask layer 130. At this time, the anti-reflection film 140 may be formed to a thickness of 300 to 600Å.

Thereafter, the antireflection film 140 and the hard mask film 130 are patterned by an etching process using a mask (not shown) exposing a part of the surface of the antireflection film 140. Here, the etching process is performed by a dry etching process, in which case the dry etching process uses a mixed gas of H 2 gas and N 2 gas as an etching gas or a mixed gas of H 2 gas and O 2 gas. The etching selectivity of the anti-reflection film 140 to the hard mask film 130 is 1: 5 to 1:10. As a result, a part of the surface of the interlayer insulating layer 120 is exposed.

The mask may be a photoresist pattern, and in this case, the photoresist may be coated on the anti-reflection film 140 and then patterned by exposure and development. The mask is then removed.

Referring to FIG. 1B, the interlayer insulating layer 120 exposed by the first etching process using the patterned anti-reflection film 140 and the hard mask film 130 as an etching mask is etched to a predetermined depth. Here, the primary etching process is performed by a dry etching process. In this case, the dry etching process uses a gas in which CFx, CHFx, Ar, and O 2 gases are combined as an etching gas at a predetermined ratio, and the etching selectivity ratio of the hard mask layer 130 to the interlayer insulating layer 120 is 1: 3. To 1: 5.

As a result, the exposed interlayer insulating layer 120 is etched to a predetermined depth to form a groove 150 having a predetermined depth in the interlayer insulating layer 120. In the first etching process, the anti-reflection film 140 and the hard mask film 130 are etched together to remove the anti-reflection film 140 and the hard mask film 130 is lowered by some thickness. The thickness of 130 is controlled to be 300 kPa or less.

Referring to FIG. 1C, a contact hole 160 exposing the drain 110 is formed by second etching the interlayer insulating layer 120 under the groove 150. In this case, the contact hole 160 becomes a drain contact hole. In this case, the etching process is performed by a dry etching process, in which case, a gas in which CxFy, Ar, and O 2 gas are combined at a predetermined ratio is used as an etching gas, and the etching of the interlayer insulating layer 120 and the hard mask layer 130 is selected. The ratio is 1:10 to 1:20.

As a result, the interlayer insulating layer 120 under the groove 150 is etched to form the contact hole 160, so that the hard mask layer 130 is etched and removed together, and then the upper sidewalls of the exposed interlayer insulating layer 120 are together. It is etched to be more inclined than the lower sidewall of the upper sidewall A of the interlayer insulating layer 120. In this case, the upper sidewall A of the interlayer insulating layer 120 is formed to have a positive profile that becomes wider from the top to the bottom.

The contact hole 160 may be formed through the first and second etching processes of the interlayer insulating layer 120, and the interlayer insulating layer 120 and the hard mask layer may be formed by using a combination of etching gases used in each etching process. This is because the etching amount of the interlayer insulating layer 120 can be controlled during each etching process by adjusting the etching selectivity between the layers 130. In particular, in the second etching process of etching the interlayer insulating layer 120 under the groove 150, the upper sidewall of the interlayer insulating layer 120 is etched by increasing the etching selectivity of the hard mask layer 130 compared to the interlayer insulating layer 120. By increasing the exposure time to the gas, the upper sidewall A of the interlayer insulating layer 120 finally formed is formed to have a positive profile inclined more than the lower sidewall.

At this time, the depth d of the interlayer insulating film 120 in which the upper sidewall A is inclined must be properly controlled, and the thickness of the interlayer insulating film 120 removed during the subsequent chemical mechanical polishing (CMP) process is determined. In consideration of the above, it is formed to maintain a depth of 300 to 600 으로부터 from the upper surface of the interlayer insulating film 120.

As described above, when the upper sidewall A of the interlayer insulating layer 120 has a positive profile, the critical dimensions (CD, W) of the upper portion of the contact hole 160 are increased. Accordingly, it is possible to mitigate the occurrence of overhang in the upper sidewall of the interlayer insulating layer 120 during the subsequent barrier metal film deposition, thereby preventing voids in the metal layer during the metal layer deposition for the subsequent contact plug formation. Can be.

Referring to FIG. 1D, a barrier metal layer 170 is formed on the interlayer insulating layer 120 including the contact hole 160 to fill a portion of the contact hole 160. The barrier metal layer 170 is to prevent diffusion of metal wirings to be formed later and to improve adhesion between the interlayer insulating layer 120 and the metal layer. The barrier metal layer 170 is formed of a laminated film of Ti / TiN. It is preferable.

As shown in FIG. 1C, when the upper sidewall A of the interlayer insulating layer 120 has a positive profile A, the CD W on the contact hole 160 is increased, so that the interlayer is deposited when the barrier metal layer 170 is deposited. Overhang occurrence is alleviated at the upper sidewall A of the insulating layer 120.

Referring to FIG. 1E, the metal layer 180 is formed by depositing a metal material on the barrier metal layer 170 including the contact hole 160 to fill the contact hole 160. The metal layer 180 is for forming a metal wiring, and is formed of a material having a low specific resistance to lower the resistance of the metal wiring to be formed later, and preferably formed of a tungsten (W) film. As such, when the barrier metal layer 170 is deposited, an overhang is alleviated in the upper sidewall A of the interlayer insulating layer 120, so that an opening is secured so that the metal layer 180 can be deposited without voids to fill the contact hole 160. do.

Referring to FIG. 1F, the upper sidewall A of the interlayer insulating layer 120 is removed. In this case, the removing process may be performed by a planarization etching process, and the planarization etching process may be performed by chemical mechanical polishing (CMP) process. In this case, in the CMP process, the metal layer 180, the barrier metal layer 170, and the interlayer insulating layer 120 are etched to the depth of the interlayer insulating layer 120 in which the upper sidewall A is inclined (d in FIG. 1C).

As a result, the metal layer 180 remains only in the contact hole 160 to form a contact plug 180a formed of the metal layer 180 inside the contact hole 180. Here, the contact plug 180a is formed as a drain contact plug. In this case, since the upper sidewall A is removed, the contact plug 180a prevents the gap between the contact plugs 180 from being narrowed, thereby suppressing bridge generation.

According to an embodiment of the present invention, no voids are generated in the metal layer 180, so that the metal layer is not lost due to the attack caused by chemical (chemical, here, slurry) during the CMP process. Open failure of the plug 180a may be prevented from occurring. Therefore, the present invention can reduce the resistive fail of the device due to voids, prevent open defects of the contact plug 180a, and improve the reliability of the device.

The present invention has been described with reference to a method of manufacturing a flash memory device for convenience of description, but the present invention is not limited thereto and may be variously applied in forming contact plugs, metal wires, or the like of a semiconductor device.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1A to 1F are cross-sectional views illustrating process steps in order to explain a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 110 drain region

120: interlayer insulating film 130: hard mask film

140: antireflection film 150: groove

160: contact hole 170: barrier metal film

180: metal layer 180a: contact plug

Claims (15)

Sequentially forming an interlayer insulating film and a hard mask film on the semiconductor substrate; Patterning the hard mask layer; Forming a groove by first etching the interlayer insulating layer using the patterned hard mask layer as an etching mask; Second etching the interlayer insulating film under the groove so that the upper sidewall of the interlayer insulating film is inclined more than the lower sidewall while forming the contact hole; Forming a barrier metal film along a surface of the interlayer insulating film to fill a portion of the contact hole; Forming a metal layer on the barrier metal layer to fill the contact hole; And Removing the upper portion of the interlayer insulating film having the sidewalls inclined. The method of claim 1, The interlayer insulating film is a method of manufacturing a semiconductor device formed of an HDP oxide film or PE-TEOS film. The method of claim 1, The interlayer insulating layer is formed to be thicker than the target thickness of the contact plug to be formed. The method of claim 1, And the hard mask film is formed of an amorphous carbon film. The method of claim 1, And forming an anti-reflection film on the hard mask film. The method of claim 5, wherein The hard mask layer is patterned by an etching process in which the etching selectivity ratio of the hard mask layer to the anti-reflection layer is 1: 5 to 1:10. The method of claim 6, The etching process is a method of manufacturing a semiconductor device using a mixed gas of H 2 gas and N 2 gas as an etching gas or a mixed gas of H 2 gas and O 2 gas. The method of claim 1, The groove is formed by an etching process in which the etching selectivity of the hard mask film to the interlayer insulating film is 1: 3 to 1: 5. The method of claim 8, The etching process is a method of manufacturing a semiconductor device using a gas combined with CFx, CHFx, Ar and O 2 gas as an etching gas. The method of claim 1, wherein the groove is formed, And controlling the thickness of the hard mask film remaining on the interlayer insulating film to be 300 Å or less. The method of claim 1, The contact hole may be formed by an etching process in which the etch selectivity of the interlayer insulating layer to the hard mask layer is 1:10 to 1:20. The method of claim 11, wherein The etching process is a method of manufacturing a semiconductor device using a combination of CxFy, Ar and O 2 gas as an etching gas. The method of claim 1, And a top sidewall of the interlayer insulating film having a positive profile. The method of claim 11, wherein And wherein the positive profile is formed to a depth of 300 to 600 microns from an upper surface of the interlayer insulating film. The method of claim 1, The upper portion of the interlayer insulating film inclined sidewalls are removed by a chemical mechanical polishing process.
KR1020070119657A 2007-11-22 2007-11-22 Method of manufacturing a semiconductor device KR20090053033A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103606532A (en) * 2013-10-23 2014-02-26 上海华力微电子有限公司 Method for improving filling capability of copper interconnection trench
KR20230065666A (en) * 2021-11-05 2023-05-12 한국과학기술연구원 Semiconductor device including trehcn with undercut structure and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103606532A (en) * 2013-10-23 2014-02-26 上海华力微电子有限公司 Method for improving filling capability of copper interconnection trench
KR20230065666A (en) * 2021-11-05 2023-05-12 한국과학기술연구원 Semiconductor device including trehcn with undercut structure and method for manufacturing the same

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