KR20090053033A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
- Publication number
- KR20090053033A KR20090053033A KR1020070119657A KR20070119657A KR20090053033A KR 20090053033 A KR20090053033 A KR 20090053033A KR 1020070119657 A KR1020070119657 A KR 1020070119657A KR 20070119657 A KR20070119657 A KR 20070119657A KR 20090053033 A KR20090053033 A KR 20090053033A
- Authority
- KR
- South Korea
- Prior art keywords
- interlayer insulating
- film
- etching
- hard mask
- insulating film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 86
- 239000011229 interlayer Substances 0.000 claims abstract description 76
- 238000000034 method Methods 0.000 claims abstract description 63
- 238000005530 etching Methods 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims description 13
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 6
- 238000007517 polishing process Methods 0.000 claims description 2
- 239000011800 void material Substances 0.000 abstract description 5
- 239000007789 gas Substances 0.000 description 28
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- -1 here Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a method for manufacturing a semiconductor device, comprising the steps of: sequentially forming an interlayer insulating film and a hard mask film on a semiconductor substrate; Patterning the hard mask layer; Forming a groove by first etching the interlayer insulating layer using the patterned hard mask layer as an etching mask; Second etching the interlayer insulating film under the groove so that the upper sidewall of the interlayer insulating film is inclined more than the lower sidewall while forming the contact hole; Forming a barrier metal film along a surface of the interlayer insulating film to fill a portion of the contact hole; Forming a metal layer on the barrier metal layer to fill the contact hole; And removing an upper portion of the interlayer insulating film having the sidewalls inclined.
Contact Etch, Sidewall Profile, Overhang, Void, Open Bad
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a semiconductor capable of preventing open defects of a contact plug due to a chemical attack by suppressing void generation due to overhang. A method for manufacturing a device.
A cell array of a NAND flash device includes a plurality of cell blocks, and each cell block is operated by dividing a cell array into a string, unlike a general flash device. Due to this characteristic, there are drain contacts connected to bit lines at both ends of the string and source contacts for global ground, which are selected for string control. It is connected to the junction of the transistor (Select Transistor).
A drain contact plug forming process of a general flash device will be briefly described. A plurality of string structures are formed in the semiconductor substrate including a source select transistor, a plurality of memory cells, and a drain select transistor. Subsequently, a source contact plug is formed through a predetermined process, an interlayer insulating layer is formed thereon, and contact holes are formed to expose the drain of the drain select transistor. Then, a barrier metal film and a tungsten (W) film are sequentially deposited on the interlayer insulating film including the contact hole, and then drained to fill the contact hole by planarization by chemical mechanical polishing (CMP). A plug (Drain Contact Plug) is formed.
Recently, as the device becomes more integrated, the contact size becomes smaller and the opening becomes narrower due to overhang during barrier metal film deposition after contact etching, thereby creating voids during subsequent tungsten film deposition. In the CMP process, a chemical attack results in loss of the tungsten film, thereby increasing the appearance of the tungsten film being opened. This lowers the process yield and the reliability of the device.
According to the present invention, the interlayer insulating film etching process is performed twice in contact etching to make the upper sidewall of the interlayer insulating film more inclined than the lower sidewall, thereby increasing the critical dimension of the upper contact hole, thereby reducing the occurrence of overhang during barrier metal film deposition. The present invention provides a method of manufacturing a semiconductor device capable of suppressing void formation of a metal layer to prevent an open defect of a contact plug after a subsequent chemical mechanical polishing process.
A method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention may include sequentially forming an interlayer insulating film and a hard mask film on a semiconductor substrate, patterning the hard mask film, and using the patterned hard mask film as an etch mask. First etching to form a groove, forming a contact hole, and secondly etching the interlayer insulating film under the groove so that the upper sidewall of the interlayer insulating film is inclined more than the lower sidewall, and a part of the contact hole is filled. Forming a barrier metal film along with forming the barrier metal film, forming a metal layer on the barrier metal film so as to fill the contact hole, and removing an upper portion of the interlayer insulating film on which sidewalls are inclined.
In the above, the interlayer insulating film is formed of an HDP oxide film or a PE-TEOS film. The interlayer insulating film is formed thicker than the target thickness of the contact plug to be formed.
The hard mask film is formed of an amorphous carbon film. The method may further include forming an anti-reflection film on the hard mask film. The hard mask film has an etching selectivity ratio of 1: 5 to 1:10 between the hard mask film and the anti-reflection film, and a mixed gas of H 2 gas and N 2 gas is used as an etching gas, or a mixture of H 2 gas and O 2 gas is used. Patterning is done using gas.
The grooves are formed by an etching process in which the etching selectivity ratio of the hard mask film to the interlayer insulating film is 1: 3 to 1: 5, and a gas in which CFx, CHFx, Ar, and O 2 gas are combined as an etching gas. When the groove is formed, the thickness of the hard mask film remaining on the interlayer insulating film is controlled to be 300 kPa or less.
The contact hole is formed by an etching process in which the etch selectivity of the interlayer insulating film to the hard mask film is 1:10 to 1:20, and a gas in which CxFy, Ar, and O 2 gases are combined as an etching gas.
The upper sidewall of the interlayer insulating film has a positive profile. The positive profile is formed from 300 to 600 microns deep from the top surface of the interlayer insulating film. The upper portion of the interlayer insulating film having the inclined sidewalls is removed by a chemical mechanical polishing (CMP) process.
The present invention has the following effects.
First, during the contact etching, the interlayer insulating film etching process is performed twice using an etch selectivity between the interlayer insulating film and the hard mask film, so that the upper sidewall of the interlayer insulating film has a positive profile inclined more than the lower sidewall. By increasing the critical dimension (CD) of the upper portion of the hole to mitigate overhang during subsequent barrier metal film deposition, it is possible to suppress the generation of voids in the metal layer for forming the contact plug.
Second, by suppressing void formation of the metal layer to prevent the metal layer from being lost due to chemical attack during the subsequent chemical mechanical polishing (CMP) process, opening of the contact plug (open) failure can be prevented.
Third, it is possible to reduce the resistive fail of the device due to the void and to prevent the open defect of the contact plug, thereby improving the reliability of the device.
Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.
1A to 1F are cross-sectional views illustrating process steps in order to explain a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.
Referring to FIG. 1A, a plurality of string structures (only drains of drain select transistors are shown; 110) including a source select transistor, a plurality of memory cells, and a drain select transistor are formed in the
Thereafter, the
The
The
Thereafter, the
The mask may be a photoresist pattern, and in this case, the photoresist may be coated on the
Referring to FIG. 1B, the
As a result, the exposed
Referring to FIG. 1C, a
As a result, the
The
At this time, the depth d of the
As described above, when the upper sidewall A of the interlayer insulating
Referring to FIG. 1D, a
As shown in FIG. 1C, when the upper sidewall A of the interlayer insulating
Referring to FIG. 1E, the
Referring to FIG. 1F, the upper sidewall A of the interlayer insulating
As a result, the
According to an embodiment of the present invention, no voids are generated in the
The present invention has been described with reference to a method of manufacturing a flash memory device for convenience of description, but the present invention is not limited thereto and may be variously applied in forming contact plugs, metal wires, or the like of a semiconductor device.
The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.
1A to 1F are cross-sectional views illustrating process steps in order to explain a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.
<Description of the symbols for the main parts of the drawings>
100
120: interlayer insulating film 130: hard mask film
140: antireflection film 150: groove
160: contact hole 170: barrier metal film
180:
Claims (15)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070119657A KR20090053033A (en) | 2007-11-22 | 2007-11-22 | Method of manufacturing a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070119657A KR20090053033A (en) | 2007-11-22 | 2007-11-22 | Method of manufacturing a semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20090053033A true KR20090053033A (en) | 2009-05-27 |
Family
ID=40860602
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070119657A KR20090053033A (en) | 2007-11-22 | 2007-11-22 | Method of manufacturing a semiconductor device |
Country Status (1)
Country | Link |
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KR (1) | KR20090053033A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103606532A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | Method for improving filling capability of copper interconnection trench |
KR20230065666A (en) * | 2021-11-05 | 2023-05-12 | 한국과학기술연구원 | Semiconductor device including trehcn with undercut structure and method for manufacturing the same |
-
2007
- 2007-11-22 KR KR1020070119657A patent/KR20090053033A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103606532A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | Method for improving filling capability of copper interconnection trench |
KR20230065666A (en) * | 2021-11-05 | 2023-05-12 | 한국과학기술연구원 | Semiconductor device including trehcn with undercut structure and method for manufacturing the same |
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