KR20070098320A - Method for forming storagenode contact hole in semiconductor device - Google Patents

Method for forming storagenode contact hole in semiconductor device Download PDF

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KR20070098320A
KR20070098320A KR1020060029836A KR20060029836A KR20070098320A KR 20070098320 A KR20070098320 A KR 20070098320A KR 1020060029836 A KR1020060029836 A KR 1020060029836A KR 20060029836 A KR20060029836 A KR 20060029836A KR 20070098320 A KR20070098320 A KR 20070098320A
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hard mask
etching
storage node
contact hole
node contact
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KR1020060029836A
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Korean (ko)
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정중택
남기원
한기현
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주식회사 하이닉스반도체
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Publication of KR20070098320A publication Critical patent/KR20070098320A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming a storage node contact hole of a semiconductor device is provided to prevent a photoresist pattern from being lost until a hard mask etching is completed by increasing a margin in the photoresist pattern in case of etching the hard mask. Interlayer dielectrics(22,24,26) are formed on a semiconductor substrate(21). A hard mask(27) is formed on the interlayer dielectric. A lower anti-reflection film(28) is formed on the hard mask. A photoresist pattern(29) is formed on the lower anti-reflection film. A portion of the lower anti-reflection film is etched through the photoresist as an etching mask, and a polymer reaction material(28a) is formed on a surface of the photoresist. The rest of the lower anti-reflection film and the hard mask are etched through the photoresist pattern as the etching barrier. The interlayer dielectrics are etched through the hard mask as the etching barrier such that a storage node contact hole is formed.

Description

반도체소자의 스토리지노드콘택홀 형성 방법{METHOD FOR FORMING STORAGENODE CONTACT HOLE IN SEMICONDUCTOR DEVICE}METHODS FOR FORMING STORAGENODE CONTACT HOLE IN SEMICONDUCTOR DEVICE}

도 1a 및 도 1b는 종래기술에 따른 반도체소자의 스토리지노드콘택홀 형성 방법을 도시한 공정 단면도,1A and 1B are cross-sectional views illustrating a method of forming a storage node contact hole in a semiconductor device according to the prior art;

도 2는 종래기술에 따른 스토리지노드콘택홀간의 오픈현상을 나타낸 사진,Figure 2 is a photograph showing the open phenomenon between the storage node contact hole according to the prior art,

도 3a 내지 도 3d는 본 발명의 실시예에 따른 반도체소자의 스토리지노드콘택홀 형성 방법을 도시한 공정 단면도.3A to 3D are cross-sectional views illustrating a method of forming a storage node contact hole in a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체기판 22 : 제1층간절연막21 semiconductor substrate 22 first interlayer insulating film

23 : 랜딩플러그콘택 24 : 제2층간절연막23: landing plug contact 24: second interlayer insulating film

25 : 비트라인 26 : 제3층간절연막25 bit line 26 third interlayer insulating film

27 : 하드마스크 28 : 하부반사방지막27: hard mask 28: lower antireflection film

29 : 포토레지스트패턴 28a : 반응물29: photoresist pattern 28a: reactant

30 : 스토리지노드콘택홀30: Storage node contact hole

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체소자의 스토리지노드콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a storage node contact hole in a semiconductor device.

최근에 메모리소자의 고집적화, 소형화 및 고속화에 따라 스토리지노드와 하부를 연결하는 스토리지노드콘택홀의 면적이 점점 감소하며 각각의 스토리지노드콘택홀간의 거리가 가까워지면서 스토리지노드콘택홀간의 오픈 현상이 발생할 확률이 높아지고 있다.Recently, due to the high integration, miniaturization, and high speed of memory devices, the area of storage node contact holes connecting the storage node and the lower portion is gradually decreased, and the distance between each storage node contact hole is getting closer, so that there is a possibility that an open phenomenon between storage node contact holes occurs. It is rising.

도 1a 및 도 1b는 종래기술에 따른 반도체소자의 스토리지노드콘택홀 형성 방법을 도시한 공정 단면도이다.1A and 1B are cross-sectional views illustrating a method of forming a storage node contact hole of a semiconductor device according to the related art.

도 1a에 도시된 바와 같이, 소정 공정이 완료된 반도체기판(11) 상부에 제1층간절연막(12)에 의해 서로 절연되는 랜딩플러그콘택(13)을 형성한 후, 제1층간절연막(12) 상부에 제2층간절연막(14)을 형성한다.As shown in FIG. 1A, the landing plug contacts 13 insulated from each other by the first interlayer insulating layer 12 are formed on the semiconductor substrate 11 on which the predetermined process is completed, and then, on the first interlayer insulating layer 12. A second interlayer insulating film 14 is formed on the substrate.

이어서, 제2층간절연막(14) 상부에 비트라인(15)을 형성한다.Subsequently, a bit line 15 is formed on the second interlayer insulating film 14.

이어서, 비트라인(15) 사이를 채울때까지 전면에 제3층간절연막(16)을 증착한 후 연마공정을 진행하여 평탄화시킨다.Subsequently, the third interlayer insulating film 16 is deposited on the entire surface until the bit lines 15 are filled with each other, and then the polishing process is performed to planarize.

이어서, 평탄화된 제3층간절연막(16) 상부에 하드마스크(17)를 형성한 후, 하드마스크(17) 상에 포토레지스트패턴(18)을 형성한다.Subsequently, after the hard mask 17 is formed on the planarized third interlayer insulating layer 16, the photoresist pattern 18 is formed on the hard mask 17.

도 1b에 도시된 바와 같이, 포토레지스트패턴(18)을 식각마스크로 하여 스토리지노드콘택 식각을 진행하여 랜딩플러그콘택(13)의 표면을 개방시키는 스토리지 노드콘택홀(19)을 형성한다. 이때, 포토레지스트패턴(18)은 모두 소모되고 하드마스크(17)가 식각배리어 역할을 하여 제3층간절연막(16)과 제2층간절연막(14)을 식각한다.As illustrated in FIG. 1B, the storage node contact is etched using the photoresist pattern 18 as an etch mask to form a storage node contact hole 19 that opens the surface of the landing plug contact 13. At this time, the photoresist pattern 18 is exhausted and the hard mask 17 serves as an etching barrier to etch the third interlayer insulating film 16 and the second interlayer insulating film 14.

상술한 종래기술은 포토레지스트패턴만을 이용한 패터닝공정의 포토레지스트 마진 부족을 해결하고자 하드마스크(17)를 사용하고 있다. 이때, 하드마스크(17)는 폴리실리콘 또는 실리콘이 다량 함유된 질화막(Silicon Rich Oxy Nitride; SRON)으로 형성한다.The prior art described above uses a hard mask 17 to solve the lack of photoresist margin in the patterning process using only the photoresist pattern. At this time, the hard mask 17 is formed of a nitride film (Silicon Rich Oxy Nitride; SRON) containing a large amount of polysilicon or silicon.

그러나, 종래기술은 하드마스크로 사용되는 폴리실리콘 또는 실리콘이 다량 함유된 질화막의 경우, 식각시 패터닝은 되나 소자의 집적도가 고집적화되면서 스토리지노드콘택홀(19)의 단축간의 거리가 짧아지면서 웨이퍼내에 형성된 일부분의 스토리지노드콘택홀에서 스토리지노드콘택홀간의 오픈 현상이 발생한다.However, in the case of a nitride film containing a large amount of silicon or silicon used as a hard mask, the prior art is patterned at the time of etching, but as the integration of the device is highly integrated, the distance between the short axis of the storage node contact hole 19 is shortened. In some storage node contact holes, an open phenomenon occurs between storage node contact holes.

도 2는 종래기술에 따른 스토리지노드콘택홀간의 오픈현상을 나타낸 사진이다.2 is a photograph showing an open phenomenon between storage node contact holes according to the prior art.

도 2와 같이, Y축으로 두 개의 스토리지노드콘택홀이 오픈된 현상(이를 'BY2 페일'이라고 함)이 발생하는데, 이는 하드마스크(17)로 사용된 폴리실리콘 또는 질화막 의 식각시 포토레지스트패턴(18)의 마진이 부족하여 나타나는 현상이다.As shown in FIG. 2, a phenomenon in which two storage node contact holes are opened on the Y axis (called 'BY2 fail') occurs, which is a photoresist pattern during etching of polysilicon or a nitride film used as a hard mask 17. This is caused by a lack of margin in (18).

즉, 하드마스크(17) 식각시 포토레지스트패턴(18)이 조금씩 식각이 되어 가는데, 이때 옆면이 더 식각이 되면서 하드마스크(17)의 위쪽의 포토레지스트패턴(18)의 면적이 줄어들게 되어 하드마스크(17)가 식각되고 하드마스크(17)를 식각배리어로 스토리지노드콘택식각시 하드마스크(17)가 식각배리어로서의 역할을 제대 로 수행하지 못함에 따라 이웃한 두 스토리지노드콘택홀간의 오픈현상이 발생하게 되는 것이다.That is, when the hard mask 17 is etched, the photoresist pattern 18 is etched little by little. At this time, as the side surface is etched more, the area of the photoresist pattern 18 on the top of the hard mask 17 is reduced. (17) is etched and the hard mask (17) as an etch barrier. When the hard node (17) does not function properly as an etch barrier, an open phenomenon occurs between two adjacent storage node contact holes. Will be done.

상술한 이웃한 두 스토리지노드콘택홀간의 오픈현상에 의해 후속 스토리지노드콘택으로 사용될 폴리실리콘 증착후 패터닝없이 식각시 이웃한 스토리지노드콘택이 서로 브릿지되는 현상을 초래하게 된다.The above-described open phenomenon between two neighboring storage node contact holes causes a phenomenon in which neighboring storage node contacts are bridged with each other during etching without patterning after polysilicon deposition to be used as a subsequent storage node contact.

위와 같은 점을 보완하기 위하여 스토리지노드콘택식각시 포토레지스트패턴의 두께를 증가시키는 방법과 하드마스크의 두께 자체를 증가시키는 두가지 방법이 있을 수 있으나, 포토레지스트패턴의 두께를 증가시키는 경우에는 패턴 붕괴의 위험이 있으며, 하드마스크 두께 자체를 증가시키는 경우에는 하드마스크 식각시 포토레지스트패턴의 마진이 더욱 없어지기 때문에 하드마스크의 식각이 완료되기 전에 포토레지스트패턴이 모두 식각되는 문제가 발생한다.In order to compensate for the above, there may be two methods of increasing the thickness of the photoresist pattern during the storage node contact etching and increasing the thickness of the hard mask itself. If the hard mask thickness itself is increased, the margin of the photoresist pattern is further lost during the etching of the hard mask. Thus, all of the photoresist patterns are etched before the hard mask is etched.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 하드마스크 식각시 포토레지스트패턴의 마진을 확보하면서 이웃한 스토리지노드콘택홀간의 오픈 현상을 방지할 수 있는 반도체소자의 스토리지노드콘택홀 형성 방법을 제공하는데 그 목적이 있다.The present invention is proposed to solve the above problems of the prior art, the storage node contact hole of the semiconductor device that can prevent the open phenomenon between the adjacent storage node contact hole while securing the margin of the photoresist pattern during hard mask etching The purpose is to provide a formation method.

상기 목적을 달성하기 위한 본 발명의 스토리지노드콘택홀 형성 방법은 소정 공정이 완료된 반도체기판 상부에 층간절연막을 형성하는 단계, 상기 층간절연막 상에 하드마스크를 형성하는 단계, 상기 하드마스크 상에 하부반사방지막을 형성하는 단계, 상기 하부반사방지막 상에 포토레지스트패턴을 형성하는 단계, 상기 포토레지스트패턴을 식각마스크로 상기 하부반사방지막의 일부를 식각하여 상기 포토레지스트패턴의 표면에 폴리머성 반응물을 재증착시키는 단계, 상기 반응물에 의해 덮인 포토레지스트패턴을 식각배리어로 상기 하부반사방지막의 나머지부분과 하드마스크를 식각하는 단계, 및 상기 하드마스크를 식각배리어로 상기 층간절연막을 식각하여 스토리지노드콘택홀을 형성하는 단계를 포함하는 것을 특징으로 하고, 상기 포토레지스트패턴의 표면에 폴리머성 반응물을 재증착시키는 단계에서 상기 하부반사방지막의 일부 식각은, 수소가스와 아르곤가스만을 포함한 플라즈마를 사용하는 것을 특징으로 하고, 상기 하부반사방지막의 일부 식각시 수소가스와 아르곤가스의 양을 1:1∼2:1의 비율로 혼합하여 사용하는 것을 특징으로 한다.The storage node contact hole forming method of the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on the semiconductor substrate, a predetermined process is completed, forming a hard mask on the interlayer insulating film, the lower reflection on the hard mask Forming a protective film, forming a photoresist pattern on the lower anti-reflective film, etching a portion of the lower anti-reflective film by using the photoresist pattern as an etch mask and redepositing a polymeric reactant on the surface of the photoresist pattern Forming a storage node contact hole by etching the remaining portion of the lower anti-reflection film and the hard mask with an etch barrier using a photoresist pattern covered by the reactant, and etching the interlayer dielectric layer with an etch barrier with the hard mask. It characterized in that it comprises a step, the photore In the step of re-depositing the polymeric reactant on the surface of the streak pattern, the etching of the lower antireflection film is characterized by using plasma containing only hydrogen gas and argon gas, and the hydrogen gas and the partial etching of the lower antireflection film. It is characterized by using an amount of argon gas mixed in a ratio of 1: 1 to 2: 1.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 3a 내지 도 3d는 본 발명의 실시예에 따른 반도체소자의 스토리지노드콘택홀 형성 방법을 도시한 공정 단면도이다.3A to 3D are cross-sectional views illustrating a method of forming a storage node contact hole in a semiconductor device according to an embodiment of the present invention.

도 3a에 도시된 바와 같이, 소정 공정이 완료된 반도체기판(21) 상부에 제1층간절연막(22)에 의해 서로 절연되는 랜딩플러그콘택(23)을 형성한 후, 제1층간절 연막(22) 상부에 제2층간절연막(24)을 형성한다. 여기서, 랜딩플러그콘택(23)은 잘 알려진 바와 같이, 반도체기판(21) 상부에 형성된 워드라인 사이에 형성되는 것으로서, 폴리실리콘 증착 및 CMP(Chemical Mechanical Polishing)를 통해 형성할 수 있다. As shown in FIG. 3A, after forming the landing plug contacts 23 insulated from each other by the first interlayer insulating layer 22 on the semiconductor substrate 21 where the predetermined process is completed, the first interlayer thin film 22 is formed. A second interlayer insulating film 24 is formed on the top. Here, the landing plug contact 23 is formed between the word lines formed on the semiconductor substrate 21, as is well known, and may be formed through polysilicon deposition and chemical mechanical polishing (CMP).

이어서, 제2층간절연막(24) 상부에 비트라인(25)을 형성한다. 이때, 비트라인(25)은 배리어메탈, 텅스텐막 및 하드마스크질화막의 순서로 적층된 구조일 수 있으며, 배리어메탈은 TI/TiN으로 형성한다.Subsequently, a bit line 25 is formed on the second interlayer insulating film 24. In this case, the bit line 25 may have a stacked structure in order of a barrier metal, a tungsten film, and a hard mask nitride film. The barrier metal may be formed of TI / TiN.

이어서, 비트라인(25) 사이를 채울때까지 전면에 제3층간절연막(26)을 증착한 후 CMP를 이용한 연마 공정을 진행하여 평탄화시킨다.Subsequently, the third interlayer insulating film 26 is deposited on the entire surface until the bit lines 25 are filled, and then a polishing process using CMP is performed to planarize.

이어서, 평탄화된 제3층간절연막(26) 상부에 하드마스크(27)를 형성한다. 이때, 하드마스크(27)는 폴리실리콘 또는 실리콘이 다량 함유된 질화막(SRON)으로 형성하며, 하드마스크(27)는 포토레지스트패턴만을 이용한 패터닝공정시 스토리지노드콘택홀이 형성되기 어려운 것을 해결하기 위한 것이다.Subsequently, a hard mask 27 is formed on the planarized third interlayer insulating layer 26. At this time, the hard mask 27 is formed of a nitride film (SRON) containing a large amount of polysilicon or silicon, and the hard mask 27 is a solution for forming a storage node contact hole that is difficult to form during the patterning process using only a photoresist pattern. will be.

바람직하게, 하드마스크(27)는 600∼1500Å 두께로 증착하며, 이러한 두께로 증착하면 후속 식각공정시 충분히 하드마스크(27)가 식각배리어 역할을 한다.Preferably, the hard mask 27 is deposited to a thickness of 600 to 1500 Å, and when deposited to such a thickness, the hard mask 27 sufficiently serves as an etching barrier in a subsequent etching process.

이어서, 하드마스크(27) 상에 후속 포토공정시의 난반사를 방지하기 위해 하부반사방지막(Bottom Anti-Reflect Coating, 28)을 형성한 후, 하부반사방지막(28) 상부에 스토리지노드콘택마스크 역할을 하는 포토레지스트패턴(29)을 형성한다. Subsequently, a bottom anti-reflective coating (28) is formed on the hard mask (27) to prevent diffuse reflection during subsequent photo processes, and then serves as a storage node contact mask on the lower anti-reflective coating (28). A photoresist pattern 29 is formed.

도 3b에 도시된 바와 같이, 포토레지스트패턴(29)을 식각배리어로 이용하여 하부반사방지막(28)을 일부 식각한다. 이때, 하부반사방지막(28)의 일부 식각시 수 소가스(H2)와 아르곤 가스(Ar)만을 포함하는 플라즈마를 사용하여 식각한다.As shown in FIG. 3B, the lower anti-reflection film 28 is partially etched using the photoresist pattern 29 as an etching barrier. At this time, the etching part of the lower anti-reflection film 28 is etched using a plasma containing only hydrogen gas (H 2 ) and argon gas (Ar).

위와 같이, 수소가스와 아르곤가스만을 포함하는 플라즈마로 하부반사방지막(28)을 식각하면, 식각시에 생성되는 폴리머성 반응물(28a)이 포토레지스트패턴(29)의 표면에 재증착된다. 즉, 포토레지스트패턴(29)의 노출된 측면 및 상부 표면에 반응물(28a)이 재증착되어 포토레지스트패턴(29)의 식각 내성을 강화시켜준다.As described above, when the lower antireflection film 28 is etched with a plasma containing only hydrogen gas and argon gas, the polymeric reactant 28a generated during etching is redeposited on the surface of the photoresist pattern 29. That is, the reactant 28a is redeposited on the exposed side and top surface of the photoresist pattern 29 to enhance the etching resistance of the photoresist pattern 29.

바람직하게, 하부반사방지막(28)의 일부 식각은, 최초 하부반사방지막(28) 두께의 30∼50%정도만 식각한다. 예컨대, 하부반사방지막(28)을 300∼600Å 두께로 증착한 경우, 일부 식각은 90∼300Å 정도로 식각한다.Preferably, the partial etching of the lower antireflection film 28 is etched only about 30 to 50% of the thickness of the first lower antireflection film 28. For example, when the lower antireflection film 28 is deposited to a thickness of 300 to 600 kPa, some etching is etched to about 90 to 300 kPa.

그리고, 하부반사방지막(28)의 일부 식각시 수소가스와 아르곤가스의 양을 1:1∼2:1의 비율로 혼합하여 사용하는데, 이처럼 수소가스의 비율이 아르곤가스보다 같거나 많으면 반응물(28a)이 더욱 많이 생성되어 포토레지스트패턴(29)의 식각내성을 더욱 강화시킨다.When the lower anti-reflection film 28 is partially etched, a mixture of hydrogen gas and argon gas is used in a ratio of 1: 1 to 2: 1. When the ratio of hydrogen gas is equal to or greater than argon gas, the reactants 28a are used. ) Is further generated to further enhance the etch resistance of the photoresist pattern 29.

도 3c에 도시된 바와 같이, 반응물(28a)이 표면에 재증착된 포토레지스트패턴(29)을 식각배리어로 하여 하부반사방지막(28)의 나머지 부분과 하부반사방지막(28) 아래의 하드마스크(27)를 식각한다. 여기서, 하드마스크(27) 식각이 완료될때까지 포토레지스트패턴(29)은 반응물(28a)에 의해 남아 있게 되어 하드마스크(27)의 식각불량이 발생하지 않는다. 더불어, 반응물(28a)에 의해 포토레지스트패턴(29)의 손실이 발생하지 않는다.As shown in FIG. 3C, the photoresist pattern 29 on which the reactant 28a is redeposited on the surface is used as an etching barrier, and the hard mask under the remaining portion of the lower antireflection film 28 and the lower antireflection film 28 is formed. 27). Here, the photoresist pattern 29 remains by the reactant 28a until the etching of the hard mask 27 is completed, so that the etching defect of the hard mask 27 does not occur. In addition, the loss of the photoresist pattern 29 is not caused by the reactant 28a.

즉, 하드마스크(27) 식각시 반응물(28a)에 의해 포토레지스트패턴(29)이 식각되는 것이 방지되고, 이로써 하드마스크(27)의 위쪽의 포토레지스트패턴(29)의 면적이 줄어드는 것을 억제한다. That is, when the hard mask 27 is etched, the photoresist pattern 29 is prevented from being etched by the reactant 28a, thereby suppressing the reduction of the area of the photoresist pattern 29 above the hard mask 27. .

따라서, 하드마스크(27)의 식각손실이 없으므로, 도 3d에 도시된 바와 같이, 하드마스크(27)는 후속 제3층간절연막(26) 및 제2층간절연막(24)을 식각하여 스토리지노드콘택홀(30)을 개방할 때, 식각배리어로서의 역할을 제대로 수행한다. 즉, 스토리지노드콘택홀(30)이 완전히 개방될 때 비록 포토레지스트패턴(29) 및 반응물(28a), 그리고 하부반사방지막(28)은 모두 소모될 수 있으나, 하드마스크(27)는 그 형태를 그대로 유지하여 식각배리어의 역할을 충분히 수행한다.Therefore, since there is no etching loss of the hard mask 27, as shown in FIG. 3D, the hard mask 27 etches the third interlayer dielectric layer 26 and the second interlayer dielectric layer 24 to form a storage node contact hole. When opening (30), it properly serves as an etching barrier. That is, when the storage node contact hole 30 is fully opened, although the photoresist pattern 29, the reactant 28a, and the lower anti-reflective film 28 may be consumed, the hard mask 27 may have its shape. It will remain as it is to fully serve as an etching barrier.

상술한 실시예에 따르면, 본 발명은 하부반사방지막 식각시 수소가스와 아르곤가스만을 포함한 플라즈마를 사용하여 포토레지스트패턴의 표면에 반응물을 생성시켜 포토레지스트패턴의 식각내성을 강화시켜주므로써 후속 하드마스크 식각시 포토레지스트패턴의 마진을 증가시켜 하드마스크 식각이 완료될때까지 포토레지스트패턴의 손실을 방지할 수 있다.According to the embodiment described above, the present invention by using a plasma containing only hydrogen gas and argon gas when etching the bottom anti-reflection film to generate a reactant on the surface of the photoresist pattern to enhance the etching resistance of the photoresist pattern by the subsequent hard mask When etching, the margin of the photoresist pattern may be increased to prevent loss of the photoresist pattern until the hard mask etching is completed.

이처럼, 손실이 없는 포토레지스트패턴을 식각마스크로 하드마스크를 식각하고, 후속 절연막들의 식각을 진행하면, 이웃한 스토리지노드콘택홀간의 오픈현상이 발생하지 않는다.As such, when the hard mask is etched using the lossless photoresist pattern as an etch mask and the subsequent insulating layers are etched, the open phenomenon between neighboring storage node contact holes does not occur.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 반응물을 생성시켜 하드마스크 식각시 포토레지스트패턴의 마진을 증가시켜 하드마스크 식각이 완료될때까지 포토레지스트패턴이 손실되는 것을 방지할 수 있는 효과가 있다.The present invention described above has an effect of preventing the photoresist pattern from being lost until the hard mask etching is completed by increasing the margin of the photoresist pattern during the hard mask etching by generating the reactant.

또한, 본 발명은 손실이 없는 하드마스크를 식각배리어로 스토리지노드콘택홀을 형성하므로, 이웃한 스토리지노드콘택홀간의 오픈현상을 방지하여 소자의 신뢰성을 향상시킬 수 있는 효과가 있다.In addition, the present invention forms a storage node contact hole as an etching barrier using a lossless hard mask, thereby preventing an open phenomenon between neighboring storage node contact holes, thereby improving reliability of the device.

Claims (7)

소정 공정이 완료된 반도체기판 상부에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate on which the predetermined process is completed; 상기 층간절연막 상에 하드마스크를 형성하는 단계;Forming a hard mask on the interlayer insulating film; 상기 하드마스크 상에 하부반사방지막을 형성하는 단계;Forming a lower anti-reflection film on the hard mask; 상기 하부반사방지막 상에 포토레지스트패턴을 형성하는 단계;Forming a photoresist pattern on the lower antireflection film; 상기 포토레지스트패턴을 식각마스크로 상기 하부반사방지막의 일부를 식각하여 상기 포토레지스트패턴의 표면에 폴리머성 반응물을 재증착시키는 단계;Etching a portion of the lower anti-reflection film by using the photoresist pattern as an etch mask to redeposit a polymeric reactant on a surface of the photoresist pattern; 상기 반응물에 의해 덮인 포토레지스트패턴을 식각배리어로 상기 하부반사방지막의 나머지부분과 하드마스크를 식각하는 단계; 및Etching the hard mask and the rest of the lower anti-reflection film by using the photoresist pattern covered by the reactant as an etching barrier; And 상기 하드마스크를 식각배리어로 상기 층간절연막을 식각하여 스토리지노드콘택홀을 형성하는 단계Forming a storage node contact hole by etching the interlayer dielectric layer using the hard mask as an etch barrier 를 포함하는 반도체소자의 스토리지노드콘택홀 형성 방법.Storage node contact hole formation method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 포토레지스트패턴의 표면에 폴리머성 반응물을 재증착시키는 단계에서,In the step of redepositing a polymeric reactant on the surface of the photoresist pattern, 상기 하부반사방지막의 일부 식각은, 수소가스와 아르곤가스만을 포함한 플라즈마를 사용하는 것을 특징으로 하는 반도체소자의 스토리지노드콘택홀 형성 방법.Partial etching of the lower anti-reflection film is a storage node contact hole forming method of a semiconductor device, characterized in that using a plasma containing only hydrogen gas and argon gas. 제2항에 있어서,The method of claim 2, 상기 하부반사방지막의 일부 식각은, 상기 하부반사방지막의 최초 두께의 30∼50%정도만 식각하는 것을 특징으로 하는 반도체소자의 스토리지노드콘택홀 형성 방법.Partial etching of the lower anti-reflective coating, etching only 30 to 50% of the initial thickness of the lower anti-reflective coating, characterized in that the storage node contact hole forming method of the semiconductor device. 제3항에 있어서,The method of claim 3, 상기 하부반사방지막의 최초 두께는 300∼600Å 두께로 증착하는 것을 특징으로 하는 반도체소자의 스토리지노드콘택홀 형성 방법.The initial thickness of the lower anti-reflection film is a storage node contact hole forming method of a semiconductor device characterized in that the deposition to 300 to 600Å thickness. 제2항에 있어서,The method of claim 2, 상기 하부반사방지막의 일부 식각시 수소가스와 아르곤가스의 양을 1:1∼2:1의 비율로 혼합하여 사용하는 것을 특징으로 하는 반도체소자의 스토리지노드콘택홀 형성 방법.The method for forming a storage node contact hole of a semiconductor device, characterized in that for etching a portion of the lower anti-reflection film is mixed with the amount of hydrogen gas and argon gas in a ratio of 1: 1 to 2: 1. 제1항 내지 제5항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 5, 상기 하드마스크는, 폴리실리콘 또는 실리콘이 다량 함유된 질화막으로 형성하는 것을 특징으로 하는 반도체소자의 스토리지노드콘택홀 형성 방법.The hard mask is formed of a nitride film containing a large amount of polysilicon or silicon, the storage node contact hole forming method of a semiconductor device. 제6항에 있어서,The method of claim 6, 상기 하드마스크는, 600∼1500Å 두께로 증착하는 것을 특징으로 하는 반도체소자의 스토리지노드콘택홀 형성 방법.The hard mask is a deposition method of the storage node contact hole of a semiconductor device, characterized in that for depositing 600 ~ 1500Å thick.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008049395A1 (en) 2007-09-28 2009-04-16 Samsung Electro - Mechanics Co., Ltd., Suwon-shi Method for forming fine patterns and method for producing a semiconductor LED
CN102569174A (en) * 2010-12-30 2012-07-11 新加坡商格罗方德半导体私人有限公司 Integrated circuit system with ultra-low K dielectric and method of manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008049395A1 (en) 2007-09-28 2009-04-16 Samsung Electro - Mechanics Co., Ltd., Suwon-shi Method for forming fine patterns and method for producing a semiconductor LED
CN102569174A (en) * 2010-12-30 2012-07-11 新加坡商格罗方德半导体私人有限公司 Integrated circuit system with ultra-low K dielectric and method of manufacture thereof
KR101333306B1 (en) * 2010-12-30 2013-11-27 글로벌파운드리즈 싱가포르 피티이. 엘티디. Integrated circuit system with ultra-low k dielectric and method of manufacture thereof

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