KR20090116156A - Method for forming contact hole of semiconductor device - Google Patents

Method for forming contact hole of semiconductor device Download PDF

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KR20090116156A
KR20090116156A KR1020080041906A KR20080041906A KR20090116156A KR 20090116156 A KR20090116156 A KR 20090116156A KR 1020080041906 A KR1020080041906 A KR 1020080041906A KR 20080041906 A KR20080041906 A KR 20080041906A KR 20090116156 A KR20090116156 A KR 20090116156A
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South Korea
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contact hole
forming
photoresist pattern
semiconductor device
hard mask
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KR1020080041906A
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Korean (ko)
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남기원
박상수
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주식회사 하이닉스반도체
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Priority to KR1020080041906A priority Critical patent/KR20090116156A/en
Publication of KR20090116156A publication Critical patent/KR20090116156A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to improve yield by preventing a contact hole bridge phenomenon by forming a polymer layer on a photoresist pattern. CONSTITUTION: An interlayer insulation film, a hard mask(350), and a reflective prevention layer(360) are formed on a substrate. A photoresist pattern(370) for the contact hole is formed in an upper side of the reflective prevention layer. The reflective prevention layer and the hard mask are etched using the photoresist pattern as an etching barrier. A polymer layer(380) is formed in a front surface of the photoresist pattern using the gas with hydrogen. A contact hole is formed by etching the interlayer insulation layer using the photoresist pattern as the etching barrier. The hard mask is comprised of an amorphous carbon layer.

Description

반도체 장치의 콘택홀 형성 방법{METHOD FOR FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE}Contact hole formation method of a semiconductor device {METHOD FOR FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE}

본 발명은 반도체 장치 제조 방법에 관한 것으로, 보다 상세하게는 반도체 장치의 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device.

반도체 장치 집적도의 향상에 따라 셀 면적이 지속적으로 감소하고 있다. 따라서, 각 장치가 차지하는 면적이 감소하고 있으며, 이에 따라 미세한 패턴을 형성하기 위한 기술이 요구되고 있다.As the semiconductor device density increases, the cell area continues to decrease. Therefore, the area occupied by each device is decreasing, and accordingly, a technique for forming a fine pattern is required.

특히, 자기정렬콘택(Self Aligned Contact;SAC) 공정을 통해 콘택홀을 형성함에 있어서 콘택홀 간의 간격 또한 감소하고 있다. 이로 인하여 콘택홀 형성을 위한 층간 절연막 식각시 층간 절연막의 최상부가 손상되어 콘택홀 간의 브릿지 발생이 증가하고 있다. 또한, 이 과정에서 콘택홀 하부의 도전 패턴 예를 들어, 비트 라인의 하드마스크 질화막이 손상되는 등의 문제점이 발생하고 있다.In particular, in forming contact holes through a self aligned contact (SAC) process, the spacing between contact holes is also reduced. As a result, when the interlayer insulating layer is etched to form the contact hole, the uppermost portion of the interlayer insulating layer is damaged to increase the bridge generation between the contact holes. Further, in this process, there is a problem that the conductive pattern under the contact hole, for example, the hard mask nitride film of the bit line is damaged.

이하, 도면을 참조하여 종래기술에 따른 콘택홀 형성의 문제점을 상세히 살펴보도록 한다.Hereinafter, the problem of forming a contact hole according to the related art will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 종래기술에 따른 반도체 장치의 콘택홀 형성 방법을 나타내는 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the related art.

도 1a에 도시된 바와 같이, 랜딩 플러그 폴리실리콘(Landing Plug Poly silicon;LPP;110)을 포함하는 제1절연막(100)상에 비트 라인용 도전막(120) 및 하드마스크 질화막(130)을 증착한 후, 하드마스크 질화막(130) 및 비트 라인용 도전막(120)을 선택적으로 식각하여 비트 라인(BL)을 형성한다.As illustrated in FIG. 1A, a bit line conductive layer 120 and a hard mask nitride layer 130 are deposited on a first insulating layer 100 including a landing plug poly silicon (LPP) 110. Thereafter, the hard mask nitride film 130 and the bit line conductive film 120 are selectively etched to form a bit line BL.

이어서, 비트 라인(BL)이 형성된 결과물의 전체 구조상에 제2절연막(140)을 형성하고, 제2절연막(140)의 상부에 비정질탄소막(150) 및 반사방지막(160)을 차례로 형성한다. 이어서, 상기 반사방지막(160)의 상부에 콘택홀 영역을 노출시키는 포토레지스트 패턴(170)을 형성한다. Subsequently, the second insulating layer 140 is formed on the entire structure of the resultant bit line BL, and the amorphous carbon layer 150 and the anti-reflection layer 160 are sequentially formed on the second insulating layer 140. Next, a photoresist pattern 170 is formed on the anti-reflection film 160 to expose the contact hole region.

도 1b에 도시된 바와 같이, 포토레지스트 패턴(170)을 식각 베리어로 반사방지막(160) 및 비정질탄소막(150)을 식각한다. 이 과정에서, 포토레지스트 패턴(170)이 소정 정도 손상된다. As shown in FIG. 1B, the anti-reflection film 160 and the amorphous carbon film 150 are etched using the photoresist pattern 170 as an etching barrier. In this process, the photoresist pattern 170 is damaged to some extent.

도 1c에 도시된 바와 같이, 포토레지스트 패턴(170)을 식각 베리어로 제2절연막(140) 및 제1절연막(100)을 식각하여 랜딩 플러그 폴리실리콘(Landing Plug Poly silicon;LPP;110)을 노출시키는 콘택홀(t1)을 형성한다. 이 과정에서 제2절연막(140)의 최상부가 크게 손상되는 경우, 인접한 콘택홀이 연결되는 브릿지(bridge) 현상이 발생할 수 있다. 또한, 이와 같은 제2절연막(140)의 손상은 콘택홀(t1) 하부의 도전 패턴 예를 들어, 비트 라인(BL)의 하드마스크 질화막(130) 손상을 초래할 수 있다.As illustrated in FIG. 1C, the second insulating layer 140 and the first insulating layer 100 are etched using the photoresist pattern 170 as an etch barrier to expose Landing Plug Poly silicon (LPP) 110. Contact holes t1 are formed. In this process, when the uppermost portion of the second insulating layer 140 is largely damaged, a bridge phenomenon in which adjacent contact holes are connected may occur. In addition, the damage of the second insulating layer 140 may cause a damage of the conductive pattern under the contact hole t1, for example, the hard mask nitride layer 130 of the bit line BL.

특히, 반도체 장치 집적도가 증가할수록 포토레지스트 패턴(170)을 얇은 두께로 형성하기 때문에, 콘택홀(t1) 형성 과정에서 포토레지스트 패턴(170)의 손상 정도가 증가하여 콘택홀 브릿지 발생 및 하드마스크 질화막(130) 손상 가능성이 증가한다. 이러한 콘택홀 브릿지(bridge) 발생 및 하드마스크 질화막(130) 손상은 반도체 장치의 전기적 안정성을 저해하고, 반도체 장치의 제조 공정 수율을 초래한다.In particular, as the degree of integration of the semiconductor device increases, the photoresist pattern 170 is formed to a thinner thickness. Thus, the damage degree of the photoresist pattern 170 increases during the formation of the contact hole t1, resulting in the formation of a contact hole bridge and a hard mask nitride layer. 130 Increases the likelihood of damage. Such contact hole bridge generation and damage to the hard mask nitride layer 130 may hinder the electrical stability of the semiconductor device and result in a process yield of the semiconductor device.

도 2는 종래기술에 따른 콘택홀 형성 방법에 의해 콘택홀 브릿지 현상이 발생한 반도체 장치의 사진을 나타낸다. 여기서, (a)는 웨이퍼의 위치에 따른 콘택홀 브릿지 발생 밀도를 나타내고, (b)는 콘택홀 브릿지가 발생된 반도체 장치를 나타내는 사진이다.2 is a photograph of a semiconductor device in which a contact hole bridge phenomenon occurs by a contact hole forming method according to the related art. Here, (a) shows the contact hole bridge generation density according to the position of the wafer, and (b) is a photograph showing the semiconductor device in which the contact hole bridge has been generated.

(b)에 도시된 바와 같이, 콘택홀(t1)을 형성하는 과정에서 제2절연막(140)의 최상부가 손상됨으로써, 인접한 콘택홀이 상호 연결되는 브릿지 현상이 발생한다. 이러한 브릿지 현상은 (a)에 도시된 바와 같이, 웨이퍼의 에지(edge) 영역에 집중하여 발생한다.As shown in (b), the uppermost portion of the second insulating layer 140 is damaged in the process of forming the contact hole t1, so that a bridge phenomenon in which adjacent contact holes are interconnected occurs. This bridge phenomenon occurs as concentrated in the edge area of the wafer, as shown in (a).

본 발명은 상기와 같은 문제점을 해결하기 위해 제안된 것으로, 콘택홀 형성 공정에서, 포토레지스트 패턴 상에 추가로 폴리머막을 형성하는 반도체 장치의 콘택홀 형성 방법을 제공하는 것을 목적으로 한다.The present invention has been proposed to solve the above problems, and an object thereof is to provide a method for forming a contact hole in a semiconductor device in which a polymer film is further formed on a photoresist pattern in a contact hole forming process.

본 발명이 속한 기술 분야에서 통상의 지식을 가진 자는 본 명세서의 도면, 발명의 상세한 설명 및 특허청구범위로부터 본 발명의 다른 목적 및 장점을 쉽게 인식할 수 있다.Those skilled in the art to which the present invention pertains can easily recognize other objects and advantages of the present invention from the drawings, the detailed description of the invention, and the claims.

이러한 목적을 달성하기 위해 제안된 본 발명은 기판상에 층간 절연막, 하드마스크 및 반사방지막을 형성하는 단계; 상기 반사방지막의 상부에 콘택홀을 위한 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각 베리어로 상기 반사방지막 및 하드마스크를 식각하는 단계; 수소 포함 가스를 이용하여 상기 포토레지스트 패턴 전면에 폴리머막을 형성하는 단계; 및 상기 포토레지스트 패턴을 식각 베리어로 상기 층간 절연막을 식각하여 콘택홀을 형성하는 단계를 포함하는 것을 일 특징으로 한다.The present invention proposed to achieve the above object comprises the steps of forming an interlayer insulating film, hard mask and anti-reflection film on the substrate; Forming a photoresist pattern for contact holes on the anti-reflection film; Etching the anti-reflection film and the hard mask using the photoresist pattern as an etching barrier; Forming a polymer film on the entire surface of the photoresist pattern using a hydrogen containing gas; And forming a contact hole by etching the interlayer insulating layer using the photoresist pattern as an etching barrier.

본 발명에 따르면, 반도체 장치의 콘택홀을 형성함에 있어서, 포토레지스트 패턴 상에 추가로 폴리머막을 형성함으로써, 콘택홀 브릿지 현상을 방지할 수 있다. 또한, 콘택홀 하부의 도전 패턴 예를 들어, 비트 라인의 하드마스크 질화막 손상을 방지할 수 있다. According to the present invention, in forming the contact hole of the semiconductor device, by forming a polymer film on the photoresist pattern, the contact hole bridge phenomenon can be prevented. In addition, damage to the hard mask nitride layer of the conductive pattern under the contact hole, for example, the bit line, may be prevented.

따라서, 반도체 장치의 전기적 안정성을 도모하고, 반도체 장치 제조 공정의 수율을 향상시킬 수 있다.Therefore, the electrical stability of a semiconductor device can be aimed at and the yield of a semiconductor device manufacturing process can be improved.

이하에서는, 본 발명의 가장 바람직한 실시예가 설명된다. 도면에 있어서, 두께와 간격은 설명의 편의를 위하여 과장될 수 있다. 본 발명을 설명함에 있어서, 본 발명의 요지와 무관한 공지의 구성은 생략될 수 있다. 각 도면의 구성요소들에 참조 번호를 부가함에 있어서, 동일한 구성 요소들에 한해서는 비록 다른 도면상에 표시되더라도 가능한 한 동일한 번호를 가지도록 하고 있음에 유의하여야 한다.In the following, the most preferred embodiment of the present invention is described. In the drawings, thickness and spacing may be exaggerated for convenience of description. In describing the present invention, well-known structures irrelevant to the gist of the present invention may be omitted. In adding reference numerals to the components of each drawing, it should be noted that the same components as much as possible, even if displayed on different drawings.

도 3a 내지 도 3c는 본 발명의 일 실시예에 따른 콘택홀 형성 방법을 설명하기 위한 공정 단면도이다.3A to 3C are cross-sectional views illustrating a method of forming a contact hole according to an exemplary embodiment of the present invention.

도 3a에 도시된 바와 같이, 랜딩 플러그 폴리실리콘(Landing Plug Polysilicon;LPP;310)을 포함하는 제1절연막(300)상에 비트 라인용 도전막(320)을 증착한 후, 하드마스크 질화막(330) 및 비트 라인용 도전막(320)을 선택적으로 식각하여 비트 라인(BL)을 형성한다.As shown in FIG. 3A, after the bit line conductive layer 320 is deposited on the first insulating layer 300 including the landing plug polysilicon (LPP) 310, the hard mask nitride layer 330 is formed. ) And the bit line conductive film 320 are selectively etched to form the bit line BL.

이어서, 비트 라인(BL)이 형성된 결과물의 전체 구조상에 제2절연막(340)을 형성한다. 여기서, 제2절연막(340)은 산화막으로 형성되는 것이 바람직하다. Subsequently, a second insulating layer 340 is formed on the entire structure of the resultant bit line BL. Here, the second insulating film 340 is preferably formed of an oxide film.

이어서, 제2절연막(340)의 상부에 하드마스크(350) 및 반사방지막(360)을 차례로 형성한다. 여기서, 하드마스크(350)는 비정질탄소막으로 형성되는 것이 바람직하다. 상기 반사방지막(360)의 상부에는 콘택홀 영역을 노출시키는 포토레지스트 패턴(370)을 형성한다. Subsequently, a hard mask 350 and an antireflection film 360 are sequentially formed on the second insulating layer 340. Here, the hard mask 350 is preferably formed of an amorphous carbon film. A photoresist pattern 370 is formed on the anti-reflection film 360 to expose the contact hole region.

도 3b에 도시된 바와 같이, 포토레지스트 패턴(370)을 식각 베리어로 반사방지막(360) 및 하드마스크(350)를 식각한다. 이때, 식각 가스는 CF4가스, O2가스 또는 N2가스를 사용하는 것이 바람직하다. 이로써, 제2절연막(340)의 상부가 노출되며, 이 과정에서 포토레지스트 패턴(370)이 손상될 수 있다.As shown in FIG. 3B, the anti-reflection film 360 and the hard mask 350 are etched using the photoresist pattern 370 as an etching barrier. At this time, the etching gas is preferably used CF 4 gas, O 2 gas or N 2 gas. As a result, an upper portion of the second insulating layer 340 is exposed, and the photoresist pattern 370 may be damaged in this process.

도 3c에 도시된 바와 같이, 포토레지스트 패턴(370)의 전면에 폴리머막(380)을 형성하고, 포토레지스트 패턴(370)을 식각 베리어로 제2절연막(340) 및 제1절연막(300)을 식각함으로써 랜딩 플러그 폴리실리콘(Landing Plug Polysilicon;LPP;310)을 노출시키는 콘택홀(t2)를 형성한다. As shown in FIG. 3C, the polymer layer 380 is formed on the entire surface of the photoresist pattern 370, and the second insulating layer 340 and the first insulating layer 300 are formed using the photoresist pattern 370 as an etching barrier. By etching, a contact hole t2 exposing the landing plug polysilicon (LPP) 310 is formed.

이때, 폴리머막(380)을 형성한 후, 폴리머막(380)이 형성된 포토레지스트 패턴(370)을 식각 베리어로 제2절연막(340) 및 제1절연막(300)을 식각하는 제1방법과, 폴리머막(380)을 형성하면서 동시에 포토레지스트 패턴(370)을 식각 베리어로 제2절연막(340) 및 제1절연막(300)을 식각하는 제2방법이 가능하다.In this case, after the polymer film 380 is formed, the first method of etching the second insulating film 340 and the first insulating film 300 using the photoresist pattern 370 on which the polymer film 380 is formed as an etching barrier, A second method of etching the second insulating layer 340 and the first insulating layer 300 using the photoresist pattern 370 as an etching barrier while forming the polymer layer 380 is possible.

제1방법의 경우, 수소 포함 가스를 이용하여 폴리머막(380)을 형성하는 것이 바람직하다. 여기서, 수소 포함 가스로는 CH4가스 또는 H2 가스를 이용하는 것이 더 욱 바람직하다. In the case of the first method, it is preferable to form the polymer film 380 using hydrogen-containing gas. Here, the hydrogen containing gas is CH 4 gas or H 2 It is even more preferable to use a gas.

이때, 수소 포함 가스에 포함된 수소(H)와 포토레지스트 패턴(370)에 포함된 탄소(C)가 반응하여 폴리머를 형성시키며, 상기 폴리머는 포토레지스트 패턴(370)의 전면에 증착되어 폴리머막(380)을 형성한다. 이로써, 이전 공정에 의해 손상된 포토레지스트 패턴(370)을 보완할 뿐만 아니라, 후속 공정에서의 포토레지스트 패턴(370) 손상을 방지할 수 있다.In this case, hydrogen (H) included in the hydrogen-containing gas and carbon (C) included in the photoresist pattern 370 react to form a polymer, and the polymer is deposited on the entire surface of the photoresist pattern 370 to form a polymer. 380 is formed. As a result, not only the photoresist pattern 370 damaged by the previous process can be compensated, but also the damage of the photoresist pattern 370 in the subsequent process can be prevented.

이어서, 전면에 폴리머막(380)이 형성된 포토레지스트 패턴(370)을 식각 베리어로 제2절연막(340) 및 제1절연막(300)을 식각하여 랜딩 플러그 폴리실리콘(Landing Plug Polysilicon;LPP;310)을 노출시키는 콘택홀(t2)을 형성한다. Next, the second insulating layer 340 and the first insulating layer 300 are etched using the photoresist pattern 370 having the polymer layer 380 formed thereon as an etching barrier, and the landing plug polysilicon (LPP; 310) is etched. A contact hole t2 is formed to expose the gap.

제2방법의 경우, 포토레지스트 패턴(370)을 식각베리어로 제2절연막(340) 및 제1절연막(300)을 식각하는 과정에서, 식각 가스에 수소 포함 가스를 추가한다. 이로써, 포토래지스트 패턴(370) 전면에 폴리머막(380)을 형성하면서 콘택홀(t2)을 형성할 수 있다.In the second method, in the process of etching the second insulating layer 340 and the first insulating layer 300 using the photoresist pattern 370 as an etching barrier, hydrogen-containing gas is added to the etching gas. As a result, the contact hole t2 may be formed while the polymer layer 380 is formed over the photoresist pattern 370.

제2절연막(340)이 산화막인 경우에, 수소 포함 가스를 이용하면 하드마스크 질화막(330) 식각률을 상대적으로 감소시키고, 제2절연막(340) 식각률을 증가시킬 수 있다. 따라서, 하드마스크 질화막(330)의 손상을 크게 감소시킬 수 있다.In the case where the second insulating layer 340 is an oxide layer, the hydrogen-containing gas may relatively reduce the etching rate of the hard mask nitride layer 330 and increase the etching rate of the second insulating layer 340. Therefore, damage to the hard mask nitride film 330 can be greatly reduced.

이때, 식각 가스에 아르곤(Ar) 가스를 첨가할 수 있다. 그러나, 콘택홀(t2) 하부의 도전 패턴 예를 들어, 비트라인(BL)의 하드마스크 질화막(330) 손상을 방지하기 위하여, 하드마스크 질화막(330) 식각률을 증가시키는 가스 예를 들어, 불소계 가스는 첨가하지 않는 것이 바람직하다.In this case, argon (Ar) gas may be added to the etching gas. However, in order to prevent damage to the conductive pattern under the contact hole t2, for example, the hard mask nitride film 330 of the bit line BL, a gas for increasing the etching rate of the hard mask nitride film 330, for example, a fluorine-based gas. Is preferably not added.

도 4는 본 발명의 일 실시예에 따른 콘택홀 형성 방법에 의해 콘택홀 브릿지 발생이 감소된 반도체 장치의 사진을 나타낸다. 특히, 웨이퍼 내의 위치에 따른 콘택홀 브릿지의 발생 밀도를 나타내도록 도시되었다.4 is a photograph of a semiconductor device in which contact hole bridge generation is reduced by a method of forming a contact hole according to an embodiment of the present invention. In particular, it is shown to represent the density of occurrence of the contact hole bridge according to the position in the wafer.

도시된 바와 같이, 포토레지스트 패턴(370) 상에 추가로 폴리머막(380)을 형성함으로써, 콘택홀 브릿지 발생을 감소시킬 수 있다. 특히, 웨이퍼 에지(edge) 영역에서의 콘택홀 브릿지 발생을 현저하게 감소시킬 수 있다.As illustrated, by forming the polymer layer 380 on the photoresist pattern 370, the generation of contact hole bridges may be reduced. In particular, the generation of contact hole bridges in the wafer edge region can be significantly reduced.

본 발명의 기술 사상은 상기 바람직한 실시예들에 따라 구체적으로 기록되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

도 1a 내지 도 1c는 종래기술에 따른 콘택홀 형성 방법을 설명하기 위한 공정 단면도.1A to 1C are cross-sectional views illustrating a method for forming a contact hole according to the related art.

도 2는 종래기술에 따른 콘택홀 형성 방법에 의해 콘택홀 브릿지가 발생한 반도체 장치의 사진.2 is a photograph of a semiconductor device in which a contact hole bridge is generated by a method for forming a contact hole according to the related art.

도 3a 내지 도 3c는 본 발명의 일 실시예에 따른 콘택홀 형성 방법을 설명하기 위한 공정 단면도.3A to 3C are cross-sectional views illustrating a method of forming a contact hole according to an embodiment of the present invention.

도 4는 본 발명의 일 실시예에 따른 콘택홀 형성 방법에 의해 콘택홀 브릿지 발생이 감소된 반도체 장치의 사진.4 is a photograph of a semiconductor device in which contact hole bridge generation is reduced by a method of forming a contact hole according to an embodiment of the present invention.

Claims (6)

기판상에 층간 절연막, 하드마스크 및 반사방지막을 형성하는 단계;Forming an interlayer insulating film, hard mask, and anti-reflection film on the substrate; 상기 반사방지막의 상부에 콘택홀을 위한 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern for contact holes on the anti-reflection film; 상기 포토레지스트 패턴을 식각 베리어로 상기 반사방지막 및 하드마스크를 식각하는 단계;Etching the anti-reflection film and the hard mask using the photoresist pattern as an etching barrier; 수소 포함 가스를 이용하여 상기 포토레지스트 패턴 전면에 폴리머막을 형성하는 단계; 및Forming a polymer film on the entire surface of the photoresist pattern using a hydrogen containing gas; And 상기 포토레지스트 패턴을 식각 베리어로 상기 층간 절연막을 식각하여 콘택홀을 형성하는 단계Etching the interlayer insulating layer using the photoresist pattern as an etching barrier to form a contact hole 를 포함하는 반도체 장치의 콘택홀 형성 방법.Contact hole forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 폴리머막은,The polymer film, 상기 수소 포함 가스의 수소(H)와 상기 포토레지스트 패턴의 탄소(C)가 반응하여 형성되는Hydrogen (H) of the hydrogen-containing gas and carbon (C) of the photoresist pattern are formed by reaction 반도체 장치의 콘택홀 형성 방법.Method for forming a contact hole in a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 하드마스크는,The hard mask, 비정질 탄소막으로 이루어지는Consisting of amorphous carbon film 반도체 장치의 콘택홀 형성 방법.Method for forming a contact hole in a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 폴리머막 형성 단계 및 상기 층간 절연막 식각 단계는,The polymer film forming step and the interlayer insulating film etching step, 동시에 수행되는Performed at the same time 반도체 장치의 콘택홀 형성 방법.Method for forming a contact hole in a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 수소 포함 가스는,The hydrogen containing gas, CH4 또는 H2인CH 4 or H 2 phosphorus 반도체 장치의 콘택홀 형성 방법.Method for forming a contact hole in a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 반사방지막 및 하드마스크 식각 단계는,The anti-reflection film and hard mask etching step, CF4가스, O2가스 또는 N2가스를 이용하여 수행되는Carried out with CF 4 gas, O 2 gas or N 2 gas 반도체 장치의 콘택홀 형성 방법.Method for forming a contact hole in a semiconductor device.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9576902B2 (en) 2014-01-28 2017-02-21 Samsung Electronics Co., Ltd. Semiconductor device including landing pad

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9576902B2 (en) 2014-01-28 2017-02-21 Samsung Electronics Co., Ltd. Semiconductor device including landing pad

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