KR101024814B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention increases the contact area between the landing plug 50 and the active region 12 by reducing the contact resistance by forming a recess in the device isolation structure to form an active region in contact with the landing plug in a pin shape. Disclosed are techniques that can be improved.

Landing plug, contact resistance, operating characteristics, recessed, SOD

Description

Method for manufacturing semiconductor device

The present invention relates to a semiconductor device and a method for forming the same, and more particularly, by forming a recess in a device isolation structure to form an active region in contact with the landing plug in a pin shape, thereby increasing the contact area between the landing plug and the active region. The present invention relates to a method of forming a semiconductor device capable of improving contact characteristics by reducing contact resistance.

As the integration of semiconductor devices is accelerated, various structure layers constituting the device are arranged in a stacked structure.

For this reason, a contact plug process technology has been proposed to connect the upper conductive layer and the lower conductive layer.

In such a contact plug forming process, the landing plug contact has a larger area at the upper part than the lower contact part to expand the contact area with a minimum area at the lower part and to increase the process margin for the subsequent process at the upper part. contact process has been proposed.

However, in order to form such a landing contact plug, there is a difficulty in etching between structures having a high aspect ratio, wherein an etching profile between two materials, for example, an etching selectivity between an oxide film and a nitride film, is used. Self Align Contact (hereinafter referred to as SAC) process technology was introduced.

For the SAC etching process, CF and CHF series gases are used. In this case, in order to prevent an attack on the lower conductive pattern, an etch stop film and a spacer using a nitride film are required.

A typical SAC process forms a device isolation film (device isolation structure) defining an active region on a semiconductor substrate, and forms a gate over the semiconductor substrate.

Subsequently, a nitride film for spacers is formed over the entire surface including the gate.

Then, an interlayer insulating film is formed on the semiconductor substrate and the gate, and then chemical mechanical polishing (CMP) is performed until the interlayer insulating film is equal to the height of the gate stack. At this time, when the nitride film on the gate starts to be exposed, the polishing rate decreases and etching is inhibited.

Next, the amorphous carbon film for the hard mask and the photosensitive film are sequentially formed, and the oxide film is etched until the spacer nitride film is exposed through the exposure and development processes for the photosensitive film.

Next, the nitride film for the spacer is etched using the hard mask pattern etched by the photoresist pattern as a etch mask, the polysilicon layer for landing plug is deposited so that all exposed semiconductor substrates are embedded, and then an etch back process or a CMP is performed. To complete the landing plug defined by the interlayer insulating film.

However, the shape of the landing plug formed according to the prior art has a problem that the operating characteristics of the chip is reduced due to the ever-increasing contact resistance as the cell size is reduced.

An object of the present invention is to provide a method of forming a semiconductor device capable of increasing the contact area between the landing plug and the active region and reducing the contact resistance to improve operating characteristics.

The method of forming a semiconductor device according to the present invention

Forming a device isolation structure defining an active region in the semiconductor substrate;

Etching the device isolation structure to a predetermined depth using a recess gate mask to form a line-type recess;

Filling the recess with an insulating film;

Forming a gate stack on the active region;

Forming an interlayer insulating film on the semiconductor substrate including the gate stack;

Selectively etching the interlayer insulating film and the insulating film to form a landing plug contact hole; And

Filling the landing plug contact hole with a conductive material to form a landing plug.

In addition, forming the device isolation structure is

Forming a trench defining the active region;

Embedding SOD in the bottom of the trench; And

Embedding the HDP on the SOD;

Forming an oxide film on a surface of the semiconductor substrate of the trench;

Forming a nitride film to prevent oxidation of the surface of the semiconductor substrate in the trench;

Forming the recess

Depositing a photoresist film on the semiconductor substrate including the device isolation structure;

Forming a photoresist pattern by performing an exposure and development process on the photoresist using the recess gate mask; And

Etching the device isolation structure by using the photoresist pattern as an etching mask;

The photosensitive film is negative type,

In the forming of the recess, the active region is partially etched so that the active region has a fin shape.

The insulating film is SOD,

Forming a gate recess in the active region;

The forming of the gate stack includes forming a spacer layer on the gate stack and on the insulating layer.

The spacer film is formed of a nitride film,

Forming the landing plug contact hole

Selectively etching the interlayer insulating layer using the spacer layer as an etch stop layer; And

And selectively etching the spacer layer and the insulating layer to expose the active region.

The present invention has the effect of increasing the contact area between the landing plug and the active region and reducing the contact resistance to improve the operating characteristics by forming a recess in the device isolation structure to form a pin shape of the active region that the landing plug contacts. .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

1A to 1J are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention. Here, (i) is a sectional view perpendicular to the longitudinal direction of the gate stack, and (ii) is a sectional view parallel to the longitudinal direction of the gate stack.

Referring to FIG. 1A, after forming a trench defining an active region 12 in a semiconductor substrate 10, an oxide film 14 is deposited to a thickness of 80 to 100 μm on the surface of the semiconductor substrate 10, and then a semiconductor substrate is formed. (10) A nitride film 16 for preventing oxidation of the surface is formed to a thickness of 60 to 80 mm 3. Next, an oxide film for protecting the nitride film 16 is deposited to a thickness of 50 to 70 GPa.

Then, the SOD (Spin On Dielectric) 22 is buried in the lower portion of the trench at a thickness of 2000 to 3000 microns, and the HDP (High Density Plasma) 24 is embedded at the upper portion of the SOD 22 at a thickness of 2000 to 3000 microns. The structure 20 is formed.

A photoresist is deposited on the semiconductor substrate 10 including the active region 12 and the device isolation structure 20, and the recess gate region is defined by performing exposure and development processes using a mask for forming the recess gate. The photosensitive film pattern 26 is formed. In this case, the photoresist pattern 26 is formed in the recess gate region through an exposure and development process using a negative type photoresist.

Referring to FIG. 1B, an HDP 24 of the device isolation structure 20 is etched to a predetermined depth by using the photoresist pattern 26 as an etching mask to form a line-type recess in the device isolation structure 20. At this time, a portion of the active region 12 in contact with the landing plug is etched to form a fin.

1C and 1D, the SOD 28 is deposited on the front surface including the recess of the device isolation structure 20, and the recess formed in the device isolation structure 20 through the CMP is disposed in the SOD 28. Landfill

Referring to FIG. 1E, a recess gate stack 30 is formed in the active region 12. Here, the recess gate stack 30 forms a recess in the active region 12 using a recess gate forming mask, and forms a gate oxide layer 31 on the front surface including the recess, and then recesses the recess gate stack 30. Is formed by laminating the conductive film 32, the metal silicide film 33, and the hard mask film 34 that fill the gaps. In addition, a nitride film 35 for spacers is formed on the top surface including the recess gate stack 30.

After the interlayer insulating film 40 is formed on the semiconductor substrate 10 including the recess gate stack 30, an amorphous carbon layer 42 and an anti-reflection film 44 for hard mask are deposited. Next, a photoresist film is deposited on the anti-reflection film 44 and a photoresist pattern 46 defining a landing plug is formed through an exposure and development process using a mask for self alignment contact (SAC).

Referring to FIG. 1F, the anti-reflection film 44 and the amorphous carbon layer 42 are etched using the photoresist pattern 46 as an etching mask to form a hard mask pattern.

Referring to FIG. 1G, the interlayer insulating layer 40 is etched using the hard mask pattern as an etch mask to form a landing plug contact hole. At this time, the spacer nitride film 35 serves as an etch stop film.

Referring to FIG. 1H, the nitride nitride layer 35 and the SOD 28 exposed by the landing plug contact hole are etched to expose the active region 12.

1I and 1J, polysilicon 48 filling the landing plug contact hole is deposited, and the landing plug 50 is formed through CMP.

Since the present invention as described above forms a recess in the device isolation structure to form an active region contacting the landing plug in a pin shape, the contact area of the landing plug 50 and the active region is increased to reduce contact resistance. Properties can be improved.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 1J are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Description of the Related Art [0002]

20: semiconductor substrate

22a, 22b: bit line contacts

24a, 24b: bit line

26a, 26b, 26c: interlayer insulating film

Claims (12)

Forming a device isolation structure defining an active region in the semiconductor substrate; Etching the device isolation structure to a predetermined depth using a recess gate mask to form a line-type recess; Filling the recess with an insulating film; Forming a gate stack on the active region; Forming an interlayer insulating film on the semiconductor substrate including the gate stack; Selectively etching the interlayer insulating film and the insulating film to form a landing plug contact hole; And Filling the landing plug contact hole with a conductive material to form a landing plug, And forming a portion of the recess, wherein the active region is partially etched to form a fin. The method of claim 1, Forming the device isolation structure is Forming a trench defining the active region; Embedding SOD in the bottom of the trench; And And embedding the HDP on the SOD. The method of claim 2, And forming an oxide film on a surface of the semiconductor substrate of the trench. The method of claim 3, wherein And forming a nitride film to prevent oxidation of the surface of the semiconductor substrate in the trench. The method of claim 1, Forming the recess Depositing a photoresist on the semiconductor substrate including the device isolation structure; Forming a photoresist pattern by performing an exposure and development process on the photoresist using the recess gate mask; And Etching the device isolation structure by using the photoresist pattern as an etching mask. The method of claim 5, The photosensitive film is a semiconductor device forming method, characterized in that the negative type. delete The method of claim 1, And the insulating film is SOD. The method of claim 1, And forming a gate recess in the active region. The method of claim 1, The forming of the gate stack includes forming a spacer layer on the gate stack and on the insulating layer. 11. The method of claim 10, And the spacer film is formed of a nitride film. 11. The method of claim 10, Forming the landing plug contact hole Selectively etching the interlayer insulating layer using the spacer layer as an etch stop layer; And Selectively etching the spacer layer and the insulating layer to expose the active region.

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