KR20090070965A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20090070965A
KR20090070965A KR1020070139140A KR20070139140A KR20090070965A KR 20090070965 A KR20090070965 A KR 20090070965A KR 1020070139140 A KR1020070139140 A KR 1020070139140A KR 20070139140 A KR20070139140 A KR 20070139140A KR 20090070965 A KR20090070965 A KR 20090070965A
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South Korea
Prior art keywords
etching
semiconductor device
layer
manufacturing
pattern
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KR1020070139140A
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Korean (ko)
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김동현
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주식회사 하이닉스반도체
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Publication of KR20090070965A publication Critical patent/KR20090070965A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

A method for manufacturing a semiconductor device is provided to prevent the loss of a sidewall of a sub hole by performing an isotropic etching in the sidewall of the sub hole forming an etching barrier layer. A device isolation layer(22) is formed in a substrate(21). A recess pattern(23) is formed in the substrate. A gate dielectric is formed on the substrate including the recess pattern. A part of a gate pattern(24) is reclaimed to the recess pattern and the remaining is protruded to the upper part of the substrate. A first electrode(24A), a second electrode(24B), and a gate hard mask(24C) are laminated in the gate pattern. A sidewall protective layer(25) is formed in the sidewall of the gate pattern. A photoresist pattern(27) is formed on the interlayer dielectric(26).

Description

반도체 소자의 제조방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자 제조기술에 관한 것으로, 특히 반도체 소자의 콘택홀 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a method for manufacturing a contact hole in a semiconductor device.

반도체 소자가 고집적화 됨에 따라 패턴 간의 간격도 좁아지고 있다. 따라서, 패턴 사이의 공간이 부족하게 된다. As semiconductor devices are highly integrated, the spacing between patterns is narrowing. Thus, there is a lack of space between the patterns.

한편, 콘택 플러그를 위한 콘택홀 형성 공정시 식각 후 발생한 손실층(Damaged Layer)을 제거하기 위해 후처리 식각(Post Etch Treatment)을 실시하고 있다. 후처리 식각은 통상 등방성 식각으로 실시되는데 이때, 콘택홀의 측면이 식각되어 콘택홀의 폭이 넓어진다.Meanwhile, in order to remove a lost layer generated after etching in the process of forming a contact hole for a contact plug, post etching is performed. Post-treatment etching is usually performed by isotropic etching, in which side surfaces of the contact holes are etched to widen the contact holes.

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a에 도시된 바와 같이, 기판(11)에 리세스패턴(12)을 형성하고, 리세스패턴(12)에 일부 매립되고 나머지는 기판(11) 상부로 돌출되는 게이트패턴(13)을 형성한다. 게이트패턴(13)은 폴리실리콘전극(13A), 텅스텐전극(13B) 및 게이트하드마스크질화막(13C)의 적층구조로 형성될 수 있다.As shown in FIG. 1A, a recess pattern 12 is formed in the substrate 11, and a gate pattern 13 is formed to be partially embedded in the recess pattern 12, and the rest protrudes above the substrate 11. do. The gate pattern 13 may be formed as a stacked structure of the polysilicon electrode 13A, the tungsten electrode 13B, and the gate hard mask nitride film 13C.

이어서, 게이트패턴(13)의 측벽에 게이트스페이서질화막(14)을 형성하고, 게이트패턴(13) 사이를 채우도록 층간산화막(15)을 형성한다.Subsequently, the gate spacer nitride film 14 is formed on the sidewall of the gate pattern 13, and the interlayer oxide film 15 is formed to fill the gate pattern 13.

이어서, 층간산화막(15) 상에 하드마스크패턴(16)을 형성하고, 자기정렬콘택식각(Self Aligned Contact Etch) 공정을 실시하여 콘택홀(17)을 형성한다. 또한, 콘택홀(17) 하부의 기판(11)을 일정깊이 식각하여 서브홀(18, Sub Hole)을 형성한다. 서브홀(18)은 기판(11)과 후속 랜딩 플러그 콘택(Landing Plug Contact)과의 접촉면적을 증가시켜 콘택 저항을 감소시키기 위한 것이다. Subsequently, a hard mask pattern 16 is formed on the interlayer oxide layer 15, and a contact hole 17 is formed by performing a self aligned contact etching process. In addition, the substrate 11 under the contact hole 17 is etched to a predetermined depth to form a sub hole 18. The subhole 18 is to increase the contact area between the substrate 11 and subsequent landing plug contacts to reduce the contact resistance.

이때, 서브홀(18)을 형성하기 위한 식각공정에서 서브홀(18)의 바닥부에 식각에 의한 손실층(19, Damaged Layer)이 형성된다.At this time, in the etching process for forming the sub-holes 18, a damaged layer 19 by etching is formed at the bottom of the sub-holes 18.

도 1b에 도시된 바와 같이, 손실층(19)을 제거하기 위한 후처리 식각을 진행한다. 후처리 식각은 등방성 식각으로 진행되며, 후처리 식각에 의해 손실층(19)이 제거된다.As shown in FIG. 1B, post-treatment etching is performed to remove the loss layer 19. The post-treatment etching proceeds to isotropic etching, and the loss layer 19 is removed by the post-treatment etching.

위와 같이, 종래 기술은 콘택홀(17)을 형성한 후, 후속 랜딩 플러그 콘택의 콘택저항 감소를 위해 서브홀(18)을 형성하고 있으며, 서브홀(18)을 형성하는 공정에서 생기는 손실층(19)을 제거하기 위해 등방성 식각으로 후처리 식각을 진행하고 있다.As described above, in the related art, after the contact hole 17 is formed, the sub hole 18 is formed to reduce the contact resistance of the subsequent landing plug contact, and the loss layer generated in the process of forming the sub hole 18 ( Post-treatment etching is performed with isotropic etching to remove 19).

그러나, 종래 기술은 손실층(18) 제거를 위한 후처리 식각시 등방성 식각에 의해 서브홀(18)의 측벽이 식각되고, 이에 따라 리세스패턴(12)에 매립된 게이트패 턴(13)과의 거리(Ｄ)가 감소하는 문제점이 있다. 또한, 서브홀(18)과 게이트패턴(13) 간의 거리가 감소하게 되면, 공간 부족에 의한 누설전류(Leakage)가 발생하게 된다.However, in the prior art, the sidewalls of the sub-holes 18 are etched by isotropic etching during the post-treatment etching for removing the loss layer 18, and thus the gate patterns 13 embedded in the recess patterns 12 are formed. There is a problem that the distance D is reduced. In addition, when the distance between the subhole 18 and the gate pattern 13 is reduced, leakage current due to insufficient space is generated.

특히, 이러한 문제점은 리세스패턴(12)을 갖는 게이트패턴(13) 외에 평판형, 핀형 및 새들형 게이트패턴에서도 발생된다. In particular, this problem also occurs in the planar, fin and saddle gate patterns in addition to the gate pattern 13 having the recess pattern 12.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 후처리 식각시 서브홀의 측면식각을 방지할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device capable of preventing side etching of the sub-hole during the post-treatment etching.

또한, 패턴 간의 공간 부족에 의한 누설전류를 방지할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing leakage current due to lack of space between patterns.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 기판에 패턴을 형성하는 단계; 상기 패턴 사이를 매립하는 층간절연막을 형성하는 단계; 상기 층간절연막을 식각하여 상기 패턴 사이에 콘택홀을 형성하는 단계; 상기 콘택홀 하부의 상기 기판을 식각하여 서브홀을 형성하는 단계; 상기 서브홀의 측벽에 식각배리어막을 형성하는 단계; 상기 식각배리어막을 식각장벽으로 등방성식각을 진행하여 상기 서브홀 형성시 생성된 손실층을 제거하는 단계를 포함하는 것을 특징으로 한다.Method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a pattern on the substrate; Forming an interlayer insulating film to fill the gaps between the patterns; Etching the interlayer insulating layer to form contact holes between the patterns; Etching the substrate under the contact hole to form a subhole; Forming an etching barrier layer on sidewalls of the sub-holes; And isotropically etching the etch barrier layer into the etch barrier to remove the loss layer formed during the formation of the sub-holes.

특히, 식각배리어막은 절연막일 수 있고, 식각배리어막은 기판과 식각선택비를 갖는 물질일 수 있으며, 식각배리어막은 산화막 또는 질화막일 수 있다.In particular, the etching barrier film may be an insulating film, the etching barrier film may be a material having an etching selectivity with respect to the substrate, and the etching barrier film may be an oxide film or a nitride film.

또한, 식각배리어막을 형성하는 단계는, 서브홀을 포함하는 기판 전면에 절연막을 형성하는 단계; 상기 손실층이 오픈되는 타겟으로 전면식각을 실시하여 상 기 절연막을 상기 서브홀의 측벽에 잔류시키는 단계를 포함할 수 있으며, 식각배리어막은 10Å∼100Å의 두께일 수 있다. In addition, the forming of the etching barrier layer may include forming an insulating layer on the entire surface of the substrate including the sub-holes; And etching the entire surface with the target to which the loss layer is opened, thereby leaving the insulating layer on the sidewalls of the sub-holes. The etching barrier layer may have a thickness of about 10 μs to about 100 μs.

또한, 등방성식각은 상기 기판과 식각배리어막의 선택비가 1∼10:1의 비율을 갖는 조건으로 실시하되, 등방성식각은 플루오린을 포함하는 가스와 O2, N2 및 Ar로 이루어진 그룹 중에서 선택된 어느 하나의 혼합가스로 실시할 수 있고, 플루오린을 포함하는 가스는 불화탄소 또는 불화질소가스일 수 있다. In addition, the isotropic etching is performed under the condition that the selectivity ratio between the substrate and the etching barrier layer is 1 to 10: 1, and the isotropic etching is selected from the group consisting of fluorine-containing gas and O 2 , N 2 and Ar. It may be carried out with one mixed gas, the gas containing fluorine may be carbon fluoride or nitrogen fluoride gas.

상술한 본 발명에 의한 반도체 소자의 제조방법은 식각시 발생한 손실층을 제거하기 위한 후처리 식각 전에 서브홀의 측벽에 식각배리어막을 형성한 후 등방성식각을 진행하여 서브홀의 측벽을 보호함으로써 서브홀의 측벽 손실을 방지할 수 있는 효과가 있다. In the method of manufacturing a semiconductor device according to the present invention described above, an etching barrier film is formed on the sidewalls of the subholes before the post-processing etching to remove the loss layer generated during the etching, and then isotropic etching is performed to protect the sidewalls of the subholes. There is an effect that can prevent.

따라서, 패턴 간의 공간 부족에 의한 누설 전류를 방지하고, 콘택저항을 낮출 수 있는 효과가 있다. Therefore, there is an effect of preventing leakage current due to lack of space between patterns and lowering the contact resistance.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 기판(21)에 소자분리막(22)을 형성한다. 기판(21)은 DRAM공정이 진행되는 반도체(실리콘) 기판일 수 있고, 소자분리막(22)을 활성영역을 정의하기 위한 것으로, STI(Shallow Trench Isolation) 공정으로 형성할 수 있다.As shown in FIG. 2A, the device isolation layer 22 is formed on the substrate 21. The substrate 21 may be a semiconductor (silicon) substrate in which a DRAM process is performed, and the device isolation layer 22 is used to define an active region, and may be formed by a shallow trench isolation (STI) process.

이어서, 기판(21)에 리세스패턴(23)을 형성한다. 리세스패턴(23)은 채널길이(Channel Length)를 증가시켜 리프레시(Refresh) 특성을 개선하기 위한 것으로, 본 발명에서는 'Ｕ'자형으로 형성하고 있으나, 'Ｕ'자형 외에 다각형의 리세스패턴(23)으로도 형성할 수 있다.Subsequently, a recess pattern 23 is formed on the substrate 21. The recess pattern 23 is for improving the refresh characteristic by increasing the channel length. In the present invention, the recess pattern 23 is formed in a 'Ｕ' shape, but in addition to the 'Ｕ' shape, a polygonal recess pattern ( 23) can also be formed.

이어서, 리세스패턴(23)을 포함하는 기판(21) 상에 게이트절연막(도시생략)을 형성한다. 게이트절연막은 산화막계열로 형성할 수 있다.Subsequently, a gate insulating film (not shown) is formed on the substrate 21 including the recess pattern 23. The gate insulating film may be formed of an oxide film series.

이어서, 리세스패턴(23)에 일부 매립되고 나머지는 기판(21) 상부로 돌출되는 게이트패턴(24)을 형성한다. 게이트패턴(24)은 제1전극(24A), 제2전극(24B) 및 게이트하드마스크(24C)의 적층구조일 수 있고, 제1전극(24A)은 폴리실리콘전극일 수 있고, 제2전극(24B)은 텅스텐일 수 있고, 게이트하드마스크(24C)는 질화막일 수 있다.Subsequently, a gate pattern 24 is partially formed in the recess pattern 23 and the remaining part protrudes over the substrate 21. The gate pattern 24 may be a stacked structure of the first electrode 24A, the second electrode 24B, and the gate hard mask 24C, the first electrode 24A may be a polysilicon electrode, and the second electrode 24B may be tungsten, and the gate hard mask 24C may be a nitride film.

이어서, 게이트패턴(24)의 측벽에 측벽보호막(25)을 형성한다. 측벽보호막(25)은 후속 공정에서 게이트패턴(24)의 측벽을 보호하기 위한 것으로, 절연물질로 형성하되 바람직하게는 질화막으로 형성할 수 있다.Subsequently, a sidewall protective film 25 is formed on the sidewall of the gate pattern 24. The sidewall protection layer 25 is to protect the sidewall of the gate pattern 24 in a subsequent process, and may be formed of an insulating material, but preferably, a nitride film.

이어서, 게이트패턴(24) 사이를 매립하는 층간절연막(26)을 형성한다. 층간절연막(26)은 게이트패턴(24) 사이를 충분히 매립하도록 산화막을 형성한 후, 게이트하드마스크(24C)가 드러나는 타겟으로 평탄화하여 형성할 수 있다. 이때, 평탄화는 화학적기계적연마(Chemical Mechanical Poslishing) 또는 에치백(Etch Back) 공정으로 실시할 수 있다. Next, an interlayer insulating film 26 is formed to fill the gate patterns 24. The interlayer insulating layer 26 may be formed by forming an oxide layer so as to sufficiently fill the gate patterns 24 and then planarizing the target to expose the gate hard mask 24C. In this case, planarization may be performed by chemical mechanical polishing or etching back.

이어서, 층간절연막(26) 상에 감광막패턴(27)을 형성한다. 감광막패턴(27)은 층간절연막(26) 상에 감광막을 코팅하고, 노광 및 현상으로 콘택홀 예정지역이 오픈되도록 패터닝하여 형성할 수 있다. 또한, 감광막패턴(27) 하부에 하드마스크패턴을 형성하여 후속 콘택홀 식각시 식각마진을 확보할 수 있다. Subsequently, a photosensitive film pattern 27 is formed on the interlayer insulating film 26. The photoresist pattern 27 may be formed by coating a photoresist on the interlayer insulating layer 26 and patterning the contact hole predetermined region to be opened by exposure and development. In addition, a hard mask pattern may be formed under the photoresist pattern 27 to secure an etching margin during subsequent contact hole etching.

도 2b에 도시된 바와 같이, 자기정렬콘택식각(Self Aligned Contact Etch)을 실시하여 콘택홀(28)을 형성한다. 이어서, 기판(21)을 일부 깊이 추가로 식각하여 서브홀(29, Sub Hole)을 형성한다. 서브홀(29)은 기판(21)을 일정 깊이 추가로 식각하여 후속 랜딩 플러그 콘택과의 접촉면적으로 증가시킴으로써 콘택 저항을 감소시키기 위한 것이다. As shown in FIG. 2B, the self-aligned contact etching is performed to form the contact hole 28. Subsequently, the substrate 21 is additionally etched to form a sub hole 29. The sub-holes 29 are intended to reduce contact resistance by further etching the substrate 21 to a certain depth to increase the contact area with subsequent landing plug contacts.

서브홀(29)을 형성하는 과정에서 서브홀(29)의 바닥부에 식각에 의한 손실층(30, Damaged Layer)이 형성된다. 즉, 기판(21)을 식각하는 공정에서 격자 결함 내지는 식각가스 중의 카본(Carbon)이나 불소(F)가 주입(Implantation)되어 손실층(30)이 형성될 수 있다. In the process of forming the sub-holes 29, a damaged layer 30 is formed on the bottom of the sub-holes 29 by etching. That is, in the process of etching the substrate 21, carbon or fluorine (F) in lattice defects or etching gases may be implanted to form the loss layer 30.

도 2c에 도시된 바와 같이, 서브홀(29)의 측벽에 식각배리어막(31)을 형성한다. 식각배리어막(31)은 서브홀(29)을 포함하는 기판(21)에 절연막을 형성하고, 손 실층(30)이 드러나는 타겟으로 전면식각을 실시하여 서브홀(29)의 측벽에 잔류시킴으로써 형성할 수 있다. 특히, 식각배리어막(31)은 서브홀(29)의 측벽 외에 측벽보호막(25) 상에도 형성될 수 있다. As shown in FIG. 2C, an etch barrier layer 31 is formed on the sidewall of the sub-hole 29. The etching barrier layer 31 is formed by forming an insulating film on the substrate 21 including the sub-holes 29, and etching the entire surface with the target on which the loss layer 30 is exposed and remaining on the sidewalls of the sub-holes 29. can do. In particular, the etching barrier layer 31 may be formed on the sidewall protection layer 25 in addition to the sidewalls of the sub holes 29.

식각배리어막(31)은 기판(21)과 식각선택비를 갖는 물질로 형성할 수 있고, 예컨대 산화막 또는 질화막으로 형성할 수 있으며, 10Å∼100Å의 두께로 형성할 수 있다.The etching barrier film 31 may be formed of a material having an etching selectivity with respect to the substrate 21, and may be formed of, for example, an oxide film or a nitride film, and may be formed to have a thickness of 10 μs to 100 μs.

도 2d에 도시된 바와 같이, 식각배리어막(31)을 식각장벽으로 등방성식각을 진행하여 손실층(30)을 제거한다. 등방성식각은 콘택홀(28) 형성 후 실시하는 후처리 식각(Post Etch Treatment)으로 진행할 수 있다. 즉, 화학건식식각(CDE;Chemical Dry Etch)를 이용한 등방성식각으로 진행할 수 있다.As shown in FIG. 2D, the loss layer 30 is removed by isotropic etching the etch barrier layer 31 to the etch barrier. Isotropic etching may be performed by post etching treatment performed after the contact hole 28 is formed. That is, the process may be performed by isotropic etching using chemical dry etching (CDE).

특히, 등방성식각은 서브홀(29)의 측벽식각을 방지하기 위해 기판(21)과 식각배리어막(31)의 선택비가 1∼10:1의 비율을 갖는 조건으로 실시할 수 있다. 이를 위해, 등방성식각은 플루오린을 포함하는 가스와 O2, N2 및 Ar로 이루어진 그룹 중에서 선택된 어느 하나의 혼합가스로 실시할 수 있다. 또한, 플루오린을 포함하는 가스는 불화탄소 또는 불화질소가스일 수 있다. In particular, the isotropic etching may be performed under the condition that the selectivity of the substrate 21 and the etching barrier layer 31 has a ratio of 1 to 10: 1 to prevent sidewall etching of the sub-holes 29. To this end, the isotropic etching may be performed with a gas containing fluorine and any mixed gas selected from the group consisting of O 2 , N 2 and Ar. In addition, the gas containing fluorine may be carbon fluoride or nitrogen fluoride gas.

위와 같이, 손실층(30)을 제거하기 위한 등방성식각시 식각배리어막(31)이 서브홀(29)의 측벽을 보호하고 있기 때문에, 서브홀(29)의 측벽 식각을 방지할 수 있다. 따라서, 측벽 손실없이 손실층(30)만 선택적으로 제거할 수 있다. As described above, since the etch barrier layer 31 protects the sidewall of the subhole 29 during isotropic etching for removing the loss layer 30, the sidewall etching of the subhole 29 may be prevented. Therefore, only the loss layer 30 can be selectively removed without sidewall loss.

식각이 완료된 서브홀(29)을 '서브홀패턴(29A)'이라고 한다. The sub-hole 29 having completed etching is referred to as a 'sub hole pattern 29A'.

도 2e에 도시된 바와 같이, 서브홀패턴(29A) 및 콘택홀(28)을 매립하도록 도전물질을 형성하여 랜딩 플러그 콘택(32, Landing Plug Contact)을 형성할 수 있다. As illustrated in FIG. 2E, a conductive material may be formed to fill the sub hole pattern 29A and the contact hole 28 to form a landing plug contact 32.

식각배리어막(31)이 절연막으로 형성되었기 때문에, 식각배리어막(31)을 제거하지 않고, 랜딩 플러그 콘택(32) 공정을 진행할 수 있다. 랜딩 플러그 콘택(32)은 서브홀패턴(29A) 및 콘택홀(28)을 충분히 매립하도록 도전물질을 형성한 후, 게이트하드마스크(24C)가 드러나는 타겟으로 평탄화하여 형성할 수 있다. 이때, 평탄화는 화학적기계적연마 또는 에치백 공정으로 진행할 수 있다. 또한, 도전물질은 폴리실리콘 또는 금속물질일 수 있다.Since the etching barrier film 31 is formed of an insulating film, the landing plug contact 32 process can be performed without removing the etching barrier film 31. The landing plug contact 32 may be formed by forming a conductive material to sufficiently fill the sub hole pattern 29A and the contact hole 28, and then planarize the target to expose the gate hard mask 24C. In this case, the planarization may be performed by chemical mechanical polishing or etch back process. In addition, the conductive material may be polysilicon or a metallic material.

위와 같이, 서브홀(29)의 측벽에 식각배리어막(31)을 형성한 후 후처리 식각을 진행하여 측벽의 손실없이 바닥면적만 증가한 서브홀패턴(29A)을 형성할 수 있다. 따라서, 누설전류를 방지하고 콘택저항을 감소시킬 수 있다. As described above, after the etching barrier layer 31 is formed on the sidewalls of the sub-holes 29, the post-etching process may be performed to form the sub-hole patterns 29A having the increased bottom area without loss of the sidewalls. Therefore, leakage current can be prevented and contact resistance can be reduced.

한편, 본 발명은 리세스패턴(23)을 갖는 게이트패턴(24)을 도시하였으나, 본 발명은 리세스패턴(23) 외에 평판형, 핀형 또는 새들형 게이트패턴에도 응용이 가능하다. Meanwhile, although the gate pattern 24 having the recess pattern 23 is illustrated in the present invention, the present invention may be applied to a planar, fin or saddle gate pattern in addition to the recess pattern 23.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도,1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 기판 22 : 소자분리막21 substrate 22 device isolation film

23 : 리세스패턴 24 : 게이트패턴23: recess pattern 24: gate pattern

25 : 측벽보호막 26 : 층간절연막25 sidewall protective film 26 interlayer insulating film

27 : 감광막패턴 28 : 콘택홀27: photoresist pattern 28: contact hole

29 : 서브홀 30 : 손실층29: subhole 30: loss layer

31 : 식각배리어막 32 : 랜딩 플러그 콘택31: etching barrier layer 32: landing plug contact

Claims (7)

기판에 패턴을 형성하는 단계;Forming a pattern on the substrate; 상기 패턴 사이를 매립하는 층간절연막을 형성하는 단계;Forming an interlayer insulating film to fill the gaps between the patterns; 상기 층간절연막을 식각하여 상기 패턴 사이에 콘택홀을 형성하는 단계;Etching the interlayer insulating layer to form contact holes between the patterns; 상기 콘택홀 하부의 상기 기판을 식각하여 서브홀을 형성하는 단계;Etching the substrate under the contact hole to form a subhole; 상기 콘택홀 및 서브홀의 측벽에 식각배리어막을 형성하는 단계; 및Forming an etching barrier layer on sidewalls of the contact hole and the subhole; And 상기 식각배리어막을 식각장벽으로 상기 서브홀 형성시 생성된 손실층을 제거하는 단계Removing the loss layer formed when the sub-hole is formed using the etch barrier layer as an etch barrier. 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 식각배리어막을 형성하는 단계는,Forming the etch barrier layer, 상기 서브홀을 포함하는 기판 전면에 절연막을 형성하는 단계; 및Forming an insulating film on an entire surface of the substrate including the sub-holes; And 상기 손실층이 오픈되는 타겟으로 전면식각을 실시하여 상기 절연막을 상기 서브홀의 측벽에 잔류시키는 단계Etching the entire surface with a target on which the loss layer is opened to leave the insulating layer on the sidewall of the sub-hole; 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 식각배리어막은 산화막 또는 질화막인 반도체 소자의 제조방법.The etching barrier film is a semiconductor device manufacturing method of the oxide film or nitride film. 제1항에 있어서,The method of claim 1, 상기 식각배리어막은 10Å∼100Å의 두께인 반도체 소자의 제조방법.The etching barrier film has a thickness of 10 ~ 100 Å semiconductor device manufacturing method. 제1항에 있어서,The method of claim 1, 상기 손실층을 제거하는 단계는,Removing the loss layer, 등방성식각으로 진행하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device proceeding by isotropic etching. 제1항에 있어서,The method of claim 1, 상기 등방성식각은 플루오린을 포함하는 가스와 O2, N2 및 Ar로 이루어진 그룹 중에서 선택된 어느 하나의 혼합가스로 실시하는 반도체 소자의 제조방법.The isotropic etching is a method of manufacturing a semiconductor device performed by a gas containing fluorine and any mixed gas selected from the group consisting of O 2 , N 2 and Ar. 제6항에 있어서,The method of claim 6, 상기 플루오린을 포함하는 가스는 불화탄소 또는 불화질소가스인 반도체 소자의 제조방법.The fluorine-containing gas is a fluorocarbon or nitrogen fluoride gas manufacturing method of a semiconductor device.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8445957B2 (en) 2010-04-09 2013-05-21 Hynix Semiconductor Inc. Semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8445957B2 (en) 2010-04-09 2013-05-21 Hynix Semiconductor Inc. Semiconductor device and method of manufacturing the same

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