KR20080095669A - Method of forming a contact structure - Google Patents

Abstract

A formation method of contact structure is provided to reduce the short failure between a contact and a conductive structure in a self-align contact etch process by laminating a first protective layer pattern and a second protective layer pattern, which has different an etching ratio from the first protective layer pattern, on the conductive structure. A formation method of contact structure includes the step of forming conductive structures including a conductive layer pattern(106) on a substrate and a first protective layer pattern formed on the conductive layer pattern or lateral side thereof; the step of forming an interlayer dielectric layer pattern(104) which fills the gap between the conductive structures; the step of forming a recess part by etching partially the upper side of the first protective layer pattern; the step of forming a second protective layer pattern(120) with a material which has higher etching ratio than the first protective layer pattern; the step of forming a contact plug which is electrically connected with the substrate by passing through the interlayer dielectric layer pattern between the first and second protective layer patterns. The conductive structure is a word line structure or a bit line structure.

Description

Method of forming a contact structure}

1 to 8 are cross-sectional views illustrating a method of forming a contact structure according to an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

100: semiconductor substrate 102: device isolation region

104: first interlayer insulating film 106: conductive film pattern

108: hard mask 110: spacer

112: first protective film pattern 114: conductive structure

116: second interlayer insulating film pattern 118: recessed portion

120: second protective film pattern 122: second photoresist pattern

124: contact hole 126: spare contact plug

128: contact plug

The present invention relates to a method of forming a contact structure, and more particularly, to a method of forming a contact structure in a self-aligned manner.

Recent semiconductor devices require high speed operation while having a high storage capacity in terms of functionality. To this end, the semiconductor devices have been developed with manufacturing techniques in order to improve the degree of integration, response speed and reliability.

As the semiconductor device, a DRAM device having free input and output of information and having a high capacity is widely used. Each memory cell of the DRAM device includes one access transistor and one storage capacitor.

As the degree of integration of the memory cell is increased, the contact margin between the word line structure and the bit line structure is gradually decreasing. To overcome this diminishing contact margin, self-aligned contact manufacturing techniques are used.

The self-aligned contact is a technique of forming a contact hole by forming a bit line structure or a word line structure and then etching the interlayer insulating layer using an etch selectivity between the bit line structure or the word line structure and the interlayer insulating layer. . Thereafter, when the inside of the contact hole is filled with a conductive material, contact plugs are formed, and they are electrically connected to the source / drain of the active region under the interlayer insulating layer.

When the contact plug is formed through the self-aligned etching process, the hard mask pattern included in the bit line structure or the word line structure must remain until the etching process is completed. However, during the etching process, a part of the hard mask pattern may be excessively etched so that the upper part of the bit line or the word line may be exposed. In this case, the bit line or the word line and the contact plug may be shorted.

In addition, since the hard mask pattern is substantially removed, the shape of the bit line structure or the word line structure may be deteriorated, which may cause problems such as difficulty in subsequent processes.

An object of the present invention for solving the above problems is to provide a method for forming a contact structure that can reduce the short (short) defect between the conductive structure and the contact.

A method of forming a contact structure according to an embodiment of the present invention for achieving the above object, the conductive structures including a conductive film pattern and a first protective film pattern provided on the upper surface and side surfaces of the conductive film pattern Form. An interlayer insulating layer pattern filling the space between the conductive structures is formed. An upper portion of the first passivation layer pattern is partially etched to form a recess. The recess portion is buried and a second passivation layer pattern is formed using a material having an etching selectivity higher than that of the first passivation layer pattern with respect to the interlayer insulating layer pattern. Next, a contact plug is formed through the interlayer insulating film pattern between the first and second protective film patterns to be electrically connected to the substrate.

According to embodiments of the present invention, the conductive structure may be a word line structure or a bit line structure.

In example embodiments, the first passivation layer pattern may include a hard mask provided on an upper surface of the conductive layer pattern and a spacer provided on side surfaces of the conductive layer pattern and the hard mask.

In example embodiments, the forming of the conductive structures may include forming a conductive layer on the substrate, forming a hard mask layer on the conductive layer, and patterning the hard mask layer and the conductive layer to form a conductive layer. The method may include forming a pattern and a hard mask and forming spacers on side surfaces of the conductive layer pattern and the hard mask.

In example embodiments, the first passivation layer pattern may be formed of silicon nitride.

In example embodiments, the second passivation layer pattern may be formed of polysilicon, a metal, or a metal silicide.

In example embodiments, the forming of the contact plug may include forming a photoresist pattern exposing the interlayer insulating layer pattern between the conductive structures, and using the photoresist pattern as an etching mask. Etching to form a contact hole for exposing the substrate, depositing a conductive material in the contact hole, forming a preliminary contact plug, and exposing the upper surface of the first passivation layer pattern, And polishing the second passivation layer pattern and the interlayer insulation layer pattern.

According to the present invention as described above, a second protective film pattern formed of a material having an etching selectivity higher than that of the first protective film pattern with respect to the first protective film pattern and the interlayer insulating film pattern is formed on the conductive structure.

Therefore, in the self-aligned contact etching process, short defects between the conductive structure and the contact can be reduced, and thus a shoulder margin between the conductive structure and the contact can be improved.

Hereinafter, a method for forming a contact structure according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and a person of ordinary skill in the art. If the present invention can be implemented in various other forms without departing from the spirit of the present invention. In the accompanying drawings, the dimensions of substrates, layers (films), contact holes, contact plugs, regions, patterns, or structures are shown to be larger than actual for clarity of the invention. In the present invention, each layer (film), region, pattern or structure is referred to as being formed "on", "top" or "bottom" of the substrate, each layer (film), region, pattern or structure. In this case, it is meant that each layer (film), region, pattern or structure is directly formed on or under the substrate, each layer (film), region, pattern or structures, or is a different layer (film), another region, another Patterns or other structures may additionally be formed on the substrate. In addition, where layers (membrane), plugs, patterns or structures are referred to as "spare", "first" and / or "second", it is not intended to limit these members but merely each layer (mem), plug, To distinguish between patterns or structures. Thus, "preliminary", "first" and / or "second" may be used either selectively or interchangeably for each layer (film), plug, pattern or structures.

1 to 8 are cross-sectional views illustrating a method of forming a contact structure according to an embodiment of the present invention. For reference, FIGS. 1 to 8 are cross-sectional views cut in the word line direction, and a semiconductor structure formed before the bit line structure will be omitted and briefly described.

Referring to FIG. 1, a shallow trench isolation (STI) process is performed on a semiconductor substrate 100 to distinguish between the active region 100 and the device isolation region 102.

In detail, a buffer oxide layer (not shown) is formed on the semiconductor substrate 100. The buffer oxide film then serves as a film for relieving stress generated on the silicon nitride film to be formed and the substrate 100. A silicon nitride film (not shown) is formed on the buffer film. A portion of the silicon nitride film is removed to form a silicon nitride film pattern (not shown). Using the silicon nitride film pattern as an etching mask, the buffer oxide film is dry-etched to form a buffer oxide film pattern (not shown). Subsequently, a trench (not shown) is formed by etching the exposed substrate 100 to a predetermined depth using the silicon nitride film pattern as an etching mask. In order to increase the margin of the photolithography process for the active pattern, an anti-reflection layer ARL may be further formed on the nitride layer. Subsequently, a silicon oxide film (not shown) is embedded in the trench and planarized to expose the silicon nitride film pattern. Finally, the silicon nitride layer pattern and the buffer oxide layer pattern are removed by a wet etching process to separate the active region 100 and the device isolation region 102.

Although not shown, a word line structure (not shown) is formed on the active region 100, and then a landing contact plug (not shown) is electrically insulated from the word line structure.

Briefly, a first interlayer insulating film 104 covering the word line structure is deposited. The first interlayer insulating layer 104 between the word line structures is etched to form a first interlayer insulating layer pattern (not shown) including a contact hole (not shown) that exposes a portion of the substrate 100. Thereafter, the contact hole is filled with a conductive material to form a landing contact plug.

Referring to FIG. 2, a conductive film including a conductive film pattern 106 and a first passivation film pattern 112 provided on upper and side surfaces of the conductive film pattern 106 on the first interlayer insulating film 104. Form structures 114. The first passivation layer pattern 112 may include a hard mask 108 provided on an upper surface of the conductive layer pattern 106 and a spacer provided on side surfaces of the conductive layer pattern 106 and the hard mask 108. 110).

A method of forming the conductive structures 114 will be described in detail. A conductive film (not shown) functioning as a bit line is formed on the first interlayer insulating film 104. The conductive layer may be formed of a polysilicon layer doped with a high concentration of impurities by a doping process, for example, an ion implantation process or an in-situ doping process.

A first silicon nitride film (not shown) is formed on the conductive film using low pressure chemical vapor deposition or plasma chemical vapor deposition. The first silicon nitride film is used as a hard mask film in a subsequent conductive film etching process. In addition, when the subsequent processes are performed, the first silicon nitride layer serves to protect the conductive layer so that the conductive layer disposed below is not exposed. Accordingly, the hard mask layer is not limited to silicon nitride, and may be an insulating material having an etching selectivity with silicon oxide used as an interlayer insulating layer.

A first photoresist pattern (not shown) defining a region in which a conductive structure is formed is formed on the hard mask layer. The hard mask layer and the conductive layer are sequentially patterned using the first photoresist pattern as an etching mask. By the above process, a preliminary conductive structure (not shown) in which the conductive film pattern 106 and the hard mask 108 are stacked is formed. Thereafter, the first photoresist pattern may be removed using an ashing and stripping method.

A second silicon nitride film (not shown) having a uniform thickness is formed along the surfaces of the preliminary conductive structure and the substrate. Thereafter, the second silicon nitride film is anisotropically etched so that only the side surface of the preliminary conductive structure remains, so that the spacer 110 is formed.

As a result, the bit line conductive structure 114 including the conductive film pattern 106, the hard mask 108, and the spacer 110 is completed.

Referring to FIG. 3, a second interlayer insulating film (not shown) covering the conductive structure 114 is deposited. The second interlayer insulating layer may be formed of silicon oxide. For example, a boro-phosphor silicate glass (BPSG) oxide, a phosphor silicate glass oxide (PSG) oxide, an undoped silicate glass oxide (USG), a spin on glass oxide (SOG), PE-TEOS (plasma enhanced-tetra ethyl ortho silicate) oxide, HDP-CVD (high density plasma-chemical vapor deposition) oxide, and the like.

The second interlayer insulating layer pattern 116 is formed by planarizing the second interlayer insulating layer so that the top surface of the conductive structure 114 is exposed. The second interlayer insulating layer pattern 116 may be formed by performing a chemical mechanical polishing process or an etch back process.

Referring to FIG. 4, an upper portion of the first passivation layer pattern 112 is partially etched to form a recess 118. As a result, the thickness of the first passivation layer pattern 112 is somewhat lowered.

As described above, according to the embodiment of the present invention, since the first passivation layer pattern 112 is made of silicon nitride, the etching process may be performed by a wet etching process using a phosphoric acid (P ₂ O ₅ ) solution. have.

Referring to FIG. 5, a second passivation layer (not shown) may be formed to fill the recess 118. Thereafter, the second passivation layer is polished until the second interlayer insulating layer pattern 116 is exposed to form the second passivation layer pattern 120. The polishing process may be formed by performing a chemical mechanical polishing process or an etch back process.

The second passivation layer pattern 120 is formed using a material having an etching selectivity higher than that of the first passivation layer pattern 112 with respect to the second interlayer insulating layer pattern 116. The second passivation layer pattern 120 may use polysilicon, a metal, or a metal silicide material. Examples of the metal or metal silicide include titanium nitride, tantalum nitride, tungsten silicide, and the like.

Referring to FIG. 6, a second photoresist pattern 122 exposing the second interlayer insulating layer pattern 116 between the second passivation layer pattern 120 is formed.

Using the photoresist pattern 122 as an etch mask, the second interlayer insulating layer pattern 116 and the first interlayer insulating layer pattern 104 are sequentially etched to expose the contact hole 124. ).

In the etching process, first, the second passivation layer pattern 120 is etched, and the second passivation layer pattern 120 has a very high etching selectivity with respect to the second interlayer insulating layer pattern 116. Therefore, the second passivation layer pattern is hardly etched, and the first passivation layer pattern 112a under the second passivation layer pattern 120 is hardly affected. In particular, even if a photo misalignment is generated to increase the etching area of the second passivation layer pattern 120, the removal of the shoulder portion may be greatly reduced.

In general, since the protective film pattern formed on the conductive structure is made of silicon nitride only, part of the protective film pattern is excessively etched during the self-aligned etching process. Therefore, the upper part of the conductive structure is partially exposed, and a short occurs between the conductive structure and the contact.

However, as described above, in the present invention, a second passivation layer pattern having a high etching selectivity is formed on the first passivation layer pattern. As a result, since the second passivation pattern, which is relatively slower than the first passivation pattern, is etched first, the second passivation pattern is hardly etched. Thus, the self-aligned etching process may be performed so as not to affect the conductive structure.

Referring to FIG. 7, a conductive material is deposited in the contact hole 124 to form a preliminary contact plug 126.

Referring to FIG. 8, the preliminary contact plug 126, the second passivation layer pattern 116, and the second interlayer insulation layer pattern 114 are polished so that the top surface of the first passivation layer pattern 108a is exposed. The polishing process may be performed through a chemical mechanical polishing process or an etch back process.

Thereafter, a process of forming a capacitor including a lower electrode, a dielectric layer, and an upper electrode connected to the contact plug 128 may be further performed.

According to the method of forming a contact structure of the present invention as described above, by stacking the first protective film pattern and the second protective film pattern having different etching ratios on the conductive structure, a short between the conductive structure and the contact during the self-aligned contact etching process ( short) can reduce defects.

As a result, a shoulder margin between the conductive structure and the contact can be improved, thereby improving reliability and yield of the semiconductor device.

As described above, the present invention has been described with reference to the preferred embodiments of the present invention, but a person of ordinary skill in the art does not depart from the spirit and scope of the present invention as set forth in the claims below. It will be understood that various modifications and changes can be made.

Claims (7)

Forming conductive structures on the substrate, the conductive structures including a conductive layer pattern and a first passivation layer pattern provided on upper and side surfaces of the conductive layer pattern; Forming an interlayer insulating layer pattern filling the space between the conductive structures; Partially etching an upper portion of the first passivation layer pattern to form a recess; Filling the recess part and forming a second passivation layer pattern using a material having an etching selectivity higher than that of the first passivation layer pattern with respect to the interlayer insulating layer pattern; And And forming a contact plug penetrating the interlayer insulating film pattern between the first and second passivation layer patterns to electrically connect with the substrate. The method of claim 1, wherein the conductive structure is a word line structure or a bit line structure. The method of claim 1, wherein the first passivation layer pattern comprises a hard mask provided on an upper surface of the conductive layer pattern and a spacer provided on side surfaces of the conductive layer pattern and the hard mask. The method of claim 3, wherein forming the conductive structures comprises: Forming a conductive film on the substrate; Forming a hard mask film on the conductive film; Patterning the hard mask film and the conductive film to form a conductive film pattern and a hard mask; And And forming spacers on side surfaces of the conductive layer pattern and the hard mask. The method of claim 1, wherein the first passivation layer pattern is formed of silicon nitride. The method of claim 1, wherein the second passivation layer pattern is made of polysilicon, a metal, or a metal silicide. The method of claim 1, wherein the forming of the contact plug comprises: Forming a photoresist pattern exposing the interlayer insulating film pattern between the conductive structures; Etching the interlayer insulating layer pattern using the photoresist pattern as an etching mask to form a contact hole exposing the substrate; Depositing a conductive material in the contact hole to form a preliminary contact plug; And And polishing the preliminary contact plug, the second passivation layer pattern, and the interlayer insulating layer pattern to expose the upper surface of the first passivation layer pattern.

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