KR20080062011A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR20080062011A
KR20080062011A KR1020060137258A KR20060137258A KR20080062011A KR 20080062011 A KR20080062011 A KR 20080062011A KR 1020060137258 A KR1020060137258 A KR 1020060137258A KR 20060137258 A KR20060137258 A KR 20060137258A KR 20080062011 A KR20080062011 A KR 20080062011A
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South Korea
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gate
forming
film
interlayer insulating
etching
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KR1020060137258A
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Korean (ko)
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하가영
김태호
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주식회사 하이닉스반도체
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Priority to KR1020060137258A priority Critical patent/KR20080062011A/en
Publication of KR20080062011A publication Critical patent/KR20080062011A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of manufacturing a semiconductor device is provided to secure reliability of a contact hole for a landing contact plug by forming an etch barrier layer using a sputtering method. A gate is formed on a semiconductor substrate(100). A source/drain region is formed in the substrate at the both sides of the gate. An insulating layer for a spacer(600) is formed at the entire surface of the substrate including the gate. An interlayer dielectric(700) is formed on the resultant structure. A contact hole for landing contact plug which defines a landing contact plug forming region is formed by etching the interlayer dielectric. An etch barrier layer(800) surrounding the upper part of the gate is formed. A perfect contact hole for landing contact plug is formed by etching a part of the interlayer dielectric and the insulating layer as the etch barrier layer until the source/drain region is exposed.

Description

반도체 소자의 제조방법{Method of manufacturing semiconductor device}Method of manufacturing semiconductor device

도 1 내지 도 4는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.1 to 4 are cross-sectional views for each process for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100: 반도체기판 200: 소자분리막100: semiconductor substrate 200: device isolation film

300: 게이트 절연막 400: 게이트 도전막300: gate insulating film 400: gate conductive film

500: 게이트 하드마스크막 600: 스페이서용 절연막500: gate hard mask film 600: insulating film for spacer

700: 층간절연막 800: 식각장벽막700: interlayer insulating film 800: etch barrier

G: 게이트 H,H': 랜딩콘택플러그용 콘택홀G: Gate H, H ': Contact hole for landing contact plug

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 콘택홀 형성의 신뢰성을 확보할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can ensure the reliability of contact hole formation.

반도체 소자의 고집적화에 따라 디자인 룰이 감소되면서 상,하부 패턴들간, 특히 소오스 영역과 비트라인간, 드레인 영역과 캐패시터간에 안정적인 전기적 연결이 이루어지지 못하고 있다. As design rules are reduced due to high integration of semiconductor devices, stable electrical connections between upper and lower patterns, particularly between source and bit lines, between drain and capacitors, are not achieved.

이에 따라, 최근의 반도체 제조 공정에서는 자기정렬콘택(self aligned contact : 이하 SAC) 공정을 통해 소오스/드레인영역 상에 랜딩콘택플러그(landing plug)를 형성함으로써, 이러한 랜딩콘택플러그에 의해 상,하부 패턴들간의 안정적인 전기적 연결이 이루어지도록 하고 있다.Accordingly, in a recent semiconductor manufacturing process, a landing contact plug is formed on a source / drain region through a self aligned contact (SAC) process, and thus, the upper and lower patterns are formed by the landing contact plug. To ensure a stable electrical connection between the two.

한편, 종래의 SAC 공정에 따른 랜딩콘택플러그로 인해 하부 패턴과 상부 패턴간의 안정적인 콘택은 확보되지만, 디자인 룰(design rule)이 점점 감소함에 따라 랜딩콘택플러그가 형성되는 콘택홀을 안정적으로 형성하는데 많은 어려움이 따르고 있다.On the other hand, stable contact between the lower pattern and the upper pattern is secured due to the landing contact plug according to the conventional SAC process, but as the design rule is gradually reduced, many contact holes for forming the landing contact plug are stably formed. Difficulties follow.

구체적으로, 랜딩콘택플러그용 콘택홀 형성방법은, 먼저, 게이트와 소오스/드레인영역으로 구성된 트랜지스터 상에 층간절연막을 형성한 후, 상기 소오스/드레인영역이 노출될 때까지 상기 층간절연막을 식각하는 공정으로 이루어지고 있고 있는데, 소자의 고집적화에 따른 리소그라피(lithography)의 한계로 인해 상기 층간절연막 식각 공정시 상기 소오스/드레인영역이 노출되지 못하는 낫-오픈(Not-Open) 현상등이 발생되고 있다.Specifically, in the method of forming a contact hole for a landing contact plug, first, an interlayer insulating film is formed on a transistor including a gate and a source / drain region, and then the interlayer insulating layer is etched until the source / drain region is exposed. Due to the limitation of lithography due to the high integration of devices, a not-open phenomenon in which the source / drain regions are not exposed during the interlayer insulating layer etching process is generated.

또한, 상기 게이트간을 절연시키거나, 게이트와 랜딩콘택플러그간을 절연시키기 위한 목적으로 게이트 전면에 스페이서용 절연막이 형성하게 되면, 콘택홀의 폭은 더욱 더 좁아지게 되면서 안정적인 콘택홀의 형성은 더욱 어려워지게 된다.In addition, when the insulating film for the spacer is formed on the entire surface of the gate for insulating the gates or insulating the gate and the landing contact plug, the width of the contact hole becomes narrower and the formation of a stable contact hole becomes more difficult. do.

본 발명은 랜딩콘택플러그용 콘택홀 형성의 신뢰성을 확보하여 안정적인 콘택홀을 형성할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a stable contact hole by securing the reliability of forming a contact hole for a landing contact plug.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 반도체기판 상에 게이트를 형성하는 단계; 상기 게이트 양측의 기판 내에 소오스/드레인영역을 형성하는 단계; 상기 게이트를 포함한 기판 전면 상에 스페이서용 절연막을 형성하는 단계; 상기 스페이서용 절연막이 형성된 기판 결과물 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 식각하여 랜딩콘택플러그 형성 영역을 한정하는 랜딩콘택플러그용 콘택홀을 형성하는 단계; 상기 게이트의 상단부를 감싸는 식각장벽막을 형성하는 단계; 및 상기 식각장벽막을 이용해서 소오스/드레인영역이 노출될 때까지 상기 층간절연막 식각시 식각되지 않은 층간절연막 부분 및 스페이서용 절연막 부분을 식각하여 완전한 랜딩콘택플러그용 콘택홀을 형성하는 단계;를 포함하는 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention, forming a gate on a semiconductor substrate; Forming a source / drain region in the substrate on both sides of the gate; Forming an insulating film for a spacer on an entire surface of the substrate including the gate; Forming an interlayer insulating film on a substrate product on which the insulating film for spacers is formed; Etching the interlayer insulating layer to form a contact hole for a landing contact plug defining a landing contact plug forming region; Forming an etch barrier layer surrounding an upper end portion of the gate; And forming a contact hole for a complete landing contact plug by etching an unetched interlayer insulating portion and an insulating portion for spacers during the interlayer insulating layer etching until the source / drain regions are exposed using the etching barrier layer. Provided are a method of manufacturing a semiconductor device.

여기서, 상기 식각장벽막은 스퍼터링 방식으로 형성하는 것을 포함한다.Here, the etching barrier film may be formed by a sputtering method.

상기 식각장벽막은 질화막과 산화막 및 고온의 Al막 중에서 어느 하나의 막으로 형성하는 것을 포함한다.The etching barrier film may be formed of any one of a nitride film, an oxide film, and a high temperature Al film.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 설명하면, 본 발명은 SAC 공정 과정에서 랜딩콘택플러그용 콘택홀 형성방법에 관한 것으로, 반도체기판 상에 형성된 층간절연막을 식각하여 랜딩콘택플러그용 콘택홀을 형성한 후, 스퍼터링 방식을 이용해서 게이트의 상단부를 감싸는 식각장벽막을 형성하고 나서, 상기 식각장벽막을 이용하여 상기 층간절연막 식각시 식각되지 않은 층간절연막 부분을 식각하여 소오스/드레인영역을 노출시키는 완전한 랜딩콘택플러그용 콘택홀을 형성하는 것을 특징으로 한다.First, the technical principle of the present invention, the present invention relates to a method for forming a contact hole for landing contact plug in the SAC process, after forming the contact hole for landing contact plug by etching the interlayer insulating film formed on the semiconductor substrate Using a sputtering method to form an etch barrier that covers the upper end of the gate, and then use the etch barrier to etch the unetched interlayer insulating portion during the etching of the interlayer insulating film to expose source / drain regions. Forming a contact hole is characterized in.

이렇게 하면, 상기 게이트 상단부에 스퍼터링 방식으로 형성된 식각장벽막으로 인해 식각되지 않은 층간절연막 부분을 완전히 식각할 수 있어 낫-오픈(Not-Open) 현상을 방지할 수 있으며, 상기 식각장벽막이 게이트 상단부에만 형성함에 따라 식각장벽막을 이용한 층간절연막 식각시 게이트 양측의 손상없이 콘택홀을 형성할 수 있으므로, 결과적으로, 랜딩콘택플러그용 콘택홀 형성의 신뢰성을 확보할 수 있으며, 안정적인 콘택홀을 형성할 수 있다.In this case, the portion of the interlayer insulating layer that is not etched can be completely etched due to the etching barrier film formed on the upper end of the gate by the sputtering method, thereby preventing the not-open phenomenon. As a result, contact holes can be formed without damaging both sides of the gate when the interlayer insulating layer is etched by using the etch barrier film. As a result, it is possible to secure the reliability of forming the contact hole for the landing contact plug and to form a stable contact hole. .

자세하게는, 도 1 내지 도 4를 참조하여 본 발명의 실시예에 따른 SAC 공정을 포함한 반도체 소자의 제조방법을 설명하도록 한다.In detail, a method of manufacturing a semiconductor device including a SAC process according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4.

도 1을 참조하면, 활성영역을 한정하는 소자분리막(200)이 구비된 반도체기판(100) 상에 게이트 물질로 게이트 절연막(300)과 게이트 도전막(400) 및 게이트 하드마스크막(500)을 형성한 후, 이들을 식각하여 상기 기판(100) 상에 게이트(G)를 형성한다.Referring to FIG. 1, a gate insulating layer 300, a gate conductive layer 400, and a gate hard mask layer 500 may be formed of a gate material on a semiconductor substrate 100 having an isolation layer 200 defining an active region. After the formation, the gates G are formed on the substrate 100 by etching them.

한편, 도시하지는 않았으나, 상기 반도체기판(100) 상에 게이트 물질을 형성하기 전에, 상기 기판 부분을 식각하여 게이트 형성 영역을 한정하는 홈을 형성할 수 있으며, 상기 홈은 유 타입(U type)타입 또는 벌브 타입(Bulb type)의 홈으로 형성할 수 있다.Although not shown, before forming a gate material on the semiconductor substrate 100, the groove may be formed by etching the substrate portion to define a gate formation region, and the groove may be a U type type. Or it may be formed as a bulb type (Bulb type) groove.

그런다음, 상기 게이트가 형성된 기판 결과물에 대해 불순물 이온주입을 수행하여 상기 게이트(G) 양측의 기판 내에 소오스/드레인영역(S/D)을 형성한 후, 상기 게이트(G)를 포함한 기판 전면 상에 균일한 두께로 스페이서용 절연막(600)을 형성한다.Then, impurity ion implantation is performed on the substrate product on which the gate is formed to form a source / drain region S / D in the substrate on both sides of the gate G, and then on the entire surface of the substrate including the gate G. The spacer insulating film 600 is formed in a uniform thickness.

도 2를 참조하면, 상기 스페이서용 절연막(600)이 형성된 기판 결과물 상에 층간절연막(700)을 증착한 후, 상기 층간절연막(700)을 화학기계적연마(Chemical Mechanical Polishing, CMP)하여 평탄화시킨다.Referring to FIG. 2, after the interlayer insulating film 700 is deposited on the substrate product on which the spacer insulating film 600 is formed, the interlayer insulating film 700 is flattened by chemical mechanical polishing (CMP).

그런다음, 상기 층간절연막(700) 상에 랜딩콘택플러그용 콘택홀 예정 영역을 노출시키는 감광막패턴(PR)을 형성한다.Next, a photoresist pattern PR is formed on the interlayer insulating layer 700 to expose a predetermined contact hole contact area for a landing contact plug.

도 3을 참조하면, 상기 감광막패턴(PR)을 마스크로 이용해서 상기 층간절연막(700)을 식각하여 상기 게이트의 상부막, 즉, 게이트 하드마스크막(500)을 노출시킴과 아울러 랜딩콘택플러그 형성 영역을 한정하는 랜딩콘택플러그용 콘택홀(H)을 형성한다.Referring to FIG. 3, the interlayer insulating layer 700 is etched using the photoresist pattern PR as a mask to expose the upper layer of the gate, that is, the gate hard mask layer 500, and to form a landing contact plug. A contact hole H for a landing contact plug defining an area is formed.

이때, 상기 층간절연막 식각시 상기 소오스/드레인영역이 노출되도록 진행되어야 하나, 소자의 고집적에 따른 리소그라피의 한계로 인해 상기 층간절연막(700) 및 스페이서용 절연막(600)이 완전히 식각되지 않게 되면서 안정적인 랜딩콘택플러그용 콘택홀이 형성되지 않는다.At this time, the source / drain region should be exposed when the interlayer insulating layer is etched. However, due to the limitation of lithography due to the high integration of the device, the interlayer insulating layer 700 and the insulating layer 600 for the spacer are not etched completely. The contact plug contact hole is not formed.

즉, 소자의 고집적에 따라 게이트의 높이는 증가되고, 게이트간의 간격은 좁아지게 되면서, 그에 대응하여 콘택홀의 종횡비(aspect)는 증가함에 따라 현재의 리소그라피 공정으로는 층간절연막을 완전히 식각하지 못하고 있다.That is, as the height of the device increases, the height of the gate increases, and the gap between the gates decreases. Accordingly, as the aspect ratio of the contact hole increases, the interlayer insulating film cannot be completely etched by the current lithography process.

도 4를 참조하면, 상기 층간절연막(700) 식각시 노출된 상기 게이트 상에 게이트의 상단부를 감싸는 식각장벽막(800)을 형성한다.Referring to FIG. 4, an etch barrier layer 800 is formed on the gate exposed when the interlayer insulating layer 700 is etched.

이때, 상기 식각장벽막(800)은 스퍼터링(sputtering) 방식을 이용해서 질화막과 산화막 및 고온의 Al막 중에서 어느 하나의 막으로 형성한다.In this case, the etching barrier film 800 is formed of any one of a nitride film, an oxide film, and a high temperature Al film by using a sputtering method.

여기서, 상기 식각장벽막(800)은 스텝 커버리지(step coverage) 특성이 나쁜 스퍼터링 방식으로 진행함에 따라 게이트(G)의 전면에 형성되지 않고, 게이트의 상단부를 감싸는 형태로 형성하게 된다.In this case, the etch barrier film 800 is formed on the front surface of the gate G as the sputtering method having poor step coverage characteristics, and is formed to surround the upper end of the gate.

그런다음, 상기 식각장벽막(800)을 이용해서 상기 소오스/드레인(S/D) 영역이 노출될 때까지 상기 층간절연막(700) 식각시 식각되지 않은 층간절연막(700) 및 스페이서용 절연막(600)을 식각하여 완전한 랜딩콘택플러그용 콘택홀(H')을 형성한다.Thereafter, the etch barrier layer 800 may not be etched when the interlayer insulating layer 700 is etched until the source / drain (S / D) region is exposed, and the insulating layer 600 for the spacer 600 is not etched. ) To form a complete landing contact plug contact hole (H ').

이처럼, 상기 게이트 상단부를 감싸는 식각장벽막으로 인해 상기 소오스/드레인영역이 노출되도록 층간절연막을 완전히 제거할 수 있게 되어 층간절연막이 제거되지 않은 현상, 즉, 층간절연막 낫-오픈(Not-Open) 현상을 방지할 수 있다.As such, the etch barrier layer surrounding the upper end of the gate enables the interlayer insulating layer to be completely removed so that the source / drain region is exposed, so that the interlayer insulating layer is not removed, that is, the not-open phenomenon. Can be prevented.

또한, 본 발명은 스텝 커버리지 특성이 나쁜 스퍼터링 방식으로 상기 식각장벽막을 형성함에 따라, 식각장벽막을 이용한 층간절연막 식각시 게이트의 상단부를 감싸는 형태로 형성하게 되면서 게이트 양측에 어택(attack) 없이 층간절연막을 식각할 수 있다.In addition, according to the present invention, as the etch barrier film is formed by a sputtering method having poor step coverage characteristics, the etch barrier film is formed so as to surround the upper end of the gate when the interlayer insulating film is etched using the etch barrier film. It can be etched.

결과적으로, 본 발명은 스퍼터링 방식으로 형성된 식각장벽막으로 인해 랜딩콘택플러그용 콘택홀 형성의 신뢰성을 확보할 수 있으며, 안정적인 콘택홀을 형성 할 수 있다.As a result, the present invention can ensure the reliability of forming the contact hole for the landing contact plug due to the etching barrier film formed by the sputtering method, it is possible to form a stable contact hole.

이후, 도시하지는 않았으나, 상기 감광막패턴을 제거한 후, 에치백(etch back)으로 식각장벽막을 제거하고 나서, 상기 콘택홀 내에 SAC 공정에 따른 랜딩콘택플러그를 형성한다.Subsequently, although not shown, after removing the photoresist pattern, the etching barrier layer is removed by an etch back, and then a landing contact plug according to the SAC process is formed in the contact hole.

이어서, 공지된 일련의 후속 공정을 차례로 진행하여 본 발명의 실시예에 따른 반도체 소자를 제조한다.Subsequently, a series of well-known subsequent steps are carried out in order to manufacture a semiconductor device according to an embodiment of the present invention.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은, 랜딩콘택플러그용 콘택홀 형성을 위한 층간절연막 식각시, 식각되지 않은 층간절연막 부분을 제거하기 위해 게이트 상단부에 스퍼터링 방식으로 식각장벽막을 형성함으로써, 이를 통해, 층간절연막을 완전히 식각할 수 있게 된다.As described above, the present invention, during the etching of the interlayer insulating film for forming the contact hole for the landing contact plug, by forming an etching barrier film on the upper end of the gate by the sputtering method to remove the unetched interlayer insulating film portion, thereby, the interlayer insulating film Can be completely etched.

또한, 본 발명은 상기 식각장벽막이 게이트 상단부에만 형성함에 따라 식각장벽막을 이용한 층간절연막 식각시 게이트 양측의 손상없이 콘택홀을 형성할 수 있다.In addition, according to the present invention, since the etch barrier layer is formed only at the upper end portion of the gate, contact holes may be formed without damaging both sides of the gate when the interlayer insulating layer is etched using the etch barrier layer.

결과적으로, 본 발명은 스퍼터링 방식으로 형성된 식각장벽막으로 인해 랜딩콘택플러그용 콘택홀 형성의 신뢰성을 확보할 수 있으며, 안정적인 콘택홀을 형성 할 수 있다.As a result, the present invention can ensure the reliability of forming the contact hole for the landing contact plug due to the etching barrier film formed by the sputtering method, it is possible to form a stable contact hole.

Claims (3)

반도체기판 상에 게이트를 형성하는 단계;Forming a gate on the semiconductor substrate; 상기 게이트 양측의 기판 내에 소오스/드레인영역을 형성하는 단계;Forming a source / drain region in the substrate on both sides of the gate; 상기 게이트를 포함한 기판 전면 상에 스페이서용 절연막을 형성하는 단계;Forming an insulating film for a spacer on an entire surface of the substrate including the gate; 상기 스페이서용 절연막이 형성된 기판 결과물 상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on a substrate product on which the insulating film for spacers is formed; 상기 층간절연막을 식각하여 랜딩콘택플러그 형성 영역을 한정하는 랜딩콘택플러그용 콘택홀을 형성하는 단계;Etching the interlayer insulating layer to form a contact hole for a landing contact plug defining a landing contact plug forming region; 상기 게이트의 상단부를 감싸는 식각장벽막을 형성하는 단계; 및Forming an etch barrier layer surrounding an upper end portion of the gate; And 상기 식각장벽막을 이용해서 소오스/드레인영역이 노출될 때까지 상기 층간절연막 식각시 식각되지 않은 층간절연막 부분 및 스페이서용 절연막 부분을 식각하여 완전한 랜딩콘택플러그용 콘택홀을 형성하는 단계;Forming a contact hole for a complete landing contact plug by etching an unetched interlayer insulating portion and an insulating portion for spacers during the interlayer insulating layer etching until the source / drain regions are exposed using the etching barrier layer; 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 식각장벽막은 스퍼터링 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The etching barrier film is a method of manufacturing a semiconductor device, characterized in that formed by the sputtering method. 제 1 항에 있어서,The method of claim 1, 상기 식각장벽막은 질화막과 산화막 및 고온의 Al막 중에서 어느 하나의 막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The etching barrier film is a semiconductor device manufacturing method, characterized in that formed of any one of a nitride film, an oxide film and a high temperature Al film.
KR1020060137258A 2006-12-28 2006-12-28 Method of manufacturing semiconductor device KR20080062011A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109427583A (en) * 2017-08-24 2019-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109427583A (en) * 2017-08-24 2019-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
CN109427583B (en) * 2017-08-24 2021-07-13 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same

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