KR20080062026A - Method for fabricating semiconductor device for prevention of contact spike - Google Patents

Method for fabricating semiconductor device for prevention of contact spike Download PDF

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KR20080062026A
KR20080062026A KR1020060137284A KR20060137284A KR20080062026A KR 20080062026 A KR20080062026 A KR 20080062026A KR 1020060137284 A KR1020060137284 A KR 1020060137284A KR 20060137284 A KR20060137284 A KR 20060137284A KR 20080062026 A KR20080062026 A KR 20080062026A
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layer
gate
forming
film
semiconductor substrate
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KR1020060137284A
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Korean (ko)
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장승순
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동부일렉트로닉스 주식회사
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Priority to KR1020060137284A priority Critical patent/KR20080062026A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of manufacturing a semiconductor device for preventing a contact spike is provided to prevent a contact spike effect by using a nitride layer as a capping layer on an isolation layer. An isolation layer(32), a gate oxide layer(33), and a gate(34) are formed on a semiconductor substrate(31). A nitride layer is deposited on the semiconductor substrate. A spacer(35a) is formed on a sidewall of the gate by etching the nitride layer. A capping layer(35b) is formed at an upper part of the isolation layer. An ion implantation process is performed to form source/drain. A silicide(36) is formed on the source/drain and the gate. A liner nitride layer(37) and an interlayer dielectric(38) are deposited on the semiconductor substrate. A contact hole(39) for exposing the silicide is formed by etching selectively the liner nitride layer and the interlayer dielectric.

Description

컨택 스파이크를 방지하기 위한 반도체 소자의 제조 방법{Method for Fabricating Semiconductor Device for Prevention of Contact Spike}Method for fabricating a semiconductor device to prevent contact spikes {Method for Fabricating Semiconductor Device for Prevention of Contact Spike}

도 1a 내지 도 1d는 종래기술에 따른 반도체 소자의 제조 방법 및 컨택 스파이크의 발생을 보여주는 단면도.1A to 1D are cross-sectional views showing a semiconductor device manufacturing method and generation of contact spikes according to the prior art;

도 2는 컨택 스파이크의 사진 예시도.2 is a photographic illustration of contact spikes.

도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 보여주는 단면도.3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<도면에 사용된 참조 번호의 설명><Description of Reference Number Used in Drawing>

31: 반도체 기판 32: 소자 분리막31: semiconductor substrate 32: device isolation film

33: 게이트 산화막 34: 게이트33: gate oxide film 34: gate

35: 질화막 35a: 측벽 스페이서35 nitride film 35a sidewall spacer

35b: 캡핑막 36: 실리사이드35b: capping film 36: silicide

37: 라이너 절연막 38: 층간 절연막37: liner insulating film 38: interlayer insulating film

39: 컨택 홀 41: 포토레지스트 패턴39: contact hole 41: photoresist pattern

본 발명은 반도체 소자의 제조 기술에 관한 것으로서, 좀더 구체적으로는 컨택 식각 공정에서 공정 마진의 부족으로 인하여 발생하는 컨택 스파이크 현상을 방지할 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing a contact spike phenomenon caused by a lack of process margin in a contact etching process.

반도체 소자의 집적도가 증가하고 설계 규칙(design rule)이 점점 미세해짐에 따라 사진 식각 공정의 마진(margin)도 갈수록 감소하고 있다. 반도체 소자의 제조 공정에서 공정 마진의 부족은 각종 문제들을 유발하고 있는데, 컨택 식각(contact etch) 공정을 진행할 때 컨택이 소자 분리막 안으로 파고드는 컨택 스파이크(contact spike) 현상은 그 중의 하나이다.As the degree of integration of semiconductor devices increases and the design rules become finer, the margins of the photolithography process decrease. The lack of process margins in the manufacturing process of semiconductor devices causes various problems, such as the contact spike phenomenon in which contacts penetrate into the device isolation layer during the contact etch process.

도 1a 내지 도 1d는 종래기술에 따른 반도체 소자의 제조 방법 및 컨택 스파이크의 발생을 보여주는 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device and a generation of contact spikes according to the prior art.

도 1a를 참조하면, 반도체 기판(11)에 소자 분리막(12)을 형성한 후, 게이트 산화막(13)과 게이트(14)를 형성한다. 이어서, 측벽 스페이서(side spacer)로 사용할 질화막(15)을 반도체 기판(11) 전면에 증착한다.Referring to FIG. 1A, after the device isolation layer 12 is formed on the semiconductor substrate 11, the gate oxide layer 13 and the gate 14 are formed. Subsequently, a nitride film 15 to be used as a side spacer is deposited on the entire surface of the semiconductor substrate 11.

다음으로, 도 1b에 도시된 바와 같이, 질화막(15)을 전면 식각하여 게이트(14) 측벽에 스페이서(15a)를 형성한다.Next, as illustrated in FIG. 1B, the nitride layer 15 is etched to form a spacer 15a on the sidewall of the gate 14.

이어서, 도 1c에 도시된 바와 같이, 소정의 이온주입 공정 후에 게이트 산화막(13)을 식각하고 실리사이드(16, silicide)를 형성한다.Subsequently, as shown in FIG. 1C, the gate oxide layer 13 is etched after forming a predetermined ion implantation process to form silicide 16.

그런 후, 도 1d에 도시된 바와 같이, 라이너(liner) 절연막(17)과 층간 절연막(18)을 차례로 증착하고 선택적으로 식각하여 컨택 홀(19, contact hole)을 형성한다. 이때, 공정 마진이 부족하여 컨택 홀(19)이 소자 분리막(12) 쪽으로 겹치게 되면 컨택 스파이크(20)가 생기게 된다.Thereafter, as shown in FIG. 1D, a liner insulating film 17 and an interlayer insulating film 18 are sequentially deposited and selectively etched to form a contact hole 19. In this case, if the contact hole 19 overlaps the device isolation layer 12 due to a lack of process margin, the contact spike 20 may be generated.

도 2는 컨택 스파이크의 사진 예시도이다. 도 1d와 도 2에 도시된 바와 같이, 컨택 스파이크(20)가 발생하면 누설전류 등의 전기적 특성이 나빠지고 반도체 제품의 성능, 신뢰도, 수율이 저하된다. 이러한 문제는 특히 0.25㎛ 제품에서 많이 발생하고 있다.2 is a photographic illustration of a contact spike. As illustrated in FIGS. 1D and 2, when the contact spike 20 is generated, electrical characteristics such as leakage current are deteriorated, and performance, reliability, and yield of semiconductor products are deteriorated. This problem is particularly common in 0.25 μm products.

따라서 본 발명의 목적은 반도체 소자의 컨택 식각 공정에서 공정 마진의 부족으로 인하여 발생하는 컨택 스파이크 현상을 방지하기 위한 것이다.Accordingly, an object of the present invention is to prevent the contact spike phenomenon caused by the lack of process margin in the contact etching process of the semiconductor device.

본 발명의 다른 목적은 반도체 소자의 전기적 특성, 성능, 신뢰도, 수율을 향상시키기 위한 것이다.Another object of the present invention is to improve electrical characteristics, performance, reliability, and yield of semiconductor devices.

이러한 목적들을 달성하기 위하여, 본 발명은 다음과 같은 구성의 반도체 소자 제조 방법을 제공한다.In order to achieve these objects, the present invention provides a method of manufacturing a semiconductor device having the following configuration.

본 발명에 따른 컨택 스파이크를 방지하기 위한 반도체 소자의 제조 방법은, 반도체 기판에 소자 분리막을 형성한 후 게이트 산화막과 게이트를 형성하는 단계와, 상기 반도체 기판의 전면에 질화막을 증착하는 단계와, 상기 질화막을 식각하여 상기 게이트의 측벽에 스페이서를 형성하고 상기 소자 분리막의 위쪽에 캡핑막을 형성하는 단계와, 소스/드레인을 형성하기 위한 이온주입 공정을 진행한 후 상기 게이트 산화막을 식각하고 상기 소스/드레인과 상기 게이트의 표면에 각각 실리사이드를 형성하는 단계와, 상기 반도체 기판의 전면에 라이너 절연막과 층간 절연 막을 차례로 증착하고 선택적으로 식각하여 상기 실리사이드를 노출시키는 컨택 홀을 형성하는 단계를 포함하여 구성된다.A method of manufacturing a semiconductor device for preventing contact spikes according to the present invention includes forming a gate oxide film and a gate after forming a device isolation film on a semiconductor substrate, depositing a nitride film on the entire surface of the semiconductor substrate, and Etching the nitride layer to form a spacer on the sidewall of the gate, forming a capping layer on the device isolation layer, and performing an ion implantation process to form a source / drain, and then etching the gate oxide layer and forming the source / drain And forming silicide on the surface of the gate, and depositing a liner insulating film and an interlayer insulating film on the front surface of the semiconductor substrate and selectively etching to form a contact hole exposing the silicide.

상기 캡핑막의 형성 단계는 상기 소자 분리막 위쪽의 질화막은 가리고 나머지 질화막은 노출시키도록 상기 증착된 질화막 위에 포토레지스트 패턴을 형성하는 단계를 포함할 수 있다.The forming of the capping layer may include forming a photoresist pattern on the deposited nitride layer to cover the nitride layer over the device isolation layer and expose the remaining nitride layer.

실시예Example

이하, 첨부 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하고자 한다. 그러나 실시예를 설명함에 있어서 본 발명이 속하는 기술 분야에 익히 알려져 있고 본 발명과 직접적으로 관련이 없는 기술 내용에 대해서는 가급적 설명을 생략한다. 이는 불필요한 설명을 생략함으로써 본 발명의 핵심을 흐리지 않고 더욱 명확히 전달하기 위함이다. 도면을 통틀어 동일하거나 대응하는 구성요소에는 동일한 참조번호를 사용한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention. However, in describing the embodiments, descriptions of technical contents that are well known in the art to which the present invention pertains and are not directly related to the present invention are omitted. This is to more clearly communicate without obscure the core of the present invention by omitting unnecessary description. The same reference numerals are used for the same or corresponding components throughout the drawings.

도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 보여주는 단면도이다.3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a를 참조하면, 반도체 기판(31)에 소자 분리막(32)을 형성한 후, 게이트 산화막(33)과 게이트(34)를 형성한다. 이어서, 측벽 스페이서로 사용할 질화막(35)을 반도체 기판(31) 전면에 증착한다.Referring to FIG. 3A, after the device isolation layer 32 is formed on the semiconductor substrate 31, the gate oxide layer 33 and the gate 34 are formed. Subsequently, a nitride film 35 to be used as the sidewall spacer is deposited on the entire surface of the semiconductor substrate 31.

다음으로, 도 3b에 도시된 바와 같이, 질화막(35) 위에 포토레지스트를 도포하고 패터닝하여 포토레지스트 패턴(41, photoresist pattern)을 형성한다. 포토레지스트 패턴(41)은 소자 분리막(32) 위쪽의 질화막(35)은 가리고 나머지 질화 막(35)은 노출시키도록 형성된다.Next, as shown in FIG. 3B, a photoresist is applied and patterned on the nitride film 35 to form a photoresist pattern 41. The photoresist pattern 41 is formed to cover the nitride film 35 over the device isolation layer 32 and expose the remaining nitride film 35.

이어서, 도 3c에 도시된 바와 같이, 질화막(35)을 전면 식각하여 게이트(34) 측벽에 스페이서(35a)를 형성한다. 질화막(35)을 전면 식각할 때 소자 분리막(32) 위쪽의 질화막(35b)은 포토레지스트 패턴(41)에 의해 보호되므로 식각되지 않고 남는다. 본 명세서에서는 이를 캡핑막(35b, capping layer)이라 칭한다. 질화막 전면 식각 후 포토레지스트 패턴(41)은 제거한다.Subsequently, as illustrated in FIG. 3C, the nitride layer 35 is etched entirely to form the spacer 35a on the sidewall of the gate 34. When the entire surface of the nitride film 35 is etched, the nitride film 35b on the device isolation layer 32 is protected by the photoresist pattern 41 and thus remains unetched. In this specification, this is referred to as a capping layer 35b. After etching the entire surface of the nitride film, the photoresist pattern 41 is removed.

그 다음, 도 3d에 도시된 바와 같이, 소스/드레인(도시 생략)을 형성하기 위한 소정의 이온주입 공정 후에 게이트 산화막(33)을 식각하고 소스/드레인과 게이트(34)의 표면에 각각 실리사이드(36)를 형성한다.Next, as shown in FIG. 3D, the gate oxide film 33 is etched after a predetermined ion implantation process for forming a source / drain (not shown), and silicides are formed on the surfaces of the source / drain and the gate 34, respectively. Form 36).

이어서, 도 3e에 도시된 바와 같이, 반도체 기판(31)의 전면에 라이너 절연막(37)과 층간 절연막(38)을 차례로 증착하고 선택적으로 식각하여 컨택 홀(39)을 형성한다. 컨택 홀(39)은 소스/드레인과 게이트(34)에 각각 형성된 실리사이드(36)를 노출시킨다. 컨택 홀(39)을 형성하기 위한 식각 공정에서 공정 마진이 부족하여 컨택 홀(39)이 소자 분리막(32) 쪽으로 치우치더라도, 소자 분리막(32)에는 캡핑막(35b)이 형성되어 있으므로 컨택 스파이크의 발생을 막아준다.Next, as shown in FIG. 3E, the liner insulating layer 37 and the interlayer insulating layer 38 are sequentially deposited on the front surface of the semiconductor substrate 31 and selectively etched to form a contact hole 39. The contact hole 39 exposes the silicide 36 formed in the source / drain and the gate 34, respectively. Even when the contact hole 39 is biased toward the device isolation layer 32 due to a lack of process margin in the etching process for forming the contact hole 39, the device isolation layer 32 has a capping layer 35b formed therein, thus contact spikes. Prevents the occurrence of

지금까지 실시예를 통하여 본 발명에 따른 컨택 스파이크를 방지하기 위한 반도체 소자의 제조 방법에 대하여 설명하였다. 본 명세서와 도면에는 본 발명의 바람직한 실시예에 대하여 개시하였으며, 비록 특정 용어들이 사용되었으나, 이는 단지 본 발명의 기술 내용을 쉽게 설명하고 발명의 이해를 돕기 위한 일반적인 의미에서 사용된 것이지, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개 시된 실시예 외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 자명한 것이다.So far, the method of manufacturing the semiconductor device for preventing the contact spike according to the present invention has been described through the examples. In the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms have been used, these are merely used in a general sense to easily explain the technical contents of the present invention and to help the understanding of the present invention. It is not intended to limit the scope. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be implemented in addition to the embodiments disclosed herein.

이상 설명한 바와 같이, 본 발명은 게이트의 측벽 스페이서로 사용하는 질화막을 소자 분리막 위에 캡핑막으로 사용함으로써 컨택 식각 공정에서 공정 마진이 부족하여 컨택과 소자 분리막이 겹치더라도 컨택 스파이크 현상을 방지할 수 있다. 따라서 본 발명은 반도체 소자의 전기적 특성, 성능, 신뢰도, 수율을 향상시킬 수 있다.As described above, the present invention can prevent the contact spike phenomenon even when the contact and the device isolation layer overlap due to insufficient process margin in the contact etching process by using the nitride film used as the sidewall spacer of the gate as the capping layer on the device isolation layer. Therefore, the present invention can improve electrical characteristics, performance, reliability, and yield of semiconductor devices.

Claims (2)

반도체 기판에 소자 분리막을 형성한 후 게이트 산화막과 게이트를 형성하는 단계;Forming a gate oxide film and a gate after forming the device isolation film on the semiconductor substrate; 상기 반도체 기판의 전면에 질화막을 증착하는 단계;Depositing a nitride film on the entire surface of the semiconductor substrate; 상기 질화막을 식각하여 상기 게이트의 측벽에 스페이서를 형성하고 상기 소자 분리막의 위쪽에 캡핑막을 형성하는 단계;Etching the nitride layer to form a spacer on sidewalls of the gate and forming a capping layer on the device isolation layer; 소스/드레인을 형성하기 위한 이온주입 공정을 진행한 후 상기 게이트 산화막을 식각하고 상기 소스/드레인과 상기 게이트의 표면에 각각 실리사이드를 형성하는 단계; 및Etching the gate oxide layer after performing an ion implantation process for forming a source / drain and forming silicide on surfaces of the source / drain and the gate, respectively; And 상기 반도체 기판의 전면에 라이너 절연막과 층간 절연막을 차례로 증착하고 선택적으로 식각하여 상기 실리사이드를 노출시키는 컨택 홀을 형성하는 단계;Depositing a liner insulating film and an interlayer insulating film on the entire surface of the semiconductor substrate in order and selectively etching to form a contact hole exposing the silicide; 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 캡핑막의 형성 단계는 상기 소자 분리막 위쪽의 질화막은 가리고 나머지 질화막은 노출시키도록 상기 증착된 질화막 위에 포토레지스트 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.The forming of the capping film may include forming a photoresist pattern on the deposited nitride film to cover the nitride film over the device isolation layer and expose the remaining nitride film.
KR1020060137284A 2006-12-29 2006-12-29 Method for fabricating semiconductor device for prevention of contact spike KR20080062026A (en)

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