CN105720039B - Interconnect structure and method of forming the same - Google Patents
Interconnect structure and method of forming the same Download PDFInfo
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- CN105720039B CN105720039B CN201410734536.6A CN201410734536A CN105720039B CN 105720039 B CN105720039 B CN 105720039B CN 201410734536 A CN201410734536 A CN 201410734536A CN 105720039 B CN105720039 B CN 105720039B
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Abstract
The invention provides an interconnection structure and a forming method thereof, wherein the forming method of the interconnection structure comprises the following steps: forming a through hole and a notch positioned in the side wall of the opening of the through hole in a first dielectric layer on a substrate; forming a conductive plug in the through hole and the notch, the conductive plug having a main body in the through hole and a protrusion in the notch; forming a second dielectric layer on the first dielectric layer and the conductive plug; forming a groove in the second dielectric layer, wherein the groove at least can expose the bulge of the conductive plug; and filling a metal material in the groove to form a metal lead. When the main body of the conductive plug and the metal lead are deformed and dislocated and the contact area between the metal lead and the main body is reduced, the protruding part is still covered by the metal lead and is in contact with the metal lead, so that good contact between the conductive plug and the metal lead can be ensured.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an interconnection structure and a forming method thereof.
Background
With the development of semiconductor technology, the integration of semiconductor devices is increasing, and the feature size (CD) of semiconductor devices is becoming smaller and smaller, which puts higher demands on the performance of devices such as transistors.
In the back end of line (BEOL) of semiconductor technology, as the density of semiconductor functional devices (e.g., transistors) is increased, the density of interconnection structures is also increased, the spacing between metal plugs is reduced, and the spacing between metal wires covering the metal plugs is also reduced. In order to reduce the distance between the metal plugs or the distance between the metal leads as much as possible and ensure that no defects such as bridging occur between the metal plugs or between the metal leads, the metal leads are often designed to have irregular shapes when the layout of the metal leads and the metal plugs is designed, and the metal plugs are designed to be close to the edge areas of the metal leads.
Referring initially to fig. 1, a top view of a prior art interconnect structure is shown. In the interconnect structure shown in fig. 1, the first plug 01, the second plug 02, and the third plug 03 are distributed in a delta shape to save space. A dielectric layer 04 is formed on the first plug 01, the second plug 02 and the third plug 03, and a first trench 06 exposing the first plug 01 and a second trench 05 exposing the second plug 02 and the third plug 03 are formed in the dielectric layer 04. The first trench 06 is used to form a first lead to connect the first plug 01, and the second trench 05 is used to form a second lead to connect the second plug 02 and the third plug 03. Wherein the first plug 01 is located at the position of the edge region of the first trench 06, and the first trench 06 forms a trapezoidal region above the first plug 01, so that the spacing between the first plug 01, the second plug 02, and the third plug 03 is smaller with the first lead and the second lead kept at a distance.
However, in actual production, the edges of the trapezoidal regions are easily rounded due to diffraction effects of the exposure process. Referring to fig. 2, an electron micrograph of the interconnect structure shown in fig. 1 is shown. After the exposure etching process, the trapezoidal region of the first trench 06, which is the region in the circle in fig. 2, is deformed compared with the pattern in the design drawing, the edge of the trapezoidal region is rounded, and the area of the trapezoidal region is small, so that part of the first plug 01 is partially covered by the dielectric layer 04, and the contact area between the first plug 01 and the metal lead to be formed in the first trench 06 is small, thereby causing poor contact.
Disclosure of Invention
The invention provides an interconnection structure and a forming method thereof, which are used for improving the contact performance between a conductive plug and a metal lead in the interconnection structure.
In order to solve the above problem, the present invention provides a method for forming an interconnect structure, including:
providing a substrate;
forming a first dielectric layer on the substrate;
forming a through hole and a notch in the side wall at one side of the opening of the through hole in the first medium layer;
forming a conductive plug in the through hole and the notch, the conductive plug having a main body in the through hole and a protrusion in the notch;
forming a second dielectric layer on the first dielectric layer and the conductive plug;
forming a groove in the second dielectric layer, wherein the groove at least can expose the bulge of the conductive plug;
and filling a metal material in the groove to form a metal lead.
Optionally, the depth of the notch is 10-50% of the depth of the through hole.
Optionally, the length of the protrusion protruding from the sidewall of the body is in a range of 15 to 30 nm.
Optionally, the step of forming a through hole and a notch in a sidewall of one side of the through hole opening in the first dielectric layer includes:
forming a groove with the bottom positioned in the first dielectric layer;
and continuously etching the first dielectric layer along the edge of the groove to form a through hole which penetrates through the first dielectric layer and has a size smaller than that of the groove, wherein the notch is formed at the part of the groove, which is positioned outside the through hole.
Optionally, the step of forming the groove in the first dielectric layer includes: forming a first mask layer on the first dielectric layer; removing part of the first dielectric layer with the first mask layer as a mask to form a groove;
continuously etching the first dielectric layer along the edge of the groove to form a through hole which penetrates through the first dielectric layer and has a size smaller than that of the groove, wherein the step of forming the through hole comprises the following steps: forming a flat layer in the groove and on the surface of the first medium layer; forming a second mask layer on the planarization layer; etching the flat layer and the first dielectric layer by taking the second mask layer as a mask until the substrate is exposed, and forming a through hole penetrating through the first dielectric layer; and removing the second mask layer and the flat layer.
Optionally, the first mask layer is a first anti-reflection layer, and the step of forming the groove includes: removing a part of the first dielectric layer with a certain thickness by adopting a dry etching process to form a groove;
the second mask layer is a second anti-reflection layer, and the step of forming the through hole comprises the following steps: and etching the first dielectric layer by adopting a dry etching process until the substrate is exposed.
Optionally, the step of forming a through hole and a notch in a sidewall of one side of the through hole opening in the first dielectric layer includes:
forming a through hole exposing the substrate in the first dielectric layer;
and removing a part of the first medium layer with the thickness in the side wall of one side of the through hole opening so as to form a notch in the side wall of one side of the through hole opening.
Optionally, the step of forming the through hole includes: forming a third mask layer on the first dielectric layer; etching the first dielectric layer by taking the third mask layer as a mask to form a through hole;
the step of forming the notch includes: forming a sacrificial layer in the through hole and on the first dielectric layer; forming a fourth mask layer on the sacrificial layer; etching the sacrificial layer and removing part of the first dielectric layer to form a notch by taking the fourth mask layer as a mask; and removing the sacrificial layer.
Optionally, the material of the sacrificial layer comprises amorphous carbon, an organic anti-reflective coating material or an inorganic anti-reflective coating material;
the step of removing the sacrificial layer comprises: removing the sacrificial layer by adopting a plasma etching process;
the etchant used in the plasma etching process includes oxygen, hydrogen or nitrogen.
Optionally, the step of forming a conductive plug in the through hole and the notch includes:
and filling tungsten in the through hole and the gap by adopting a physical vapor deposition method to form a conductive plug.
Optionally, the step of filling a metal material in the trench to form a metal lead includes:
and filling copper in the groove by adopting a copper electroplating process to form a metal lead.
Optionally, after providing the substrate, before forming the first dielectric layer on the substrate, forming a gate structure and a source and a drain in the substrate at two sides of the gate structure on the substrate;
and in the step of forming the through hole in the first dielectric layer, the through hole exposes the source electrode or the drain electrode.
Optionally, after the gate structure and the source or drain on both sides of the gate structure are formed on the substrate, and before the step of forming the first dielectric layer on the substrate, a metal silicide is formed on the source and drain, and in the step of forming the through hole in the first dielectric layer, the through hole exposes the metal silicide.
Optionally, in the step of forming the trench in the second dielectric layer, the trench exposes the protrusion of the conductive plug and a part of the main body of the conductive plug, or the trench exposes the protrusion of the conductive plug and the whole main body of the conductive plug.
The present invention also provides an interconnect structure comprising:
a substrate;
a first dielectric layer located on the substrate;
the conductive plug is positioned in the first dielectric layer and provided with a main body and a protruding part protruding from one side wall of the top end of the main body;
the second dielectric layer is positioned on the first dielectric layer and the conductive plug;
and the metal lead is positioned in the second dielectric layer and can be at least contacted with the bulge of the conductive plug.
Optionally, the thickness of the protruding portion is 10-50% of the thickness of the main body.
Optionally, the length of the protrusion protruding from the sidewall of the body is in a range of 15 to 30 nm.
Optionally, the metal lead is in contact with the protrusion of the conductive plug and a part of the main body of the conductive plug, or the metal lead is in contact with the protrusion of the conductive plug and the whole main body of the conductive plug.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method of the interconnection structure provided by the invention, a through hole and a notch positioned in the side wall of the opening of the through hole are formed in a first dielectric layer on a substrate; forming a conductive plug in the through hole and the notch, the conductive plug having a main body in the through hole and a protrusion in the notch; forming a second dielectric layer on the first dielectric layer and the conductive plug; forming a groove in the second dielectric layer, wherein the groove at least can expose the bulge of the conductive plug; and filling a metal material in the groove to form a metal lead. When the main body of the conductive plug and the metal lead are deformed and dislocated and the contact area between the metal lead and the main body is reduced, the protruding part is still covered by the metal lead and is in contact with the metal lead, so that good contact between the conductive plug and the metal lead can be ensured.
Drawings
FIGS. 1 and 2 are schematic diagrams of a method of forming an interconnect structure according to the prior art;
FIGS. 3-10 are schematic diagrams of steps in one embodiment of a method of forming an interconnect structure according to the present invention;
FIGS. 11-15 are schematic diagrams of another embodiment of a method of forming an interconnect structure of the present invention;
FIG. 16 is a schematic diagram of an embodiment of an interconnect structure of the present invention.
Detailed Description
As described in the background, in the prior art interconnect structure, a defect of too small a contact area is easily generated between the conductive plug and the metal lead covering the conductive plug, thereby causing poor contact.
The invention provides a forming method of an interconnection structure, which comprises the steps of forming a through hole and a notch positioned in the side wall of one side of the opening of the through hole in a first dielectric layer on a substrate; forming a conductive plug in the through hole and the notch, the conductive plug having a main body in the through hole and a protrusion in the notch; forming a second dielectric layer on the first dielectric layer and the conductive plug; forming a groove in the second dielectric layer, wherein the groove at least can expose the bulge of the conductive plug; and filling a metal material in the groove to form a metal lead. When the main body of the conductive plug and the metal lead are deformed or dislocated, so that the contact area between the metal lead and the main body is reduced, the protruding part is still covered by the metal lead and is in contact with the metal lead, and good contact between the conductive plug and the metal lead can be ensured.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments of the present invention accompanied with figures are described in detail below.
Fig. 3 to 10 are schematic diagrams of respective steps in an embodiment of a method for forming an interconnect structure according to the present invention.
The forming method of the interconnection structure of the embodiment comprises the following steps:
a substrate 100 is provided. In this embodiment, the substrate 100 is a silicon substrate, and in other embodiments, the substrate 100 may also be other semiconductor substrates such as a silicon germanium substrate or a silicon on insulator substrate, which is not limited in this invention.
With continued reference to fig. 3, in the present embodiment, a gate structure is formed on the substrate 100, and the gate structure includes a gate 103 and a gate dielectric layer (not shown).
In this embodiment, after the gate 103 is formed, a sidewall structure 105 located on the sidewall and the top of the gate 103 is also formed.
Specifically, the gate 103 is made of polysilicon, and the sidewall structure 105 is made of silicon nitride, but the invention is not limited to the materials of the gate 103 and the sidewall structure 105, in other embodiments, the gate 103 may also be made of metal, and the sidewall structure 105 may also be made of silicon oxide.
Before forming the sidewall structure 105, the method for forming an interconnect structure of this embodiment further includes: a protective layer 104 is formed on top of the gate 103 for protecting the gate 103, and the gate structure further includes the protective layer 104. In this embodiment, the material of the protection layer 104 is silicon nitride, but the invention is not limited to the material of the protection layer 104, nor to whether the protection layer 105 is formed.
In the present embodiment, after a plurality of gate structures are formed, a source and a drain (not shown) are formed in the substrate 100 at both sides of the gate structures, and a metal silicide layer 101 is formed on the source and the drain. The metal silicide layer 101 functions to improve the contact between the source and drain electrodes and conductive plugs to be formed on the source and drain electrodes. However, the invention is not limited to whether the metal silicide layer 101 is formed after the source and the drain are formed, and in other embodiments, the metal silicide layer 101 may be formed at the bottom of the via hole after a first dielectric layer is formed on the substrate and the via hole exposing the source or the drain is formed in the first dielectric layer.
With continued reference to fig. 3, in the present embodiment, after the metal silicide layer 101 is formed, a first dielectric layer 106 is formed on the substrate 100 and the gate structure.
In this embodiment, the material of the first dielectric layer 106 is silicon oxide. However, the material of the first dielectric layer 106 is not limited in the present invention, and in other embodiments, the material of the first dielectric layer 106 may also be a low-K dielectric layer or an ultra-low-K dielectric layer, such as a porous dielectric.
Referring to fig. 3 to 7, a through hole 113A and a notch 113B located in a side wall of an opening of the through hole 113A are formed in the first dielectric layer 106.
The via 113A is used to form the body of a conductive plug for electrically connecting a source or drain with a metal lead. The notch 113B is used to form a protruding portion of the conductive plug, and the protruding portion is used to increase the contact area between the conductive plug and the metal lead, so that when a defect that the contact area between the main body of the conductive plug and the metal lead is too small occurs, good contact performance can still be ensured between the protruding portion of the conductive plug and the metal lead.
In this embodiment, the depth of the notch 113B is 10 to 50% of the depth of the through hole 113A.
It should be noted that, in the present embodiment, a plurality of conductive plugs and metal wires covering different conductive plugs are simultaneously formed in the first dielectric layer 106 at different positions of the substrate 100. At the position where the adjacent metal leads are closely arranged, or the position where the bent portion of the metal lead covers the conductive plug, or the position where the edge of the metal lead covers the conductive plug, the metal lead is easily deformed due to photolithography and the like, for example, the size of the metal lead is reduced, and then the defect of too small contact area as described in the background art occurs.
In this embodiment, a simulation of the interconnect layout design may be performed prior to providing the substrate 100. Based on the simulation of layout design, the position where the defect that the contact area is too small is easily generated between the metal lead and the conductive plug is found. And forming a notch in the side wall on one side of the opening of the through hole at the position where the defect that the contact area is too small is easily generated, so that the notch faces to the subsequent metal lead forming position. In this way, after the conductive plug is formed in the through hole and the notch, the conductive plug has a main body located in the through hole and a projection located in the notch, and the projection is closer to the metal lead than the main body, and the projection is in contact with the metal lead, so that the contact area of the metal lead and the conductive plug is increased.
Specifically, in the present embodiment, referring to fig. 3, the step of forming a through hole 113A and a notch 113B in a sidewall of one side of an opening of the through hole 113A in the first dielectric layer 106 includes:
a first masking layer 107 is formed on the first dielectric layer 106, and a first opening 108 for forming an initial gap is formed in the first masking layer 107.
Specifically, in the present embodiment, the first mask layer 107 is a first antireflection layer. The first Anti-reflection layer may be a Bottom Anti-reflection Coating (BARC) layer commonly used in the field of photolithography, and may include an organic Anti-reflection Coating material layer, an inorganic Anti-reflection Coating material layer, or an organic Anti-reflection Coating material and an inorganic Anti-reflection Coating material superposition layer. The first anti-reflection layer has the function of reducing the notch effect and the standing wave effect during exposure, so that the formed initial notch appearance is better, but the invention does not limit the specific structure and the material of the first anti-reflection layer.
In this embodiment, a photoresist layer is formed on the first mask layer 107, and the first mask layer 107 is etched by dry etching using the photoresist layer as a mask to form the first opening 108. The invention is not limited to a particular method of forming the first opening 108.
Referring to fig. 5, using the first mask layer 107 as a mask, the first dielectric layer 106 exposed by the first opening 108 is removed, and a groove 109 with a bottom located in the first dielectric layer 106 is formed. The recess 109 is used to form a notch.
Optionally, the depth of the groove 109 is in a range of 150 to 600 angstroms, and the depth of the groove 109 is the depth of a subsequently formed notch.
In this embodiment, a dry etching process is used to remove a portion of the thickness of the first dielectric layer 106 exposed by the first opening 108, so as to form a groove 109. The invention is not limited to a particular process for removing a portion of the thickness of the first dielectric layer 106.
It should be noted that the present invention is not limited to a specific method for forming the recess 109 in the first dielectric layer 106, and in other embodiments, the recess 109 may be formed in other manners.
Referring to fig. 6 in combination, a planarization layer 110 is formed in the recess 109 and on the surface of the first dielectric layer 106.
A second mask layer 111 is formed on the planar layer 110, and the planar layer 110 provides a planar surface for forming the second mask layer 111.
The second mask layer 111 has a second opening 112 for forming a via hole therein, the second opening 112 is located above the groove 109, and as shown by the dotted line in fig. 6, a dimension D1 of the second opening 112 is smaller than a dimension D2 of the groove 109, and an edge of the second opening 112 is aligned with an edge of the groove 109.
Specifically, in this embodiment, the material of the planarization layer 110 is amorphous carbon, the second mask layer 111 is a second Anti-reflection layer, which may be a Bottom Anti-reflection Coating (BARC) commonly used in the photolithography field, and may include an organic Anti-reflection Coating material layer, an inorganic Anti-reflection Coating material layer, or an organic Anti-reflection Coating material and an inorganic Anti-reflection Coating material stacked layer. The second anti-reflection layer has the function of reducing the notch effect and the standing wave effect during exposure, so that the formed through hole has better appearance, but the invention does not limit the specific structure and the material of the second anti-reflection layer.
It should be noted that, in the present embodiment, the second opening 112 is used to form a through hole, and the through hole is used to form a conductive plug connecting the source or the drain and the metal wire, so that the second opening 112 is located above the source or the drain between two adjacent gate structures. In this embodiment, since the metal silicide layer 101 is formed on the source or the drain, the second opening 112 is located above the metal silicide layer 101.
Referring to fig. 7, using the second mask layer 111 as a mask, the planarization layer 110 exposed by the second opening 112 is removed, and the first dielectric layer 106 is etched continuously along the edge of the groove 109, so as to form a via 113A penetrating through the first dielectric layer 106. In the present embodiment, since the metal silicide layer 101 is formed in advance, the first dielectric layer 106 is etched to expose the metal silicide layer 101. In other embodiments where the metal silicide layer 101 is not provided, the via 113A exposes a source or a drain in the substrate 100, and the via 118A may also expose only the substrate 100 when the interconnect structure is used to connect other semiconductor devices other than transistors.
Specifically, in the present embodiment, a dry etching process is used to remove the first dielectric layer 106 exposed by the second opening 112 until the metal silicide layer 101 is exposed.
The second mask layer 111 and the planarization layer 110 are removed, and the portion of the groove 109 located outside the via 113A forms a notch 113B, i.e. the notch 113B is located in the sidewall of the opening of the via 113A except one side.
Referring to fig. 8, a conductive plug 114 having a main body 114A in the through hole 113A and a protrusion 114B in the notch 113B is formed in the through hole 113A and the notch 113B. Since the notch 113B is located in the side wall of the opening of the through hole 113A, the protrusion 114B is located at the top end of the main body 114A and protrudes out of the side wall of the main body 114.
Specifically, in this embodiment, a physical vapor deposition method is adopted to fill the metal material layer in the through hole 113A and the gap 113B, and the metal material layer is subjected to chemical mechanical polishing to form the conductive plug 114. The conductive plug 114 is made of tungsten, but the present invention does not limit the specific material of the conductive plug 114, nor the specific process for filling the metal material layer in the through hole 113A and the gap 113B.
Referring to fig. 9, a second dielectric layer 115 is formed on the first dielectric layer 106 and the conductive plug 114. The second dielectric layer 115 may be silicon oxide, a low-K material (K value less than 3), or an ultra-low-K material (K value less than 2.6), and the specific material of the second dielectric layer 115 is not limited in the present invention.
After forming the second dielectric layer 115, a trench 116 is formed in the second dielectric layer 115, wherein the trench 116 exposes at least the protrusion 114B of the conductive plug 114, and the trench 116 is used to form a metal wire to connect to the top of the conductive plug 114. It should be noted that the design shape of the trench 116 is to expose the main body 114A and the protrusion 114B of the conductive plug 114, but in actual production, due to diffraction effect of the exposure process or process deviation occurring in etching the third opening 116, the actual shape of the trench 116 may deviate from the design shape, for example, shrink, so that the trench 116 does not completely expose the main body 114A of the conductive plug 114, thereby reducing the contact area between the metal lead formed in the trench 116 and the main body 114A.
Depending on different process conditions, the trench 116 may expose the protrusion 114B of the conductive plug 114 and a portion of the body 114A of the conductive plug 114, or the trench 116 may expose the protrusion 114B of the conductive plug 114 and the entire body 114A of the conductive plug 114.
Referring to fig. 10, a metal wire 117 is formed in a trench 116 in a second dielectric layer 115. The metal lead 117 covers the top of the conductive plug 114. At least the protrusion 114B of the conductive plug 114 can be exposed due to the groove 116. The convex portion 114B is closer to the metal lead 117 than the main body 114A, and the convex portion 114B is in contact with the metal lead 117, so that the contact area of the metal lead 117 and the conductive plug 114 is increased. In the case where the contact area of the main body 114A and the metal lead 117 formed in the third opening 116 is reduced, the protruding portion 114B functions to make a good conductive contact between the conductive plug 114 and the metal lead 117, improving the performance of the interconnect structure.
In the present embodiment, a copper electroplating process is used to fill the trench 116 with copper to form a metal lead 117. The present invention is not limited to a particular process for forming the metal lead 117.
It should be noted that, if the thickness of the protruding portion 114B is too large, the protruding portion 114B occupies too large a volume of the first dielectric layer 106, and may interact with the semiconductor structure in the first dielectric layer 106, thereby affecting the performance of the interconnect structure or the transistor; if the thickness of the projection 114B is too small, the contact of the projection 114B with the metal lead 117 may be weakened.
In the present embodiment, since the depth of the notch 113B is 10 to 50% of the depth of the through hole 113A, as shown in fig. 10, the thickness H1 of the protrusion 114B is 10 to 50% of the thickness H2 of the main body 114A, and optionally, the thickness H1 of the protrusion 114B is determined by the depth of the groove 109, and the thickness of the protrusion 114B is in the range of 150 to 600 angstroms.
It should be noted that, if the length of the protrusion 114B protruding from the sidewall of the main body 114A is too large, the protrusion 114B is liable to form a large parasitic capacitance with the gate 103, the source, or the drain, which affects the performance of the interconnect structure or the transistor; if the length of the protrusion 114B protruding from the sidewall of the main body 114A is too small, the contact between the protrusion 114B and the metal lead 117 may be weakened. Alternatively, in the present embodiment, as shown in fig. 10, the length F1 of the protrusion 114B protruding from the sidewall of the main body 114A is in the range of 15 to 30 nm.
Fig. 11 to 15 show schematic views of another embodiment of the present invention. The present embodiment is different from the above embodiments in that a through hole is formed in the first dielectric layer 106, and a step of forming a notch in a sidewall of the through hole opening is different.
Referring to fig. 11 to 15, the step of forming a through hole in the first dielectric layer 106 and forming a notch in a sidewall of one side of the through hole opening includes:
referring to fig. 11, a third mask layer 201 is formed on the first dielectric layer 106, and the third mask layer 201 has a third opening 202 for forming a via.
The third opening 202 is used to form a through hole, and the through hole is used to form a conductive plug connecting the source/drain and the metal lead, so that the third opening 202 is located above the source/drain between two adjacent gate structures, i.e., above the metal silicide layer 101.
It should be noted that, in this embodiment, the third mask layer 201 includes a third Anti-reflection layer, which may be a Bottom Anti-reflection Coating (BARC) commonly used in the field of photolithography, and may include an organic Anti-reflection Coating material layer, an inorganic Anti-reflection Coating material layer, or an overlying layer of the organic Anti-reflection Coating material and the inorganic Anti-reflection Coating material layer. The third anti-reflection layer has the function of reducing the notch effect and the standing wave effect during exposure, so that the formed through hole has better appearance, but the invention does not limit the specific structure and the material of the third anti-reflection layer.
Referring to fig. 12, the third mask layer 201 is used as a mask to etch the first dielectric layer 106 exposed by the third opening 202 until the metal silicide layer 101 is exposed, thereby forming a via hole 118A.
In this embodiment, since the metal silicide layer 101 is formed in advance, the first dielectric layer 106 exposed by the third opening 202 is etched until the metal silicide layer 101 is exposed, and the via hole 118A is formed. In other embodiments, if the metal silicide layer 101 is not formed, the via 118A exposes the source or the drain in the substrate 100, and when the interconnect structure is used to connect other semiconductor devices other than transistors, the via 118A may only expose the substrate 100.
In this embodiment, the method for etching the first dielectric layer 106 exposed by the third opening 202 may be a plasma etching method, and the like, which is not limited in the present invention.
Referring to fig. 13, a sacrificial layer 203 is formed in the via hole 118A and on the first dielectric layer 106.
In this embodiment, the material of the sacrificial layer 203 is amorphous carbon, and the sacrificial layer 203 is easily removed, so that the cleanliness of the inner surface of the through hole 118A and the subsequently formed gap is high, and the performance of the conductive plug is improved. However, the present invention is not limited to the specific material of the sacrificial layer 203, and in other embodiments, the material of the sacrificial layer 203 may also be an organic anti-reflective coating material or an inorganic anti-reflective coating material.
With continued reference to fig. 13, in the present embodiment, a fourth mask layer 204 is formed on the sacrificial layer 203, the fourth mask layer 204 has a fourth opening 119 for forming a notch, and the fourth opening 119 is located above the via 118A and a sidewall of the via 118A.
Referring to fig. 14, using the fourth mask layer as a mask, the sacrificial layer 203 is etched and a portion of the thickness of the first dielectric layer 106 is removed, thereby forming a gap 118B in the first dielectric layer 106. Since the fourth opening 119 is located above the through hole 118A and a side wall of the through hole 118A, the notch 118B is located in the side wall of the opening of the through hole 118A.
Referring to fig. 15, the sacrificial layer 203 is removed.
In this embodiment, the step of removing the sacrificial layer 203 includes: and removing the sacrificial layer 203 by using a plasma etching process, wherein an etchant used in the plasma etching process comprises oxygen, hydrogen or nitrogen.
After removing the sacrificial layer 203, the via hole 118A and the gap 118B are exposed, and then the via hole 118A and the gap 118B may be filled with a metal material to form a body and a protrusion of the conductive plug.
The through hole 118A and the notch 118B formed by the above embodiment have higher surface cleanliness of the inner wall, and the conductive plug formed in the through hole 118A and the notch 118B has better appearance, which is beneficial to improving the performance of the conductive plug.
The present invention also provides an interconnect structure that can be formed, but is not limited to, using the method of forming the interconnect structure of the present invention.
Referring to fig. 16, a schematic diagram of an embodiment of the interconnect structure of the present invention is shown, where the interconnect structure of this embodiment includes:
substrate 100'. In this embodiment, the substrate 100 'is a silicon substrate, and in other embodiments, the substrate 100' may also be other semiconductor substrates such as a silicon germanium substrate or a silicon on insulator substrate, which is not limited in this invention.
With reference to fig. 16, in this embodiment, a gate structure is further formed on the substrate 100 ', and the gate structure includes a gate 103' made of polysilicon, and a sidewall 105 'located on a sidewall of the gate 103' and made of silicon nitride.
It should be noted that, in this embodiment, the material of the gate 103 ' is polysilicon, but the material of the gate 103 ' is not limited in the present invention, and in other embodiments, the material of the gate 103 ' may also be a metal material.
It should be noted that, in this embodiment, a protection layer 104 is formed on the top of the gate 103 ', the gate structure further includes a protection layer 104 ', the protection layer 104 ' is used to protect the gate 103 ', and the protection layer 104 ' is made of silicon nitride, but the material of the protection layer 104 ' and whether the protection layer 104 ' is formed are not limited.
In the present embodiment, the interconnection structure includes a plurality of gate structures on the substrate 100 ', and source and drain electrodes (not shown) formed in the substrate 100 ' between the plurality of gate structures, and a metal silicide layer 101 ' on the source and drain electrodes. The metal silicide layer 101' functions to improve contact between the source and drain electrodes and conductive plugs to be formed on the source and drain electrodes.
With continued reference to fig. 16, in this embodiment, the interconnect structure further includes:
a first dielectric layer 106 'on the substrate 100' and the gate structure.
In this embodiment, the material of the first dielectric layer 106' is silicon oxide. However, the material of the first dielectric layer 106 'is not limited in the present invention, and in other embodiments, the material of the first dielectric layer 106' may also be a low-K dielectric layer or an ultra-low-K dielectric, such as a porous dielectric.
A conductive plug 114 ' located in the first dielectric layer 106 ', the conductive plug having a main body 114 ' A and a protrusion 114B ' protruding from a side wall of a top end of the main body 114A '.
A second dielectric layer 115 'and a metal wire 117' disposed on the first dielectric layer 106 'and the conductive plug, wherein the metal wire 117' can at least contact with the protrusion 114B 'of the conductive plug 114'. The protrusion 114B 'is closer to the metal lead 117' than the main body, and the protrusion 114B 'contacts with the metal lead 117', so that the contact area between the metal lead 117 'and the conductive plug 114' is increased.
In the actual process, in the formed interconnect structure, the metal lead 117 'contacts with the protrusion 114B' of the conductive plug and a part of the main body 114A 'of the conductive plug, or the metal lead 117' contacts with the protrusion 114B 'of the conductive plug and the whole main body 114A' of the conductive plug.
It should be noted that, in the present embodiment, a plurality of conductive plugs and metal leads covering different conductive plugs are simultaneously formed in the first dielectric layer 106 'at different positions of the substrate 100'. At the position where the adjacent metal leads are closely arranged, or the position where the bent portion of the metal lead covers the conductive plug, or the position where the edge of the metal lead covers the conductive plug, the metal lead is easily deformed by photolithography and the like, for example, the size of the metal lead is reduced, and then the defect of too small contact area as described in the background art occurs.
In this embodiment, the simulation of the layout design of the interconnect structure may be performed in advance. Based on the simulation of layout design, finding out the defect position with too small contact area between the metal lead and the conductive plug; when the layout is designed, the interconnection structure of the embodiment is used for generating a defect position with an excessively small contact area between the metal lead and the conductive plug. A protrusion 'is provided on the main body of these conductive plugs, which are prone to generate defective positions, and is closer to the metal lead than the main body, and the protrusion contacts with the metal lead 117', so that the contact area between the metal lead and the conductive plug is increased. The protruding part plays a role in enabling the conductive plug and the metal lead to generate good conductive contact, and performance of the interconnection structure is improved.
In this embodiment, the material of the conductive plug is tungsten, but the specific material of the conductive plug is not limited in the present invention.
In this embodiment, the second dielectric layer 115 'may be silicon oxide, a low-K material (K value is less than 3) or an ultra-low-K material (K value is less than 2.6), and the invention is not limited to the specific material of the second dielectric layer 115'.
It should be noted that, if the thickness of the protruding portion 114B 'is too large, the protruding portion 114B' occupies too large volume of the first dielectric layer 106 ', and may interact with the semiconductor structure in the first dielectric layer 106', thereby affecting the performance of the interconnect structure or the transistor; if the thickness of the protruding portion 114B ' is too small, the contact of the protruding portion 114B ' with the metal lead 117 ' may be weakened. In the present embodiment, as shown in fig. 16, the thickness H1 'of the protrusion 114B' is 10-50% of the thickness H2 'of the main body 114A', and optionally, the thickness H1 'of the protrusion 114B' is in the range of 150 to 600 angstroms.
It should be noted that, if the length of the protrusion 114B 'protruding from the sidewall of the body 114A' is too large, the protrusion 114B 'is liable to form a larger parasitic capacitance with the gate 103', the source, or the drain, which affects the performance of the interconnect structure or the transistor; if the length of the protrusion 114B 'protruding from the main body 114A' is too small, the contact between the protrusion 114B 'and the metal lead 117' may be weakened. Optionally, in this embodiment, the length F1 ' of the protrusion 114B ' protruding from the sidewall of the main body 114A ' is in the range of 15 to 30 nanometers.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (16)
1. A method for forming an interconnect structure, comprising:
providing a substrate;
forming a first dielectric layer on the substrate;
forming a through hole and a notch in the side wall at one side of the opening of the through hole in the first medium layer;
forming a conductive plug in the through hole and the notch, the conductive plug having a main body in the through hole and a protrusion in the notch;
forming a second dielectric layer on the first dielectric layer and the conductive plug;
forming a groove in the second dielectric layer, wherein the groove at least can expose the bulge of the conductive plug;
filling a metal material in the groove to form a metal lead;
the depth of the notch is 10-50% of the depth of the through hole.
2. The method of forming as claimed in claim 1, wherein the length of the protrusion from the body sidewall is in a range of 15 to 30 nanometers.
3. The method of claim 1, wherein forming a via in the first dielectric layer and a notch in a sidewall at a side of the via opening comprises:
forming a groove with the bottom positioned in the first dielectric layer;
and continuously etching the first dielectric layer along the edge of the groove to form a through hole which penetrates through the first dielectric layer and has a size smaller than that of the groove, wherein the notch is formed at the part of the groove, which is positioned outside the through hole.
4. The forming method of claim 3,
the step of forming a recess in the first dielectric layer comprises: forming a first mask layer on the first dielectric layer; removing part of the first dielectric layer with the first mask layer as a mask to form a groove;
continuously etching the first dielectric layer along the edge of the groove to form a through hole which penetrates through the first dielectric layer and has a size smaller than that of the groove, wherein the step of forming the through hole comprises the following steps: forming a flat layer in the groove and on the surface of the first medium layer; forming a second mask layer on the planarization layer; etching the flat layer and the first dielectric layer by taking the second mask layer as a mask until the substrate is exposed, and forming a through hole penetrating through the first dielectric layer; and removing the second mask layer and the flat layer.
5. The method of claim 4, wherein the first mask layer is a first anti-reflective layer, and the step of forming the recess comprises: removing a part of the first dielectric layer with a certain thickness by adopting a dry etching process to form a groove;
the second mask layer is a second anti-reflection layer, and the step of forming the through hole comprises the following steps: and etching the first dielectric layer by adopting a dry etching process until the substrate is exposed.
6. The method of claim 1, wherein forming a via in the first dielectric layer and a notch in a sidewall at a side of the via opening comprises:
forming a through hole exposing the substrate in the first dielectric layer;
and removing a part of the first medium layer with the thickness in the side wall of one side of the through hole opening so as to form a notch in the side wall of one side of the through hole opening.
7. The method of forming as claimed in claim 6, wherein the step of forming the via hole includes: forming a third mask layer on the first dielectric layer; etching the first dielectric layer by taking the third mask layer as a mask to form a through hole;
the step of forming the notch includes: forming a sacrificial layer in the through hole and on the first dielectric layer; forming a fourth mask layer on the sacrificial layer; etching the sacrificial layer and removing part of the first dielectric layer to form a notch by taking the fourth mask layer as a mask; and removing the sacrificial layer.
8. The method of forming of claim 7, wherein a material of the sacrificial layer comprises amorphous carbon, an organic anti-reflective coating material, or an inorganic anti-reflective coating material;
the step of removing the sacrificial layer comprises: removing the sacrificial layer by adopting a plasma etching process;
the etchant used in the plasma etching process includes oxygen, hydrogen or nitrogen.
9. The method of forming of claim 1, wherein the step of forming conductive plugs in the vias and gaps comprises:
and filling tungsten in the through hole and the gap by adopting a physical vapor deposition method to form a conductive plug.
10. The method of forming of claim 1, wherein the trench is filled with a metal material, the step of forming a metal lead comprising:
and filling copper in the groove by adopting a copper electroplating process to form a metal lead.
11. The method of forming of claim 1, wherein after providing the substrate, and before the step of forming the first dielectric layer on the substrate, forming a gate structure on the substrate and a source and a drain in the substrate on both sides of the gate structure;
and in the step of forming the through hole in the first dielectric layer, the through hole exposes the source electrode or the drain electrode.
12. The method of claim 11, wherein after forming the gate structure and the source or drain on either side of the gate structure on the substrate, a metal silicide is formed on the source and drain before forming a first dielectric layer on the substrate, and wherein in the step of forming the via in the first dielectric layer, the via exposes the metal silicide.
13. The method of forming of claim 1, wherein in the step of forming a trench in the second dielectric layer, the trench exposes the protrusion of the conductive plug and a portion of the body of the conductive plug, or the trench exposes the protrusion of the conductive plug and the entire body of the conductive plug.
14. An interconnect structure, comprising:
a substrate;
a first dielectric layer located on the substrate;
the conductive plug is positioned in the first dielectric layer and provided with a main body and a protruding part protruding from one side wall of the top end of the main body;
the second dielectric layer is positioned on the first dielectric layer and the conductive plug;
a metal lead in the second dielectric layer, the metal lead being at least capable of contacting the protrusion of the conductive plug;
the thickness of the protruding part is 10-50% of the thickness of the main body.
15. The interconnect structure of claim 14 wherein the length of said protrusion from the body sidewall is in the range of 15 to 30 nanometers.
16. The interconnect structure of claim 14, wherein the metal lead contacts the protrusion of the conductive plug and a portion of the body of the conductive plug, or the metal lead contacts the protrusion of the conductive plug and the entire body of the conductive plug.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08293547A (en) * | 1995-04-25 | 1996-11-05 | Matsushita Electron Corp | Semiconductor device |
| JP2008004734A (en) * | 2006-06-22 | 2008-01-10 | Nec Corp | Integrated passive element, and multi-layer wiring substrate incorporating the same |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3114931B2 (en) * | 1998-03-30 | 2000-12-04 | 日本電気株式会社 | Semiconductor device having conductor plug and method of manufacturing the same |
| JP2001358215A (en) * | 2000-06-16 | 2001-12-26 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| CN1237598C (en) * | 2001-08-22 | 2006-01-18 | 联华电子股份有限公司 | Method for forming metal capacitor in inlaying mfg. process |
| TWI223380B (en) * | 2003-07-14 | 2004-11-01 | Nanya Technology Corp | Semiconductor device and method of fabricating the same |
| CN100517623C (en) * | 2006-12-05 | 2009-07-22 | 中芯国际集成电路制造(上海)有限公司 | Wafer press welding and bonding method and structure thereof |
| US7880303B2 (en) * | 2007-02-13 | 2011-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked contact with low aspect ratio |
| CN101419923B (en) * | 2007-10-25 | 2010-09-29 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for lead wire welding mat |
| KR101602451B1 (en) * | 2010-01-22 | 2016-03-16 | 삼성전자주식회사 | Method of forming semiconductor device having contact plug and related device |
| US8435891B2 (en) * | 2011-06-02 | 2013-05-07 | International Business Machines Corporation | Converting metal mask to metal-oxide etch stop layer and related semiconductor structure |
-
2014
- 2014-12-04 CN CN201410734536.6A patent/CN105720039B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08293547A (en) * | 1995-04-25 | 1996-11-05 | Matsushita Electron Corp | Semiconductor device |
| JP2008004734A (en) * | 2006-06-22 | 2008-01-10 | Nec Corp | Integrated passive element, and multi-layer wiring substrate incorporating the same |
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