CN1237598C - Method for forming metal capacitor in inlaying mfg. process - Google Patents
Method for forming metal capacitor in inlaying mfg. process Download PDFInfo
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- CN1237598C CN1237598C CN 01130733 CN01130733A CN1237598C CN 1237598 C CN1237598 C CN 1237598C CN 01130733 CN01130733 CN 01130733 CN 01130733 A CN01130733 A CN 01130733A CN 1237598 C CN1237598 C CN 1237598C
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Abstract
The present invention relates to a method for forming metal capacitors in the process of inlaying production. Before the formation of a metal film capacitor, lower inner connecting lines are made by using the process of inlaying copper. A bottom electrode of the capacitor is formed in the process of inlaying production, and the process of inlaying production is simultaneously used for forming conductor wires and plugs. An anti-reflecting layer is formed on the top of an insulation layer which is used for isolating a double inlaid structure, the anti-reflecting layer can also be onto other anti-reflecting layers as a hard-coat screen layer, a grind termination layer and an etch stop layer, another insulation layer and a metallic layer are orderly formed, and micro-shadow etching is carried out so as to form a top electrode and a capacitor insulation layer. Upper inner connecting lines are made continuously by using the process of inlaying copper after capacitors are completely formed. The present invention has the advantages that the micro-shadow etching procedures in manufacturing an integrated circuit of a built-in capacitor are reduced, the fabricating cost is reduced, the integrated circuit of a built-in capacitor is lowered, the processes of forming the integrated circuit are easily controlled, and the integrated circuit of a built-in capacitor is formed by using the process of inlaying copper so as to reduce RC delay.
Description
Technical field
The invention relates to that a kind of formation includes the integrated circuit of capacitor, particularly relevant for a kind of method that in damascene process, forms metal capacitor.
Background technology
As everyone knows, capacitor can be integrated mutually with various integrated circuits.For example can be used as decoupling capacitance device (decoupling Capacitors), to be used for improving voltage-regulation (voltage regulation) and the interference resistant ability (noise immunity) of distribute power (power distr ibution) is provided.Can also be applied in analogy/logical circuit, analogy one digital converter, mixed type signal (mixedsignal) or radio frequency (radio frequency) circuit operation or the like.
Fig. 1-shown in Figure 4, shown in Figure 1 for the tradition manufacturing includes the method for the semiconductor element of capacitor 20, be deposition of aluminum metal level on insulating barrier 12, carry out the photoetching etch process subsequently, be patterned to aluminum metal layer 14a and 14b.Wherein insulating barrier 12 comprise some be formed on the silicon base and substrate in element (not illustrating).Then, on aluminum metal layer 14a and 14b and insulating barrier 12, form insulating barrier 16, and in this insulating barrier 16 and form tungsten plug (tungsten plug; W-plug) 18 electrically connect with aluminum metal layer 14a.Afterwards, depositing metal layers/dielectric layer/metal level in regular turn on tungsten plug 18 and insulating barrier 16, and carry out forming first conductive plate 21, dielectric layer 22 and second conductive plate 23, thereby constituting capacitor 20, as shown in Figure 2 after photoengraving carves.Wherein, first conductive plate 21 (being bottom electrode) is connected with aluminum metal layer 14a via tungsten plug 18.Continue at capacitor 20 and insulating barrier 16 tops deposit another layer insulating 26, and in the insulating barrier 16 of insulating barrier 26 and its below, form tungsten plug 28a and 28b simultaneously, as shown in Figure 3.Continuation deposits another layer aluminum metal layer above insulating barrier 26 and tungsten plug 28a and 28b, and carries out forming aluminum metal layer 34a and 34b, as shown in Figure 4 after photoengraving scribes journey.Wherein aluminum metal layer 34a is via tungsten plug 28a and first conductive plate 23 (being top electrode), and aluminum metal layer 34b electrically connects via the aluminum metal layer 14b of tungsten plug 28b and lower floor.Its major defect is:
In above-mentioned processing procedure, need extra lithography step to form capacitor 20, capacitor 20 could be integrated in the integrated circuit, therefore, increased the cost of whole manufacture of semiconductor.
Yet, above-mentionedly integrate intraconnections processing procedure and capacitor processing procedure with aluminum metal and can't adapt to gradually at present to improving the requirement of element integration and data transmission speed.Therefore, as lead, reduce RC and postpone (RC delay), become present development trend with metallic copper with high conductivity.But the copper metal can't come define pattern in the mode of dry ecthing, and its reason is the copper chloride (CuCl that copper metal and the gas reaction of chlorine electricity slurry generate
2) boiling point high (about 1500 ℃), so the making of copper conductor needs to carry out with damascene process (dama scene process).
Summary of the invention
Main purpose of the present invention provides a kind of method that forms metal capacitor in damascene process, by before forming film capacitor, in first insulating barrier, form first copper conductor and second copper conductor, and form first sealant on first and second copper conductors to being less than.Then on first sealant, form second insulating barrier and anti-reflecting layer in regular turn, when forming metal capacitor, only need extra one photoetching etching step, overcome the drawback of prior art, reach and reduce the photoetching etching step of making the integrated circuit that includes capacitor and the purpose that reduces manufacturing cost.
Second purpose of the present invention provides a kind of method that forms metal capacitor in damascene process, reaches the purpose of using less photoetching etching step to form the integrated circuit that contains capacitor.
The 3rd purpose of the present invention provides a kind of method that forms metal capacitor in damascene process, reaches the purpose that reduces the integrated circuit that includes capacitor.
The 4th purpose of the present invention provides a kind of method that forms metal capacitor in damascene process, reaches the purpose of processing procedure of the integrated circuit that includes capacitor of easy control.
The 5th purpose of the present invention provides a kind of method that forms metal capacitor in damascene process, reaches to use copper wiring to make the integrated circuit that includes capacitor, to reduce the purpose that RC postpones.
The object of the present invention is achieved like this: a kind of method that forms metal capacitor in damascene process is characterized in that: which comprises at least following steps:
(1) provides one first insulating barrier;
(2) in this first insulating barrier, form one first copper conductor and one second copper conductor;
(3) form one first sealant on this first and second copper conductor to being less than;
(4) on this first sealant, form one second insulating barrier;
(5) on this second insulating barrier, form an anti-reflecting layer;
(6) in this anti-reflecting layer, second insulating barrier and first sealant, form the dual-damascene structure that comprises the first bronze medal connector, one second bronze medal connector, one the 3rd copper conductor and the 4th copper conductor, wherein this first bronze medal connector is in order to connect the 3rd copper conductor and first copper conductor, and this second bronze medal connector is in order to connect the 4th copper conductor and second copper conductor;
(7) on this anti-reflecting layer, the 3rd copper conductor and the 4th copper conductor, form one the 3rd insulating barrier;
(8) on the 3rd insulating barrier, form a metal level;
(9) in this anti-reflecting layer as an etch stop layer, with this metal level and the 3rd insulating layer patternization, with in forming a top electrode and an insulating layer of capacitor corresponding to the 3rd copper conductor place;
(10) on this anti-reflecting layer and this top electrode, form one the 4th insulating barrier;
(11) in the 4th insulating barrier, form the dual-damascene structure that comprises the 3rd bronze medal connector, the 4th bronze medal connector, the 5th copper conductor and the 6th copper conductor, wherein the 3rd bronze medal connector is in order to connect the 5th copper conductor and top electrode, and the 4th bronze medal connector is in order to connect the 6th copper conductor and the 4th copper conductor;
(12) form one second sealant on the 5th and the 6th copper conductor to being less than.
The material of this anti-reflecting layer is to select at least a in silicon oxynitride or carborundum.The material of the 3rd insulating barrier is to select at least a in silicon nitride, silicon oxynitride, carborundum, tantalum oxide, zirconia, hafnium oxide or aluminium oxide.The thickness of the 3rd insulating barrier is between 100 dust to 1200 dusts.The material of this metal level is to select at least a in titanium, titanium nitride, tantalum, tantalum nitride, aluminium or aluminium copper.This metal layer thickness is between 100 dust to 2000 dusts.
The another kind of method that forms metal capacitor in damascene process is characterized in that: which comprises at least following steps:
(1) provides one first insulating barrier;
(2) in this first insulating barrier, form one first copper conductor and one second copper conductor;
(3) form one first sealant on this first and second copper conductor to being less than;
(4) on this first sealant, form one second insulating barrier;
(5) on this second insulating barrier, form an anti-reflecting layer;
(6) in this anti-reflecting layer, second insulating barrier and first sealant, form the dual-damascene structure that comprises the first bronze medal connector, the second bronze medal connector, the 3rd copper conductor and the 4th copper conductor, wherein this first bronze medal connector is in order to connect the 3rd copper conductor and first copper conductor, and this second bronze medal connector is in order to connect the 4th copper conductor and second copper conductor;
(7) on this anti-reflecting layer, the 3rd copper conductor and the 4th copper conductor, form one second sealant;
(8) on this second sealant, form the 3rd insulating barrier;
(9) on the 3rd insulating barrier, form a metal level;
(10) on this second sealant as an etch stop layer, with this metal level and the 3rd insulating layer patternization, with in forming a top electrode and an insulating layer of capacitor corresponding to the 3rd copper conductor place, wherein the part of this second sealant is also as this insulating layer of capacitor;
(11) on this second sealant and this top electrode, form one the 4th insulating barrier;
(12) in the 4th insulating barrier and this second sealant, form the dual-damascene structure that comprises the 3rd bronze medal connector, the 4th bronze medal connector, the 5th copper conductor and the 6th copper conductor, wherein the 3rd bronze medal connector is in order to connect the 5th copper conductor and top electrode, and the 4th bronze medal connector is in order to connect the 6th copper conductor and the 4th copper conductor;
(13) form one the 3rd sealant on the 5th and the 6th copper conductor to being less than.
Describe in detail below in conjunction with preferred embodiment and conjunction with figs..
Description of drawings
Fig. 1-Fig. 4 is that tradition is integrated into flow process generalized section in the integrated circuit with capacitor.
Fig. 5-Figure 12 is the flow process generalized section that forms metal capacitor in damascene process of embodiments of the invention 1.
Figure 13-Figure 20 is the flow process generalized section that forms metal capacitor in damascene process of embodiments of the invention 2.
Embodiment
Embodiment 1
Consult Fig. 5-Figure 12, describe a kind of method that in damascene process, forms metal capacitor of the present invention's first preferred embodiment in detail.
Consult Fig. 5, on insulating barrier 102, form another layer insulating 106, wherein may comprise other intraconnections in the insulating barrier 102, and insulating barrier 102 belows comprise be formed in the substrate and substrate in element, describe content of the present invention in order to know, the circuit element of these bottoms is also not shown in the diagram.Utilize damascene process in insulating barrier 106, to form copper conductor 104a and the 104b that thickness is about 2000 to 6000 dusts.For instance, in insulating barrier 106, behind the formation groove, behind the barrier layer (not illustrating) of formation one deck compliance, insert the copper metal, carry out cmp afterwards, with worn unnecessary copper metal and barrier layer.Then forming sealant 108 at least on copper conductor 104a and 104b, is to be example to form comprehensive sealant 108 in the drawings, and its thickness is about the 100-400 Izod right side, and its material can be silicon nitride (SiN) or carborundum (SiC)
Then, on sealant 108, form insulating barrier 110 and anti-reflecting layer 112 in regular turn.When forming dual-damascene structure, anti-reflecting layer 112 can be used as hard mask, and when forming copper conductor, anti-reflecting layer 112 can be used as the grinding stop layer; When forming the top electrode of metal capacitor, anti-reflecting layer 112 can be used as etch stop layer.The material that is used to form anti-reflecting layer 112 can be silicon oxynitride (SiON) or carborundum (SiC).The thickness of anti-reflecting layer 112 is about the 100-600 Izod right side.
In anti-reflecting layer 112, insulating barrier 110 and sealant 108, form double-mosaic pattern, this pattern is made of interlayer fenestra 114a and 114b and groove 116a and 116b, its media layer window hole 114b can expose the surface of copper conductor 104b, and interlayer fenestra 114a can expose the surface of copper conductor 104a.
Consult Fig. 6, at the barrier layer (not illustrating) of anti-reflecting layer 112, interlayer fenestra 114a and 114b and groove 116a and 116b surface formation compliance.Deposited copper metal on barrier layer, and insert among interlayer fenestra 114a and 114b and groove 116a and the 116b.Utilize the cmp processing procedure to remove unnecessary part, and cooperate with anti-reflecting layer 112 as grinding stop layer, the dual-damascene structure that is constituted by copper connector 120a and 120b and copper conductor 122a and 122b with formation.Wherein, copper conductor 122a is the bottom electrode as metal capacitor.
Above-mentioned double-insert process except being used to form copper connector 120a and 120b and copper conductor 122b, also is used to form bottom electrode 122a.Therefore, do not need extra photoetching etch process to form bottom electrode 122a, moreover bottom electrode 122a is positioned at same plane with copper conductor 122b.
Then in anti-reflecting layer 112 and copper conductor 122a and the last insulating barrier 124 that forms of 122b, this insulating barrier 124 is the insulating layer of capacitor as metal capacitor.The thickness of insulating barrier 124 is about the 100-1200 Izod right side, yet actual thickness still needs the application of apparent capacity device and required capacitance thereof and decides.The material of insulating barrier 124 can be silicon nitride (Si
3N
4), silicon oxynitride (SiON), carborundum (SiC), tantalum oxide (TaO
2), zirconia (ZrO
2), hafnium oxide (HfO
2), aluminium oxide (Al
2O
3) or other have the material of high-k.
Consult Fig. 7, form metal level 126 on insulating barrier 124, this metal level 126 is that its thickness is about the 100-2000 Izod right side with the top electrode in order to the formation metal capacitor.The material of above-mentioned metal level 126 can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminium, aluminium copper (AlCu) etc.
Then consult Fig. 8, definition metal level 126 and insulating barrier 124, to form top electrode 126 and insulating layer of capacitor 124, its method is for carrying out the photoetching etch process, till the anti-reflecting layer 112 that exposes as etch stop layer.
According to above-mentioned step, when forming metal capacitor 128, only need extra one photoetching etching step.Therefore, the photoetching etching step of making the integrated circuit that includes capacitor can be reduced, manufacturing cost can also be reduced.
The zone of formed bottom electrode 122a is regional corresponding with top electrode 126 roughly, and the zone of top electrode 126 needs the zone more than or equal to bottom electrode 122a.Bottom electrode 122a, insulating barrier 124 and 126 formation capacitors 128 of top electrode.
Then consult Fig. 9, form one deck code-pattern expendable insulating layer 130 in anti-reflecting layer 112 and metal capacitor 128 tops.Follow the processing procedure that this expendable insulating layer 130 is carried out planarization, cmp processing procedure for example, make the surface of insulating barrier 130 not be subjected to the influence of the hypsography that the capacitor 128 of its below caused, and become the insulating barrier 130 ' with flat surfaces shown in Figure 10, be beneficial to the carrying out of successive process.
Consult Figure 11,12, then carry out another road double-insert process, form the pattern of dual damascene in insulating barrier 130 ', this pattern is made of groove 134a and 134b and interlayer fenestra 132a and 132b.Wherein, interlayer fenestra 132b can expose the surface of the lead 122b that desires to do electrical contact, and interlayer fenestra 132a can expose the surface of the top electrode 126 of desiring to do electrical contact.
As shown in figure 12, form the barrier layer (not illustrating) of one deck compliance in the surface of insulating barrier 130 ', groove 134a and 134b and interlayer fenestra 132a and 132b.And on barrier layer the deposited copper metal, and insert groove 134a and 134b, and among interlayer fenestra I32a and the 132b.Carry out cmp afterwards,, and in double-mosaic pattern, form copper conductor 138a and 138b and copper connector 136a and 136b with worn unnecessary copper metal and barrier layer.In copper conductor 138a and 138b and insulating barrier 130 ' top covering one deck sealant 140, its material can be silicon nitride or carborundum afterwards.So top electrode 126 electrically connects via copper connector 136a and copper conductor 138a, copper conductor 122b then electrically connects via copper connector 136b and copper conductor 138b.
Follow-up copper wiring is still proceeded, till the manufacturing of finishing whole intraconnections.Because it is a prior art, so do not repeat.
Above-mentioned insulating barrier 102,106,110 and 130 material can be the insulation materials of low-k, for example the spin-coating macromolecule and the chemical vapour deposition (CVD) formula low-k material of doping or unadulterated silica, low-k.
Embodiment 2
Consulting Figure 13-Figure 20, is a kind of method that forms metal capacitor in damascene process in order to explanation preferred embodiment 2 of the present invention.
At first consult Figure 13, on insulating barrier 202, form another layer insulating 206, wherein may comprise other intraconnections in the insulating barrier 202, and insulating barrier 202 belows comprise be formed in the substrate and substrate in element, describe content of the present invention in order to know, the circuit element of these bottoms is also not shown in the diagram.Utilize damascene process in insulating barrier 206, to form copper conductor 204a and the 204b that thickness is about 2000 to 6000 dusts.For example, in insulating barrier 206, behind the formation groove, behind the barrier layer (not illustrating) of formation one deck compliance, insert the copper metal, carry out cmp afterwards, with worn unnecessary copper metal and barrier layer.Then forming sealant 208 at least on copper conductor 204a and 204b, is to be example to form comprehensive sealant 208 in the drawings, and its thickness is about the 100-400 Izod right side, and its material can be silicon nitride (SiN) or carborundum (SiC).
Then, on sealant 208, form insulating barrier 210 and anti-reflecting layer 212 in regular turn.When forming dual-damascene structure, anti-reflecting layer 212 can be used as hard mask; When forming copper conductor, anti-reflecting layer 212 can be used as the grinding stop layer.The material that is used to form anti-reflecting layer 212 can be silicon oxynitride (SiON) or carborundum (SiC).The thickness of anti-reflecting layer 212 is about the 100-600 Izod right side.
In anti-reflecting layer 212, insulating barrier 210 and sealant 208, form double-mosaic pattern, this pattern is made of interlayer fenestra 214a and 214b and groove 216a and 216b, its media layer window hole 214b can expose the surface of copper conductor 204b, and interlayer fenestra 214a can expose the surface of copper conductor 204a.
Then consult Figure 14, at the barrier layer (not illustrating) of anti-reflecting layer 212, interlayer fenestra and 214b and groove 216a and 216b surface formation compliance.Deposited copper metal on barrier layer, and insert among interlayer fenestra 214a and 214b and groove 216a and the 216b.Utilize the cmp processing procedure to remove unnecessary part, and cooperate with anti-reflecting layer 212 as grinding stop layer, the dual-damascene structure that is constituted by copper connector 220a and 220b and copper conductor 222a and 222b with formation.Wherein, copper conductor 222a is the bottom electrode as metal capacitor.
Above-mentioned double-insert process except being used to form copper connector 220a and 220b and copper conductor 222b, also is used to form bottom electrode 222a.Therefore, do not need extra photoetching etch process to form bottom electrode 222a.Moreover bottom electrode 222a is positioned at same plane with copper conductor 222b.
Then in anti-reflecting layer 212 and copper conductor 222a and the last sealant 223 that forms of 222b, its thickness is about the 100-400 Izod right side.This sealant 223 is as diffused barrier layer, to avoid the migration of copper atom; This sealant 223 also can be as etch stop layer when forming top electrode; Also can be used as the insulating layer of capacitor of a part.Its material can be silicon nitride or carborundum.
Continue at the insulating barrier 224 that forms one deck high-k on the sealant 223.And sealant 223 can improve adhesive force between insulating barrier 224 and the bottom electrode 222a at this.Insulating barrier 224 is the insulating layer of capacitor as another part.The thickness of insulating barrier 224 is about the 100-1200 Izod right side, yet actual thickness still needs the application of apparent capacity device and required capacitance thereof and decides.The material of insulating barrier 224 can be silicon nitride, silicon oxynitride, carborundum (SiC), tantalum oxide (TaO
2), zirconia (ZrO
2), hafnium oxide (HfO
2), aluminium oxide (Al
2O
3) or other have the material of high-k.
Consult Figure 15, form metal level 226 on insulating barrier 224, this metal level 226 is that its thickness is about the 100-2000 Izod right side with the top electrode in order to the formation metal capacitor.The material of above-mentioned metal level 226 can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminium, aluminium copper (AlCu) etc.
Then consult Figure 16, definition metal level 226 and insulating barrier 224, to form the insulating layer of capacitor 225 of top electrode 226 and part, its method is for carrying out the photoetching etch process, till the anti-reflecting layer 223 that exposes as etch stop layer.
According to above-mentioned step, when forming metal capacitor 228, only need extra one photoetching etching step.Therefore, the photoetching etching step of making the integrated circuit that includes capacitor 228 can be reduced, manufacturing cost can also be reduced.
Insulating layer of capacitor 225 comprises insulating barrier 224 and sealant 223.The zone of formed bottom electrode 222a is regional corresponding with top electrode 226 roughly, and the capacitance of metal capacitor 228 also is controlled in the overlapping area of bottom electrode 222a and top electrode 226.Bottom electrode 222a, insulating barrier 225 and 226 formation capacitors 228 of top electrode.
Consult Figure 17, form one deck code-pattern expendable insulating layer 230 in sealant 223 and metal capacitor 228 tops.Follow the processing procedure that this expendable insulating layer 230 is carried out planarization, for example the cmp processing procedure makes insulating barrier 230 become the insulating barrier 230 ' with flat surfaces shown in Figure 180, is beneficial to the carrying out of successive process.
Consult Figure 19,20, then carry out another road double-insert process, form the pattern of dual damascene in insulating barrier 230 ' and sealant 223, this pattern is made of groove 234a and 234b and interlayer fenestra 232a and 232b.Wherein, interlayer fenestra 232b can expose the surface of the lead 222b that desires to do electrical contact, and interlayer fenestra 232a can expose the surface of the top electrode 226 of desiring to do electrical contact.
As shown in figure 20, form the barrier layer (not illustrating) of one deck compliance in the surface of insulating barrier 230 ', groove 234a and 234b and interlayer fenestra 232a and 232b.And on barrier layer the deposited copper metal, and insert among groove 234a and 234b and interlayer fenestra 232a and the 232b.Carry out cmp afterwards,, and in double-mosaic pattern, form copper conductor 238a and 238b and copper connector 236a and 236b with worn unnecessary copper metal and barrier layer.In copper conductor 238a and 238b and insulating barrier 230 ' top covering one deck sealant 240, its material can be silicon nitride or carborundum afterwards.So top electrode 226 electrically connects via copper connector 236a and copper conductor 238a, copper conductor 222b then electrically connects via copper connector 236b and copper conductor 238b.
Follow-up copper wiring is still proceeded, till the manufacturing of finishing whole intraconnections.
Above-mentioned insulating barrier 202,206,210 and 230 material can be the spin-coating macromolecule of insulation material (for example mix or unadulterated silica), low-k of low-k and chemical vapour deposition (CVD) formula low-k material etc.
Though the present invention discloses as above with preferred embodiment, so it is not in order to restriction the present invention, anyly has the knack of this skill person, and without departing from the spirit and scope of the present invention, institute does and changes and retouching, all belongs within protection scope of the present invention.
Claims (12)
1, a kind of method that forms metal capacitor in damascene process is characterized in that: which comprises at least following steps:
(1) provides one first insulating barrier;
(2) in this first insulating barrier, form one first copper conductor and one second copper conductor;
(3) form one first sealant on this first and second copper conductor to being less than;
(4) on this first sealant, form one second insulating barrier;
(5) on this second insulating barrier, form an anti-reflecting layer;
(6) in this anti-reflecting layer, second insulating barrier and first sealant, form the dual-damascene structure that comprises the first bronze medal connector, one second bronze medal connector, one the 3rd copper conductor and the 4th copper conductor, wherein this first bronze medal connector is in order to connect the 3rd copper conductor and first copper conductor, and this second bronze medal connector is in order to connect the 4th copper conductor and second copper conductor;
(7) on this anti-reflecting layer, the 3rd copper conductor and the 4th copper conductor, form one the 3rd insulating barrier;
(8) on the 3rd insulating barrier, form a metal level;
(9) in this anti-reflecting layer as an etch stop layer, with this metal level and the 3rd insulating layer patternization, with in forming a top electrode and an insulating layer of capacitor corresponding to the 3rd copper conductor place;
(10) on this anti-reflecting layer and this top electrode, form one the 4th insulating barrier;
(11) in the 4th insulating barrier, form the dual-damascene structure that comprises the 3rd bronze medal connector, the 4th bronze medal connector, the 5th copper conductor and the 6th copper conductor, wherein the 3rd bronze medal connector is in order to connect the 5th copper conductor and top electrode, and the 4th bronze medal connector is in order to connect the 6th copper conductor and the 4th copper conductor;
(12) form one second sealant on the 5th and the 6th copper conductor to being less than.
2, the method that forms metal capacitor in damascene process according to claim 1 is characterized in that: the material of this anti-reflecting layer is to select at least a in silicon oxynitride or carborundum.
3, the method that forms metal capacitor in damascene process according to claim 1 is characterized in that: the material of the 3rd insulating barrier is to select at least a in silicon nitride, silicon oxynitride, carborundum, tantalum oxide, zirconia, hafnium oxide or aluminium oxide.
4, the method that forms metal capacitor in damascene process according to claim 1, it is characterized in that: the thickness of the 3rd insulating barrier is between 100 dust to 1200 dusts.
5, the method that forms metal capacitor in damascene process according to claim 1 is characterized in that: the material of this metal level is to select at least a in titanium, titanium nitride, tantalum, tantalum nitride, aluminium or aluminium copper.
6, the method that forms metal capacitor in damascene process according to claim 1, it is characterized in that: this metal layer thickness is between 100 dust to 2000 dusts.
7, a kind of method that forms metal capacitor in damascene process is characterized in that: which comprises at least following steps:
(1) provides one first insulating barrier;
(2) in this first insulating barrier, form one first copper conductor and one second copper conductor;
(3) form one first sealant on this first and second copper conductor to being less than;
(4) on this first sealant, form one second insulating barrier;
(5) on this second insulating barrier, form an anti-reflecting layer;
(6) in this anti-reflecting layer, second insulating barrier and first sealant, form the dual-damascene structure that comprises the first bronze medal connector, the second bronze medal connector, the 3rd copper conductor and the 4th copper conductor, wherein this first bronze medal connector is in order to connect the 3rd copper conductor and first copper conductor, and this second bronze medal connector is in order to connect the 4th copper conductor and second copper conductor;
(7) on this anti-reflecting layer, the 3rd copper conductor and the 4th copper conductor, form one second sealant;
(8) on this second sealant, form the 3rd insulating barrier;
(9) on the 3rd insulating barrier, form a metal level;
(10) on this second sealant as an etch stop layer, with this metal level and the 3rd insulating layer patternization, with in forming a top electrode and an insulating layer of capacitor corresponding to the 3rd copper conductor place, wherein the part of this second sealant is also as this insulating layer of capacitor;
(11) on this second sealant and this top electrode, form one the 4th insulating barrier;
(12) in the 4th insulating barrier and this second sealant, form the dual-damascene structure that comprises the 3rd bronze medal connector, the 4th bronze medal connector, the 5th copper conductor and the 6th copper conductor, wherein the 3rd bronze medal connector is in order to connect the 5th copper conductor and top electrode, and the 4th bronze medal connector is in order to connect the 6th copper conductor and the 4th copper conductor;
(13) form one the 3rd sealant on the 5th and the 6th copper conductor to being less than.
8, the method that forms metal capacitor in damascene process according to claim 7 is characterized in that: the material of this anti-reflecting layer is to select at least a in silicon oxynitride or carborundum.
9, the method that forms metal capacitor in damascene process according to claim 7 is characterized in that: the material of the 3rd insulating barrier is to select at least a in silicon nitride, silicon oxynitride, carborundum, tantalum oxide, zirconia, hafnium oxide or aluminium oxide.
10, the method that forms metal capacitor in damascene process according to claim 7, it is characterized in that: the thickness of the 3rd insulating barrier is between 100 dust to 1200 dusts.
11, the method that forms metal capacitor in damascene process according to claim 7 is characterized in that: the material of this metal level is to select at least a in titanium, titanium nitride, tantalum, tantalum nitride, aluminium or aluminium copper.
12, the method that forms metal capacitor in damascene process according to claim 7, it is characterized in that: this metal layer thickness is between 100 dust to 2000 dusts.
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| CN105720039A (en) * | 2014-12-04 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and forming method therefor |
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|---|---|---|---|---|
| US7960838B2 (en) | 2005-11-18 | 2011-06-14 | United Microelectronics Corp. | Interconnect structure |
| US7365009B2 (en) | 2006-01-04 | 2008-04-29 | United Microelectronics Corp. | Structure of metal interconnect and fabrication method thereof |
| CN102420103B (en) * | 2011-05-26 | 2013-09-11 | 上海华力微电子有限公司 | Copper Damascus process MIM (metal-insulator-metal) capacitor structure and manufacturing process |
| CN111199953B (en) | 2018-11-16 | 2022-04-08 | 无锡华润上华科技有限公司 | MIM capacitor and manufacturing method thereof |
-
2001
- 2001-08-22 CN CN 01130733 patent/CN1237598C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105720039A (en) * | 2014-12-04 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and forming method therefor |
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|---|---|
| CN1402325A (en) | 2003-03-12 |
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