CN102420103B - Copper Damascus process MIM (metal-insulator-metal) capacitor structure and manufacturing process - Google Patents
Copper Damascus process MIM (metal-insulator-metal) capacitor structure and manufacturing process Download PDFInfo
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- CN102420103B CN102420103B CN 201110138154 CN201110138154A CN102420103B CN 102420103 B CN102420103 B CN 102420103B CN 201110138154 CN201110138154 CN 201110138154 CN 201110138154 A CN201110138154 A CN 201110138154A CN 102420103 B CN102420103 B CN 102420103B
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Abstract
The invention relates to a copper Damascus process MIM (metal-insulator-metal) capacitor structure and a manufacturing process thereof. The structure is characterized that through adding two maskplates, a single Damascus process is used so as to manufacture an MIM capacitor and an inductor simultaneously. According to the technical scheme of the invention, the manufactured MIM double-layer capacitor structure can be completely compatible with a CMOS (complementary metal-oxide-semiconductor transistor) logic circuit and an inductive copper Damascus process, and the density of the MIN capacitor is increased.
Description
Technical field
The present invention relates to a kind of copper Damascus technics, relate in particular to a kind of copper Damascus technics metal-insulator-metal (Metal-Insulator-Metal is called for short MIM) capacitance structure and manufacture method.
Background technology
Along with reducing of feature sizes of semiconductor devices, the semiconductor rear section copper wiring replaces aluminum manufacturing procedure becomes main flow technology.In mixed signal and radio circuit, exploitation mim capacitor structure and the manufacturing process of the copper Damascus technics of CMOS compatible logical circuit and inductance fully necessitates.This has not only improved the complexity of technology; And use low resistance copper can improve the MIM capacitive property as battery lead plate.
Patent US6329234, structure and the technological process of process for copper CMOS compatible metal dielectric layer metal capacitor, its technical scheme that adopts is to make individual layer Damascus MIM electric capacity in double damask structure.
Patent US6670237, structure and the technological process of process for copper CMOS compatible metal dielectric layer metal capacitor, its technical scheme that adopts is to make individual layer Damascus MIM electric capacity in the through-hole structure of single Damascus.
And along with the reducing of semiconductor dimensions, must reduce the MIM capacity area.This just requires to increase capacitance density.
Double-deck mim capacitor structure and copper Damascus manufacturing process that the present invention proposes, the MIM of the copper Damascus technics of CMOS compatible logical circuit and inductance, and increase fully capacitance density.
Summary of the invention
The invention discloses a kind of copper Damascus technics metal-insulating layer-metal capacitor structure and manufacture method, fully CMOS compatible logical circuit and inductance the copper Damascus technics, and increase the MIM capacitance density.
Above-mentioned purpose of the present invention is achieved through the following technical solutions:
A kind of copper Damascus technics metal-insulating layer-metal capacitor manufacture method, wherein,
Deposit one matrix dielectric layer forms first electrode trenches and metal interconnected line trenches by Damascus technics at matrix, and makes first electrode and metal interconnecting wires;
Deposit first dielectric barrier layer and first dielectric layer successively on the matrix dielectric layer;
Etching first dielectric layer, first dielectric barrier layer form second electrode trenches, make the bottom of described second electrode trenches contact described first electrode;
Deposit forms first insulating barrier, makes described first insulating barrier cover described first dielectric layer and described second electrode trenches;
Form through hole by photoetching and etching, make described through hole pass described first insulating barrier, described first dielectric layer and described first dielectric barrier layer, contact described metal interconnecting wires;
At through hole and be coated with that deposit forms metal barrier and copper seed layer in second electrode trenches of first insulating barrier, and fill metallic copper, carry out the cmp planarization afterwards, to remove excess metal, form second electrode and through hole line;
Deposit second dielectric barrier layer and second dielectric layer on described first dielectric layer successively;
Etching second dielectric layer, second dielectric barrier layer form the third electrode groove, make the bottom of described third electrode groove contact described second electrode;
Deposit forms second insulating barrier, makes described second insulating barrier cover described second dielectric layer and described third electrode groove;
Etching second insulating barrier, second dielectric layer, second dielectric barrier layer form the first line groove and the second line groove, make the described first line groove pass described second insulating barrier, described second dielectric layer and described second dielectric barrier layer, contact described through hole line; Make the described second line groove pass described second insulating barrier, described second dielectric layer and described second dielectric barrier layer, contact described second electrode;
At the first line groove, the second line groove and be coated with that deposit forms metal barrier and copper seed layer in the third electrode groove of second insulating barrier, fill metallic copper, and carry out the cmp planarization, to remove excess metal, form third electrode, the first groove line and the second groove line.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacture method, wherein, described Damascus technics is specially: by photoetching be etched on the matrix dielectric layer and form first electrode trenches and metal interconnected line trenches, depositing metal barrier layer and copper seed layer; In first electrode trenches and metal interconnected line trenches, fill metallic copper; The cmp planarization to remove excess metal, forms first electrode and metal interconnecting wires.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacture method, wherein, form described matrix dielectric layer, described first dielectric layer, described second dielectric layer, described first dielectric barrier layer and described second dielectric barrier layer by chemical vapor deposition.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacture method, wherein, the material of the described matrix dielectric layer of deposit, described first dielectric layer and described second dielectric layer is chosen from SiO2, SiOCH, FSG etc.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacture method, wherein, described first dielectric barrier layer of deposit and described second dielectric barrier layer material are chosen from SiN, SiCN etc.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacture method wherein, forms described metal barrier and copper seed layer by physical vapor deposition.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacture method, wherein, the material of the described metal barrier of deposit is TaN or Ta.
The manufacture method of aforesaid copper Damascus technics metal-insulating layer-metal capacitor, wherein, by the copper the prevented diffusion dielectric layer of chemical vapor deposition or atomic layer deposition guarantor type, to form described first insulating barrier and described second insulating barrier.
The manufacture method of aforesaid copper Damascus technics metal-insulating layer-metal capacitor wherein, can prevent that copper diffusion dielectric layer often adopts silicon nitride.
The manufacture method of aforesaid copper Damascus technics metal-insulating layer-metal capacitor wherein, all is deposited with the high sacrificing protection layer of one deck etching selection ratio, to avoid successive process to the damage of insulating barrier on described first insulating barrier and described second insulating barrier.
The manufacture method of aforesaid copper Damascus technics metal-insulating layer-metal capacitor, wherein, the sacrificing protection layer that will be deposited on respectively before carrying out the physical vapor deposition metal barrier on described first insulating barrier and described second insulating barrier is removed.
The manufacture method of aforesaid copper Damascus technics metal-insulating layer-metal capacitor, wherein, by the double-deck dielectric layer of chemical vapor deposition or atomic layer deposition to form described first insulating barrier and described second insulating barrier.
The manufacture method of aforesaid copper Damascus technics metal-insulating layer-metal capacitor wherein, is used SiN layer and SiO2 layer institute as double-deck dielectric layer, or is used SiN layer and high dielectric constant material layer as double-deck dielectric layer.
The manufacture method of aforesaid copper Damascus technics metal-insulating layer-metal capacitor, wherein, described high dielectric constant material adopts HfO, ZrO, AlO, LaO etc.
A kind of structure of copper Damascus technics metal-insulating layer-metal capacitor, wherein,
Be coated with a matrix dielectric layer in one substrate, the upper surface of described matrix dielectric layer is provided with first electrode trenches and metal interconnected line trenches, described first electrode trenches and described metal interconnecting wires grooved inner surface all are coated with metal barrier, and fill metallic copper in described first electrode trenches and the described metal interconnected line trenches, respectively as first electrode and metal interconnecting wires;
Be provided with one first dielectric barrier layer and one first dielectric layer on the described matrix dielectric layer successively, offer second electrode trenches and through hole on described first dielectric layer, described second electrode trenches passes described first dielectric layer and described first dielectric barrier layer terminates in described first electrode, described through hole passes described first dielectric layer and described first dielectric barrier layer terminates in described metal interconnecting wires, the described second electrode trenches inner surface is coated with one first insulating barrier and metal barrier successively, and to be filled with metallic copper in described second electrode trenches be second electrode; Described through-hole wall and bottom are provided with metal barrier, and all to be filled with metallic copper in the described through hole be the through hole line;
Be provided with one second dielectric barrier layer and one second dielectric layer on described first dielectric layer successively, described second dielectric layer is provided with third electrode groove, the first line groove and the second line groove, described third electrode groove passes described second dielectric layer and described second dielectric barrier layer terminates in described second electrode, the described first line groove passes described second dielectric layer and described second dielectric barrier layer terminates in described through hole line, and the described second line groove passes described second dielectric layer and described second dielectric barrier layer terminates in described second electrode; Described third electrode grooved inner surface is coated with one second insulating barrier and metal barrier successively, and to be filled with metallic copper in the described third electrode groove be third electrode; The described first line grooved inner surface is coated with metal barrier, and to be filled with metallic copper in the described first line groove be the first groove line; The described second line trench wall is coated with metal barrier, and to be filled with metallic copper in the described second line groove be the second groove line.
In sum, owing to adopted technique scheme, structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention, by adding two mask plates, use single Damascus technics to make metal-insulating layer-metal capacitor and inductance simultaneously, make the metal-insulator-metal double layer capacity structure produced by technical scheme of the present invention fully CMOS compatible logical circuit and inductance the copper Damascus technics, and increase metal-insulating layer-metal capacitor density.
Description of drawings
Fig. 1 is structure and formation first electrode of manufacturing process and the structural representation behind the metal interconnecting wires of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Fig. 2 is structure and deposit first dielectric barrier layer of manufacturing process and the structural representation behind first dielectric layer of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Fig. 3 is the structural representation after the photoetching of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof and etching form second electrode trenches;
Fig. 4 is the structural representation after the deposit of finishing first insulating barrier of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof;
Fig. 5 is structure and the photoetching of manufacturing process and the structural representation behind the etching formation through hole of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Fig. 6 is structure and formation second electrode of manufacturing process and the structural representation behind the through hole line of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Fig. 7 is the structural representation after the deposit of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof forms second dielectric barrier layer and second dielectric layer;
Fig. 8 is structure and the photoetching of manufacturing process and the structural representation behind the etching formation third electrode groove of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Fig. 9 is the structural representation after the deposit of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof forms second insulating barrier;
Figure 10 is the structural representation after the photoetching of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof and etching form the first line groove and the second line groove;
Figure 11 is the structural representation behind the formation third electrode, the first groove line, the second groove line of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof;
Figure 12 is the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and the circuit diagram of manufacturing process thereof.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is further described:
A kind of copper Damascus technics metal-insulating layer-metal capacitor manufacture method, wherein,
Fig. 1 is structure and formation first electrode of manufacturing process and the structural representation behind the metal interconnecting wires of copper Damascus technics metal-insulating layer-metal capacitor of the present invention, see also Fig. 1, form first electrode trenches 3011 and metal interconnected line trenches 4011 by Damascus technics chemical wet etching on matrix dielectric layer 101, depositing metal barrier layer 801 and copper seed layer, electroplate and fill metallic copper, excess metal is removed in the cmp planarization, makes first electrode 301 and metal interconnecting wires 401;
Fig. 2 is structure and deposit first dielectric barrier layer of manufacturing process and the structural representation behind first dielectric layer of copper Damascus technics metal-insulating layer-metal capacitor of the present invention, see also Fig. 2, deposit first dielectric barrier layer 201 and first dielectric layer 102 successively on matrix dielectric layer 101, because first electrode 301 and metal interconnecting wires 401 all are formed in the matrix dielectric layer 101, so first dielectric barrier layer covers first electrode 301 and metal interconnecting wires 401 fully;
Fig. 3 is the structural representation after the photoetching of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof and etching form second electrode trenches, see also Fig. 3, the spin coating photoresist, form the figure of described second electrode 302 by photoetching, etching first dielectric layer 102, first dielectric barrier layer 201 afterwards, to form second electrode trenches 3021, open first dielectric barrier layer 201, make the bottom of described second electrode trenches 3021 contact described first electrode 301, described second electrode trenches, 3021 parts are positioned at first electrode, 301 tops;
Fig. 4 is the structural representation after the deposit of finishing first insulating barrier of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof, see also Fig. 4, deposit forms first insulating barrier 3022, make described first insulating barrier 3022 cover described first dielectric layer 102 and described second electrode trenches 3021, that is to say that first insulating barrier 3022 covers the upper surface of first dielectric layer 102 and the inwall of second electrode trenches 3021;
Fig. 5 is structure and the photoetching of manufacturing process and the structural representation behind the etching formation through hole of copper Damascus technics metal-insulating layer-metal capacitor of the present invention, see also Fig. 5, form through hole 4021 by photoetching and etching, make described through hole 4021 pass described first insulating barrier 3022, described first dielectric layer 102 and described first dielectric barrier layer 201, contact described metal interconnecting wires 401, that is to say and in etching process, open first insulating barrier 3022, first dielectric layer 102 and described first dielectric barrier layer 201;
Fig. 6 is structure and formation second electrode of manufacturing process and the structural representation behind the through hole line of copper Damascus technics metal-insulating layer-metal capacitor of the present invention, see also Fig. 6, at through hole and be coated with depositing metal barrier layer 801 and copper seed layer in second electrode trenches 3021 of first insulating barrier 3022, fill metallic copper (ECP), excess metal is removed in cmp (CMP) planarization, to form second electrode 302 and through hole line 402, in the process of depositing metal barrier layer 801 and copper seed layer and plated metal copper, metal barrier 801 and metallic copper can cover first dielectric layer 102 above, can directly the metallic copper and the metal barrier 801 that cover above first dielectric layer 102 be removed by carrying out the chemical grinding planarization, first insulating barrier 3022 of same first dielectric layer, 102 upper surfaces also can be removed in process of lapping;
Fig. 7 is the structural representation after the deposit of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof forms second dielectric barrier layer and second dielectric layer, see also Fig. 7, deposit second dielectric barrier layer 202 and second dielectric layer 103 on described first dielectric layer 102 successively, wherein, because second electrode 302 and through hole line 402 all are formed on first dielectric layer 102, second dielectric barrier layer 202 and second dielectric layer 103 cover on second electrode 302 and the through hole line 402 simultaneously;
Fig. 8 is structure and the photoetching of manufacturing process and the structural representation behind the etching formation third electrode groove of copper Damascus technics metal-insulating layer-metal capacitor of the present invention, see also Fig. 8, spin coating photoresist on second dielectric layer 103, form the figure of third electrode 303 by photoetching, etching second dielectric layer 103 afterwards, second dielectric barrier layer 202, to form third electrode groove 3031, open second dielectric barrier layer 202, make the bottom of described third electrode groove 3031 contact described second electrode 302, third electrode groove 3031 is positioned at the top of second electrode 302, is connected with second electrode 302;
Fig. 9 is the structural representation after the deposit of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof forms second insulating barrier, see also Fig. 9, deposit forms second insulating barrier 3032, make described second insulating barrier 3032 cover described second dielectric layer 103 and described third electrode groove 3031, that is to say that second insulating barrier 3032 of deposit has covered the upper surface of second dielectric layer 103 and the inwall of third electrode groove 3031;
Figure 10 is the structural representation after the photoetching of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof and etching form the first line groove and the second line groove, see also Figure 10, form the first line groove 4031 and the second line groove 5011 by photoetching and etching, it is etching second insulating barrier 3032, second dielectric layer 103, second dielectric barrier layer 202, form the first line groove 4031 and the second line groove 5011, make the described first line groove 4031 pass described second insulating barrier 3032, described second dielectric layer 103 and described second dielectric barrier layer 202, contact described through hole line 402, make the described second line groove 5011 pass described second insulating barrier 3032, described second dielectric layer 103 and described second dielectric barrier layer 202, contact described second electrode 302, that is to say, in one embodiment of the invention, open second insulating barrier 3032 in the etching process, second dielectric layer 103 and second dielectric barrier layer 202, first electrode trenches, 4031 bottoms are communicated with through hole line 402, and the second line groove, 5011 bottoms are connected with second electrode 302;
Figure 11 is the formation third electrode of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention, the first groove line, structural representation behind the second groove line, see also Figure 11, at the first line groove 4031, the second line groove 5011 and be coated with depositing metal barrier layer 801 and copper seed layer in the third electrode groove 3031 of second insulating barrier 3032, electroplate afterwards and fill metallic copper, excess metal is removed in the cmp planarization, to form third electrode 303, the first groove line 403 and the second groove line 501, in the process of depositing metal barrier layer 801 and copper seed layer and plated metal copper, metal barrier 801 and metallic copper can cover second dielectric layer 103 above, can directly the metallic copper and the metal barrier 801 that cover above second dielectric layer 103 be removed by carrying out the cmp planarization, equally, second insulating barrier 3032 of second dielectric layer, 103 upper surfaces also can be removed simultaneously.
Form described matrix dielectric layer 101, described first dielectric layer 102, described second dielectric layer 103, described first dielectric barrier layer 201 and described second dielectric barrier layer 202 by chemical vapor deposition (CVD) among the present invention.
The material of the described matrix dielectric layer 101 of deposit, first dielectric layer 102 and described second dielectric layer 103 is chosen from SiO2, SiOCH, FSG etc. among the present invention.
Described first dielectric barrier layer 201 of deposit and described second dielectric barrier layer, 202 materials are chosen from SiN, SiCN etc. among the present invention.
Form described metal barrier 801 and copper seed layer by physical vapor deposition (PVD) among the present invention.
The material of the described metal barrier of deposit is TaN or Ta among the present invention.
The copper prevented by chemical vapor deposition or atomic layer deposition guarantor type among the present invention spreads dielectric layer, to form described first insulating barrier 3022 and described second insulating barrier 3032.
Can prevent described in the present invention that copper diffusion dielectric layer often adopts the silicon nitride of guarantor's type.
Make described first electrode trenches 3011 identical with the degree of depth of described metal interconnected line trenches 4011 among the present invention in the etching process, so that the thickness of the thickness of described first electrode 301 and described metal interconnecting wires 401 is suitable.
Make described second electrode trenches 3021 identical with described through hole 4021 degree of depth among the present invention in the etching process, so that the height of the thickness of described second electrode 302 and described through hole line 402 is suitable.
Be that described third electrode groove 3031 is identical with the degree of depth of the described first line groove 4031 and the second line groove 5011 in the etching process among the present invention, so that the thickness of the thickness of described third electrode 303 and the described first groove line 403 and the second groove line 501 is suitable.
All be deposited with the high sacrificing protection layer of one deck etching selection ratio on first insulating barrier 3022 and described second insulating barrier 3032 described in the present invention, to avoid successive process to the damage of insulating barrier.
To be deposited on described first insulating barrier 3022 among the present invention before carrying out physical vapor deposition metal barrier 801 respectively removes with the sacrificing protection layer on described second insulating barrier 3032.
Among the present invention by the double-deck dielectric layer of chemical vapor deposition or atomic layer deposition to form described first insulating barrier 3022 and described second insulating barrier 3032.
Use SiN layer and SiO2 layer institute as double-deck dielectric layer among the present invention, or use SiN layer and high dielectric constant material layer as double-deck dielectric layer.
High dielectric constant material described in the present invention adopts HfO, ZrO, AlO, LaO etc.
Figure 11 is the structural representation behind the formation third electrode, the first groove line, the second groove line of the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and manufacturing process thereof, see also Figure 11, a kind of structure of copper Damascus technics metal-insulating layer-metal capacitor, wherein
Be coated with a matrix dielectric layer 101 in one substrate, the upper surface of described matrix dielectric layer 101 is provided with first electrode trenches 3011 and metal interconnected line trenches 4011, the degree of depth of first electrode trenches 3011 is identical with the degree of depth of metal interconnected line trenches 4011, described first electrode trenches 3011 and described metal interconnected line trenches 4011 inner surfaces all are coated with metal barrier 801, and be filled with metallic copper in described first electrode trenches 3011 and the described metal interconnected line trenches 4011, respectively as first electrode 301 and metal interconnecting wires 401, wherein, the thickness of the thickness of first electrode 301 and described metal interconnecting wires 401 is suitable;
Be provided with one first dielectric barrier layer 201 and one first dielectric layer 102 on the described matrix dielectric layer 101 successively, offer second electrode trenches 3021 and through hole 4021 on described first dielectric layer 102, described second electrode trenches 3021 passes described first dielectric layer 102 and described first dielectric barrier layer 201 terminates in described first electrode 301, described through hole 4021 passes described first dielectric layer 102 and described first dielectric barrier layer 201 terminates in described metal interconnecting wires 401, the degree of depth of second electrode trenches 3021 is identical with the degree of depth of through hole 4021, described second electrode trenches, 3021 inner surfaces are coated with one first insulating barrier 3022 and metal barrier 801 successively, and to be filled with metallic copper in described second electrode trenches 3021 be second electrode 302; Described through hole 4021 inwalls and bottom are provided with metal barrier 801, and to be filled with metallic copper in the described through hole 4021 be through hole line 402, and wherein, the height of the thickness of second electrode 302 and through hole line 402 is suitable;
Be provided with one second dielectric barrier layer 202 and one second dielectric layer 103 on described first dielectric layer 102 successively, described second dielectric layer 103 is provided with third electrode groove 3031 and the first line groove 4031 and the second line groove 5011, described third electrode groove 3031 passes described second dielectric layer 103 and described second dielectric barrier layer 202 terminates in described second electrode 302, the described first line groove 4031 passes described second dielectric layer 103 and described second dielectric barrier layer 202 terminates in described through hole line 402, the described second line groove 5011 passes described second dielectric layer 103 and described second dielectric barrier layer 202 terminates in described second electrode 302, the degree of depth of the first line groove 4031 and the second line groove 5011 is identical with the degree of depth of third electrode groove 3031, described third electrode groove 3031 inner surfaces are coated with one second insulating barrier 3032 successively, metal barrier 801, and to be filled with metallic copper in the described third electrode groove 3031 be third electrode 303; The described first line groove 4031 and the second line groove, 5011 inner surfaces are coated with metal barrier 801, and be filled with metallic copper in the described first line groove 4031 and the second line groove 5011 and be respectively the first groove line 403 and the second groove line 501, wherein, the thickness of third electrode 303 and the first groove line 403 are suitable with the second groove line, 501 thickness.
Figure 12 is the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and the circuit diagram of manufacturing process thereof, see also Figure 12, produce metal-insulating layer-metal capacitor by technology provided by the invention and structure, the electric capacity that forms has two, be provided with an electric capacity between first electrode and second electrode, be provided with an electric capacity equally between third electrode and second electrode.
Structure disclosed in this invention and processing step are to make multiple layer metal-insulating barrier-metal capacitance in the single-layer metal layer, certainly the present invention is not limited only to single-layer metal, and the method disclosed in the present and structure are applicable to too makes more multi-layered metal-insulating layer-metal capacitor in the multiple layer metal.
In sum, owing to adopted technique scheme, structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention, by adding two mask plates, use single Damascus technics to make metal-insulating layer-metal capacitor and inductance simultaneously, make the metal-insulator-metal double layer capacity structure produced by technical scheme of the present invention fully CMOS compatible logical circuit and inductance the copper Damascus technics, and increase metal-insulating layer-metal capacitor density.
More than specific embodiments of the invention are described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and substituting also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of doing under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (15)
1. a method of utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor is characterized in that,
Deposit one matrix dielectric layer forms first electrode trenches and metal interconnected line trenches by Damascus technics at matrix, and makes first electrode and metal interconnecting wires;
Deposit first dielectric barrier layer and first dielectric layer successively on the matrix dielectric layer;
Etching first dielectric layer, first dielectric barrier layer form second electrode trenches, make the bottom of described second electrode trenches contact described first electrode;
Deposit forms first insulating barrier, makes described first insulating barrier cover described first dielectric layer and described second electrode trenches;
Form through hole by photoetching and etching, make described through hole pass described first insulating barrier, described first dielectric layer and described first dielectric barrier layer, connect described metal interconnecting wires;
At through hole and be coated with that deposit forms metal barrier and copper seed layer in second electrode trenches of first insulating barrier, and fill metallic copper, carry out the cmp planarization afterwards, to remove excess metal, form second electrode and through hole line;
Deposit second dielectric barrier layer and second dielectric layer on described first dielectric layer successively;
Etching second dielectric layer, second dielectric barrier layer form the third electrode groove, make the bottom of described third electrode groove contact described second electrode;
Deposit forms second insulating barrier, makes described second insulating barrier cover described second dielectric layer and described third electrode groove;
Etching second insulating barrier, second dielectric layer, second dielectric barrier layer form the first line groove and the second line groove, make the described first line groove pass described second insulating barrier, described second dielectric layer and described second dielectric barrier layer, contact described through hole line; Make the described second line groove pass described second insulating barrier, described second dielectric layer and described second dielectric barrier layer, contact described second electrode;
At the first line groove, the second line groove and be coated with that deposit forms metal barrier and copper seed layer in the third electrode groove of second insulating barrier, fill metallic copper, and carry out the cmp planarization, to remove excess metal, form third electrode, the first groove line and the second groove line.
2. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 1, it is characterized in that, described Damascus technics is specially: by photoetching be etched on the matrix dielectric layer and form first electrode trenches and metal interconnected line trenches, depositing metal barrier layer and copper seed layer; In first electrode trenches and metal interconnected line trenches, fill metallic copper; The cmp planarization to remove excess metal, forms first electrode and metal interconnecting wires.
3. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 1, it is characterized in that, form described matrix dielectric layer, described first dielectric layer, described second dielectric layer, described first dielectric barrier layer and described second dielectric barrier layer by chemical vapor deposition.
4. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 1, it is characterized in that the material of the described matrix dielectric layer of deposit, described first dielectric layer and described second dielectric layer is chosen from SiO2, SiOCH, FSG.
5. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 1 is characterized in that described first dielectric barrier layer of deposit and described second dielectric barrier layer material are chosen from SiN, SiCN.
6. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 1 is characterized in that, forms described metal barrier and copper seed layer by physical vapor deposition.
7. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 1 is characterized in that the described metal barrier layer material of deposit is TaN or Ta.
8. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 1, it is characterized in that, by the copper the prevented diffusion dielectric layer of chemical vapor deposition or atomic layer deposition conformal, to form described first insulating barrier and described second insulating barrier.
9. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 8 is characterized in that, describedly prevents that copper diffusion dielectric layer adopts silicon nitride.
10. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 1; it is characterized in that; all be deposited with the high sacrificing protection layer of one deck etching selection ratio on described first insulating barrier and described second insulating barrier, to avoid successive process to the damage of insulating barrier.
11. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 10; it is characterized in that the sacrificing protection layer that will be deposited on respectively on described first insulating barrier and described second insulating barrier is removed before carrying out the physical vapor deposition metal barrier.
12. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 1 is characterized in that, by chemical vapor deposition or the double-deck dielectric layer of atomic layer deposition to form described first insulating barrier and described second insulating barrier.
13. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 12, it is characterized in that, use SiN layer and SiO2 layer as double-deck dielectric layer, or use SiN layer and high dielectric constant material layer as double-deck dielectric layer.
14. the method for utilizing the copper Damascus technics to make metal-insulating layer-metal capacitor according to claim 13 is characterized in that described high dielectric constant material adopts HfO, ZrO, AlO or LaO.
15. a metal-insulating layer-metal capacitor structure of utilizing the copper Damascus technics to make is characterized in that,
Be coated with a matrix dielectric layer in one substrate, the upper surface of described matrix dielectric layer is provided with first electrode trenches and metal interconnected line trenches, described first electrode trenches and described metal interconnecting wires grooved inner surface all are coated with metal barrier, and fill metallic copper in described first electrode trenches and the described metal interconnected line trenches, respectively as first electrode and metal interconnecting wires;
Be provided with one first dielectric barrier layer and one first dielectric layer on the described matrix dielectric layer successively, offer second electrode trenches and through hole on described first dielectric layer, described second electrode trenches passes described first dielectric layer and described first dielectric barrier layer terminates in described first electrode, described through hole passes described first dielectric layer and described first dielectric barrier layer terminates in described metal interconnecting wires, the described second electrode trenches inner surface is coated with one first insulating barrier and metal barrier successively, and to be filled with metallic copper in described second electrode trenches be second electrode; Described through-hole wall and bottom are provided with metal barrier, and all to be filled with metallic copper in the described through hole be the through hole line;
Be provided with one second dielectric barrier layer and one second dielectric layer on described first dielectric layer successively, described second dielectric layer is provided with third electrode groove, the first line groove and the second line groove, described third electrode groove passes described second dielectric layer and described second dielectric barrier layer terminates in described second electrode, the described first line groove passes described second dielectric layer and described second dielectric barrier layer terminates in described through hole line, and the described second line groove passes described second dielectric layer and described second dielectric barrier layer terminates in described second electrode; Described third electrode grooved inner surface is coated with one second insulating barrier and metal barrier successively, and to be filled with metallic copper in the described third electrode groove be third electrode; The described first line grooved inner surface is coated with metal barrier, and to be filled with metallic copper in the described first line groove be the first groove line; The described second line trench wall is coated with metal barrier, and to be filled with metallic copper in the described second line groove be the second groove line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110138154 CN102420103B (en) | 2011-05-26 | 2011-05-26 | Copper Damascus process MIM (metal-insulator-metal) capacitor structure and manufacturing process |
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| US10128327B2 (en) * | 2014-04-30 | 2018-11-13 | Stmicroelectronics, Inc. | DRAM interconnect structure having ferroelectric capacitors exhibiting negative capacitance |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1402325A (en) * | 2001-08-22 | 2003-03-12 | 矽统科技股份有限公司 | Method for forming metal capacitor in inlaying mfg. process |
| US6709918B1 (en) * | 2002-12-02 | 2004-03-23 | Chartered Semiconductor Manufacturing Ltd. | Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology |
| CN1624894A (en) * | 2003-12-05 | 2005-06-08 | 中芯国际集成电路制造(上海)有限公司 | Laminated method insulator metal capacitor and manufacturing method thereof |
| CN101160661A (en) * | 2003-09-30 | 2008-04-09 | 国际商业机器公司 | Metal-insulator-metal capacitor and method of fabrication |
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| US7169680B2 (en) * | 2005-02-24 | 2007-01-30 | United Microelectronics Corp. | Method for fabricating a metal-insulator-metal capacitor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1402325A (en) * | 2001-08-22 | 2003-03-12 | 矽统科技股份有限公司 | Method for forming metal capacitor in inlaying mfg. process |
| US6709918B1 (en) * | 2002-12-02 | 2004-03-23 | Chartered Semiconductor Manufacturing Ltd. | Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology |
| CN101160661A (en) * | 2003-09-30 | 2008-04-09 | 国际商业机器公司 | Metal-insulator-metal capacitor and method of fabrication |
| CN1624894A (en) * | 2003-12-05 | 2005-06-08 | 中芯国际集成电路制造(上海)有限公司 | Laminated method insulator metal capacitor and manufacturing method thereof |
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