CN100539016C - MIM capacitor and manufacture method thereof - Google Patents
MIM capacitor and manufacture method thereof Download PDFInfo
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- CN100539016C CN100539016C CNB2007100402368A CN200710040236A CN100539016C CN 100539016 C CN100539016 C CN 100539016C CN B2007100402368 A CNB2007100402368 A CN B2007100402368A CN 200710040236 A CN200710040236 A CN 200710040236A CN 100539016 C CN100539016 C CN 100539016C
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Abstract
The invention provides a kind of manufacture method of MIM capacitor, comprising: the interconnection structure surface in Semiconductor substrate forms first passivation layer; The described passivation layer of patterning, and deposit first metal formation pad and lead; Described pad is as lower electrode plate, and described lead is as the electric pole plate connecting line; Has the substrate surface dielectric layer deposition of pad, lead and passivation layer; The dielectric layer on etching electric pole plate connecting line surface is so that expose the electric pole plate connecting line; At described dielectric layer and electric pole plate connecting line surface deposition second metal level as electric pole plate; At described electric pole plate surface deposition second passivation layer; Described second passivation layer of etching, second metal level and dielectric layer form insulated trench.Method of the present invention can utilize the aluminum pad on device top layer and wiring to form MIM capacitor.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of metal-insulator-metal type (Metal-Insulator-Metal, MIM) capacitor and manufacture method thereof.
Background technology
Capacitor is widely used in the semiconductor integrated circuit as stored charge, coupling, filtering device.Usually in order to improve the performance of high-speed digital circuit and radio frequency (RF) circuit, need to adopt jumbo capacitor.Along with semiconductor fabrication enters the 90nm process node, device feature size constantly dwindles, and the high-performance between the element, highdensity connection not only interconnect in single interconnection layer, and will interconnect between multilayer.Therefore, multilayer interconnect structure is adopted in connection between the device in a large number, a plurality of interconnecting metal layers pile up mutually, interlayer dielectric places therebetween, in interlayer dielectric, form interconnected groove and connecting hole then, and fill interconnected groove and connecting hole to form the interconnecting metal lead of interconnection multiple layer metal layer with electric conducting material.But utilize each metal level and the required electric capacity of interlayer dielectric forming circuit of interconnection structure, these electric capacity that form between interconnection layer are called metal-insulator-metal type (MIM) capacitor.MIM capacitor is widely used in mixed signal devices and logical device for example in the devices such as analog digital conversion (ADC) or digital-to-analogue conversion (DAC) circuit, radio frequency (RF) circuit, analog circuit, high-power microprocessor (MPU) and DRAM cell, is used for the storage and the Circuit Matching of electric charge.
MIM capacitor of the prior art is formed at the upper strata of multilayered semiconductor interconnection structure mostly.Application number is that 200410084949.0 Chinese patent application has been introduced a kind of MIM capacitor and interconnection structure, it is to form mim capacitor structure at semiconductor device inside top dielectric layer and internal connecting layer, intraconnections is used to form the contact plunger of mim capacitor structure below, wherein contact plunger be mim capacitor structure bottom electrode with part.Form sunk area on the top of dielectric layer and fill metal material formation top electrode therein, and the material of top electrode and bottom electrode is identical.The method of this MIM capacitor that forms in interconnection layer is subjected to the influence of interconnection line layout, can not make full use of the space and form more MIM capacitor; And the manufacturing process complexity, to process conditions and equipment requirements than higher.
Summary of the invention
The object of the present invention is to provide a kind of MIM capacitor and manufacture method thereof, can utilize the aluminum pad on device top layer and wiring to form MIM capacitor.
For achieving the above object, the invention provides a kind of manufacture method of MIM capacitor, comprising:
Interconnection structure surface in Semiconductor substrate forms first passivation layer;
The described passivation layer of patterning, and deposit first metal formation pad layer and lead; Described pad layer is as lower electrode plate, and described lead is as the electric pole plate connecting line;
Has the substrate surface dielectric layer deposition of pad, lead and passivation layer;
The dielectric layer on etching electric pole plate connecting line surface is so that expose the electric pole plate connecting line;
At described dielectric layer and electric pole plate connecting line surface deposition second metal level as electric pole plate;
At described electric pole plate surface deposition second passivation layer;
Described second passivation layer of etching, second metal level and dielectric layer form insulated trench.
Comprise copper interconnecting line in the described interconnection structure, link to each other with lead with described pad.
The step of the described passivation layer of patterning comprises:
At described passivation layer surface painting photoresist layer;
Utilize photoetching processes such as exposure, development to form the photoresist figure;
With the photoresist figure is the described passivation layer of mask etching.
The material of described first and second passivation layers is silica, silicon nitride, silicon oxynitride or its combination.
Described first metal is aluminium or aluminium copper.
Described second metal is wherein a kind of or its combination of tantalum, tungsten, titanium, aluminium, tantalum nitride, titanium nitride.
Described second metal layer thickness is
The material of described dielectric layer is silicon nitride or silicon oxynitride, and thickness is
The manufacture method of another kind of MIM capacitor provided by the invention comprises:
Interconnection structure surface in Semiconductor substrate forms first passivation layer;
The described passivation layer of patterning, and deposit first metal formation plain conductor as the electric pole plate connecting line;
Form lower electrode plate in described passivation layer surface;
Has the substrate surface dielectric layer deposition of lead, passivation layer and lower electrode plate;
The dielectric layer on etching electric pole plate connecting line surface is so that expose the electric pole plate connecting line;
At described dielectric layer and electric pole plate connecting line surface deposition second metal level as electric pole plate;
At described electric pole plate surface deposition second passivation layer;
Described second passivation layer of etching, second metal level and dielectric layer form insulated trench.
Described plain conductor links to each other with copper interconnecting line in the described interconnection structure.
The step that forms lower electrode plate comprises:
At described passivation layer surface painting photoresist layer;
Utilize photoetching processes such as exposure, development to form the photoresist figure;
Plated metal aluminium also removes described photoresist figure.
The material of described first and second passivation layers is silica, silicon nitride, silicon oxynitride or its combination.
Described first metal is aluminium or aluminium copper.
Described second metal is wherein a kind of or its combination of tantalum, tungsten, titanium, aluminium, tantalum nitride, titanium nitride.
Described second metal layer thickness is
The material of described dielectric layer is silicon nitride or silicon oxynitride, and thickness is
Correspondingly, the present invention also provides a kind of MIM capacitor, it is characterized in that: comprise lower electrode plate and dielectric that forms on described lower electrode plate surface and the electric pole plate that forms in described dielectric layer surface that the pad by the interconnection structure surface constitutes; Described interconnection layer surface also has plain conductor and links to each other with described electric pole plate.
Described lower electrode plate metal is aluminium or aluminium copper.
Described electric pole plate metal is wherein a kind of or its combination of tantalum, tungsten, titanium, aluminium, tantalum nitride, titanium nitride.
The thickness of described electric pole plate metal is
The material of described dielectric layer is silicon nitride or silicon oxynitride, and thickness is
Described lower electrode plate is arranged in the passivation layer on interconnection structure surface.
Described lower electrode plate is positioned at the surface of the passivation layer on interconnection structure surface.
Described interconnection structure comprises interconnection layer and dielectric layer.
Compared with prior art, the present invention has the following advantages:
A large amount of metallic coppers that adopt are as interconnecting lead in the CMOS logical device.The pad of bonding mostly adopts metallic aluminium and top layer is used to go between.Except pad, top layer also has the connection that large-area, thicker interconnecting lead is used for the interconnection layer lead, and its material also adopts metallic aluminium.The pattern density of top layer aluminum pad layer is normally lower, has large stretch of white space, therefore can utilize the top-level metallic aluminum pad layer to form a large amount of MIM capacitor, so just can reduce the quantity of the MIM electric capacity that forms at the device inside copper interconnection layer, reduce the consumption in device inside space, helped further reducing device size.MIM capacitor of the present invention utilizes the lower electrode plate of aluminum pad layer as capacitor, form dielectric layer and electric pole plate by a masking process, and the pattern density of top layer is low relatively, required precision to mask plate is not high, therefore can simplify the manufacturing process of MIM capacitor, reduce manufacturing cost.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Identical parts have used identical Reference numeral in the accompanying drawing.Accompanying drawing is not painstakingly drawn in proportion, focuses on illustrating purport of the present invention.In the accompanying drawings, for clarity sake, amplified the thickness in layer and zone.
Fig. 1 to Fig. 9 is the generalized section according to the MIM capacitor manufacture method of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Fig. 1 to Fig. 9 is the generalized section according to the MIM capacitor manufacture method of the embodiment of the invention, and described schematic diagram is an example, and it should excessively not limit the scope of protection of the invention at this.At first as shown in Figure 1, MIM capacitor of the present invention is positioned at the top layer of semiconductor device multilayer interconnect structure.Multilayer interconnect structure comprises several layers dielectric layer and interconnection layer, and the interconnection line in the dielectric layer connects the plain conductor in each interconnection layer, only shows the uppermost interconnection structure that comprises dielectric layer and interconnection layer in the multilayer interconnection interconnection structure among Fig. 1.Be formed with plain conductor 110 in the interconnection layer 100 in interconnection structure, interconnection layer 100 surfaces have dielectric layer 120, utilize mosaic technology to form interconnection line in described dielectric layer 120.The MIM capacitor of disclosed embodiment is used for the RF device according to the present invention, therefore, can select to be used to form the metal material kind of interconnection line according to the frequency band of RF device.For example, if frequency band is 2.4GHz, can select metallic aluminium so.For the frequency band more than the 15GHz, adopt tungsten or copper, the material of interconnection line is preferably copper in the dielectric layer 120 of the embodiment of the invention.Interconnection line can be monometallic line 160 or a dual-damascene metal line 130 in the interlayer dielectric layer.Wherein metal connecting line 130 is connected to above-mentioned plain conductor 110 on the surface of semiconductor device sandwich construction.
Next as shown in Figure 2, utilize PECVD (plasma-reinforced chemical vapor deposition) process deposits passivation layer 140 on the surface of dielectric layer 120.The material of passivation layer 140 can show silicon oxide sio 2, for example a kind of or its combination among tetraethoxysilane (TEOS), silicon nitride SIN, the silicon oxynitride SION.At described passivation layer 140 surface coated photoresist layers, and utilizing photoetching processes such as exposure, development to form the photoresist figure, is the described passivation layer of mask etching with the photoresist figure then.Utilize physical vapor deposition (PVD) or sputter (sputtering) process deposits metallic aluminium or aluminium copper subsequently, wherein the content of copper is 0.5%.And remove the photoresist figure, form pad layer 150, MIM bottom electrode and the aluminum conductor 180 that is connected the MIM top electrode.
In ensuing processing step, as shown in Figure 3, at passivation layer 140, pad 150 and 170 and lead 180 surfaces, the dielectric layer 190 of deposit MIM capacitor.The material of described dielectric layer is silicon nitride or silicon oxynitride.Also can other high dielectric constant material in other embodiment of the present invention.The method of chemical vapor deposition (CVD) is adopted in the formation of dielectric layer 190, is preferably plasma-reinforced chemical vapor deposition (PECVD) technology.Its thickness is decided according to the designing requirement of capacitance, for example
Those skilled in the art do not need to pay creative work and just can determine, and are not purpose of the present invention and content, therefore do not give unnecessary details.
Next, at the surface coated photoresist of dielectric layer 190 and utilize the described photoresist of conventional photoetching process patterning to form the photoresist figure, be used for the position of positioning lead 180.Utilize above-mentioned figure to be mask, adopt the dielectric layer 190 on plasma etching industrial or reactive ion etching (RIE) technology etching lead 180 surfaces, thereby expose lead 180, as shown in Figure 4.
In ensuing processing step, as shown in Figure 5, on dielectric layer 190 and lead 180 surfaces, utilize ald (ALD), physical vapor deposition (PVD), sputter or chemical vapor deposition (CVD) technology, be preferably the PVD depositing operation, deposited metal 200.The material of described metal level 200 is wherein a kind of or its combination of tantalum Ta, tungsten W, titanium Ti, aluminium Al, tantalum nitride TaN, titanium nitride TiN, and thickness is
Metal level 200 is electrically connected with lead 180, is connected to the lower interconnection layer by lead 180.
Subsequently, as shown in Figure 6,, utilize ald (ALD), chemical vapor deposition (CVD) technology, be preferably plasma-reinforced chemical vapor deposition (PECVD) technology, another layer of deposit passivation layer 210 on metal level 200 surfaces.Utilize photoresist figure mask to adopt plasma etching industrial or reactive ion etching (RIE) technology etching passivation layer 210, metal level 200 and dielectric layer 190 then, form insulated trench 220, as shown in Figure 7.In the present embodiment, the etching of passivation layer 210, metal level 200 and dielectric layer 190 adopts plasma etching, the etchant gas that feeds in reative cell is to comprise for example mist of hydrogen Ar, neon Ne of SF6, CHF3, CF4, chlorine Cl2, oxygen O2, nitrogen N 2, helium He and other inert gas, flow 100-400sccm, underlayer temperature is controlled between 20 ℃ and 90 ℃, chamber pressure is 4-20mTorr, plasma source radio frequency power output 1500W-2000W.The surface that passivation layer 140 is exposed in insulated trench 220 bottoms that etching forms.Insulated trench 220 is used for MIM capacitor and other MIM capacitor or pad are kept apart.
Next as shown in Figure 8, MIM capacitor manufacture method of the present invention is utilized the lower electrode plate of the aluminum pad layer 170 of device surface formation as MIM capacitor, has made full use of the space of device surface, can form a large amount of MIM capacitor.Other pad is 150 pads that still can be used as the bonding that is used to go between for example.Among Fig. 8, after the etching insulated trench 220, continue to carry out passivation layer 210, metal level 200 and the dielectric layer 190 on an etching technics etching pad 150 surfaces, with exposed pad 150.In other embodiments, the etching of the passivation layer 210 on pad 150 surfaces, metal level 200 and dielectric layer 190 can be carried out simultaneously with etching insulated trench 220.
In another embodiment of the manufacture method of MIM capacitor of the present invention, as shown in Figure 9, form passivation layers 140 on dielectric layer 120 surfaces of the interconnection structure of Semiconductor substrate; The described passivation layer 140 of patterning, and plated metal aluminium then forms plain conductor 180 as the electric pole plate connecting line; On described passivation layer 140 surfaces, plated metal aluminium forms lower electrode plate 170 then; And in substrate surface dielectric layer deposition 190 with electric pole plate connecting line 180, passivation layer 140 and lower electrode plate 170; The dielectric layer 190 on etching electric pole plate connecting line 180 surfaces is so that expose electric pole plate connecting line 180; Subsequently at described dielectric layer 190 and electric pole plate connecting line 180 surface deposition metal levels 200 as electric pole plate.Then at described another passivation layer 210 of electric pole plate 200 surface depositions; The described passivation layer 210 of etching, metal level 200 and dielectric layer 190 form insulated trench 220.Wherein plain conductor 180 (electric pole plate connecting line) links to each other with copper interconnecting line in the described interconnection layer.The step that forms lower electrode plate 170 comprises: at described passivation layer 140 surface coated photoresist layers; Utilize photoetching processes such as exposure, development to form the photoresist figure; Plated metal aluminium also removes described photoresist figure.The material of passivation layer is silica, silicon nitride, silicon oxynitride or its combination.The material of metal level 200 is wherein a kind of or its combination of tantalum, tungsten, titanium, aluminium, tantalum nitride, titanium nitride, and thickness is
The material of dielectric layer 190 is silicon nitride or silicon oxynitride, and thickness is
MIM capacitor of the present invention as shown in Figure 8, comprise the lower electrode plate 170 that the pad by dielectric layer 120 surfaces of interconnection structure constitutes, with the dielectric 190 that forms on described lower electrode plate 170 surfaces, and the electric pole plate 200 that forms on described dielectric layer 190 surfaces; Dielectric layer 120 surfaces of described interconnection structure also have plain conductor 180 and link to each other with described electric pole plate 200.Wherein, lower electrode plate 170 is arranged in the passivation layer 140 on dielectric layer 120 surfaces, and in other embodiments, lower electrode plate 170 can also be positioned at the surface of the passivation layer 140 on dielectric layer 120 surfaces, as shown in Figure 9.The material of lower electrode plate 170 is an aluminium; The metal of electric pole plate 200 is wherein a kind of or its combination of tantalum, tungsten, titanium, aluminium, tantalum nitride, titanium nitride, and thickness is
The material of dielectric layer 190 is silicon nitride or silicon oxynitride, and thickness is
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (24)
1, a kind of manufacture method of MIM capacitor comprises:
Interconnection structure surface in Semiconductor substrate forms first passivation layer;
Described first passivation layer of patterning, deposition first metal forms pad layer and lead in the groove that described first passivation layer of patterning forms; Described pad layer is as lower electrode plate, and described lead is as the electric pole plate connecting line;
In substrate surface dielectric layer deposition with pad, lead and first passivation layer;
The dielectric layer on etching electric pole plate connecting line surface is so that expose the electric pole plate connecting line;
At described dielectric layer and electric pole plate connecting line surface deposition second metal level as electric pole plate;
At described electric pole plate surface deposition second passivation layer;
Described second passivation layer of etching, second metal level and dielectric layer form insulated trench.
2, the method for claim 1 is characterized in that: comprise copper interconnecting line in the described interconnection structure, link to each other with lead with described pad.
3, the method for claim 1 is characterized in that: the step of described first passivation layer of patterning comprises:
At the described first passivation layer surface painting photoresist layer;
Utilize photoetching processes such as exposure, development to form the photoresist figure;
With the photoresist figure is described first passivation layer of mask etching.
4, the method for claim 1 is characterized in that: the material of described first and second passivation layers is silica, silicon nitride, silicon oxynitride or its combination.
5, the method for claim 1 is characterized in that: described first metal is aluminium or aluminium copper.
6, the method for claim 1 is characterized in that: described second metal is wherein a kind of or its combination of tantalum, tungsten, titanium, aluminium, tantalum nitride, titanium nitride.
7, method as claimed in claim 6 is characterized in that: described second metal layer thickness is 100～
8, the method for claim 1 is characterized in that: the material of described dielectric layer is silicon nitride or silicon oxynitride, thickness is 200～
9, a kind of manufacture method of MIM capacitor comprises:
Interconnection structure surface in Semiconductor substrate forms first passivation layer;
Described first passivation layer of patterning, deposition first metal forms plain conductor as the electric pole plate connecting line in the groove that described first passivation layer of patterning forms;
At the lower electrode plate of described first passivation layer surface formation as the top layer pad layer;
Has the substrate surface dielectric layer deposition of lead, first passivation layer and lower electrode plate;
The dielectric layer on etching electric pole plate connecting line surface is so that expose the electric pole plate connecting line;
At described dielectric layer and electric pole plate connecting line surface deposition second metal level as electric pole plate;
At described electric pole plate surface deposition second passivation layer;
Described second passivation layer of etching, second metal level and dielectric layer form insulated trench.
10, method as claimed in claim 9 is characterized in that: described plain conductor links to each other with copper interconnecting line in the described interconnection structure.
11, method as claimed in claim 9 is characterized in that: the step that forms lower electrode plate comprises:
At the described first passivation layer surface painting photoresist layer;
Utilize photoetching processes such as exposure, development to form the photoresist figure;
Plated metal aluminium also removes described photoresist figure.
12, method as claimed in claim 9 is characterized in that: the material of described first and second passivation layers is silica, silicon nitride, silicon oxynitride or its combination.
13, method as claimed in claim 9 is characterized in that: described first metal is aluminium or aluminium copper.
14, method as claimed in claim 9 is characterized in that: described second metal is wherein a kind of or its combination of tantalum, tungsten, titanium, aluminium, tantalum nitride, titanium nitride.
15, method as claimed in claim 14 is characterized in that: described second metal layer thickness is 100～
16, method as claimed in claim 9 is characterized in that: the material of described dielectric layer is silicon nitride or silicon oxynitride, thickness is 200～
17, a kind of MIM capacitor, it is characterized in that: comprise lower electrode plate and dielectric layer that forms on described lower electrode plate surface and the electric pole plate that forms in described dielectric layer surface that the pad by the interconnection structure surface of Semiconductor substrate constitutes; Described interconnection structure surface also has plain conductor and links to each other with described electric pole plate.
18, MIM capacitor as claimed in claim 17 is characterized in that: described lower electrode plate metal is aluminium or aluminium copper.
19, MIM capacitor as claimed in claim 17 is characterized in that: described electric pole plate metal is wherein a kind of or its combination of tantalum, tungsten, titanium, aluminium, tantalum nitride, titanium nitride.
20, MIM capacitor as claimed in claim 19 is characterized in that: the thickness of described electric pole plate metal is 100～
21, MIM capacitor as claimed in claim 17 is characterized in that: the material of described dielectric layer is silicon nitride or silicon oxynitride, thickness is 200～
22, MIM capacitor as claimed in claim 17 is characterized in that: described lower electrode plate is arranged in the passivation layer on interconnection structure surface.
23, MIM capacitor as claimed in claim 17 is characterized in that: described lower electrode plate is positioned at the surface of the passivation layer on interconnection structure surface.
24, MIM capacitor as claimed in claim 17 is characterized in that: described interconnection structure comprises interconnection layer and dielectric layer.
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| CNB2007100402368A CN100539016C (en) | 2007-04-24 | 2007-04-24 | MIM capacitor and manufacture method thereof |
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| CNB2007100402368A CN100539016C (en) | 2007-04-24 | 2007-04-24 | MIM capacitor and manufacture method thereof |
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| CN101882587B (en) * | 2009-05-04 | 2012-03-28 | 中芯国际集成电路制造(北京)有限公司 | Structure for achieving wire bonding and packaging and production method thereof |
| CN102148185B (en) * | 2010-02-09 | 2013-05-01 | 中芯国际集成电路制造(上海)有限公司 | Method for forming interconnection structure |
| CN102148186B (en) * | 2010-02-09 | 2013-05-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102148188B (en) * | 2010-02-09 | 2016-02-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN102446917B (en) * | 2011-11-15 | 2014-02-05 | 上海华力微电子有限公司 | Multilayer MOM capacitor and manufacturing method thereof |
| US9165821B2 (en) * | 2013-12-23 | 2015-10-20 | Infineon Technologies Ag | Method for providing a self-aligned pad protection in a semiconductor device |
| CN103762206A (en) * | 2014-01-07 | 2014-04-30 | 申宇慈 | Electronic device interconnection body |
| CN108766953B (en) * | 2018-05-31 | 2021-01-01 | 德淮半导体有限公司 | Semiconductor device and method of forming the same |
| US10910304B2 (en) | 2019-01-24 | 2021-02-02 | Globalfoundries U.S. Inc. | Tight pitch wirings and capacitor(s) |
| CN111366618B (en) * | 2020-04-01 | 2022-07-29 | 上海华虹宏力半导体制造有限公司 | Temperature and humidity sensor and manufacturing method thereof |
| CN117153813A (en) * | 2022-05-24 | 2023-12-01 | 屹世半导体(上海)有限公司 | High-voltage isolation device and manufacturing method thereof |
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Effective date of registration: 20111117 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |